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CoolPi-Armbian-Rockchip-RK3.../tools/perf/pmu-events/arch/x86/knightslanding/memory.json

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[
{
"BriefDescription": "Counts the number of times the machine clears due to memory ordering hazards",
"Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800044",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000044",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800044",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from MCDRAM (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600044",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400044",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200044",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181803091",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101003091",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080803091",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from MCDRAM (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180603091",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100403091",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080203091",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000070",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800070",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses from MCDRAM (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600070",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400070",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200070",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses from DDR (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01818032f7",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01010032f7",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00808032f7",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses from MCDRAM (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01806032f7",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01004032f7",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00802032f7",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses from DDR (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181808000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101008000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080808000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses from MCDRAM (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180608000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100408000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080208000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from DDR (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800022",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000022",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800022",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from MCDRAM (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600022",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400022",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200022",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from DDR (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800400",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000400",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800400",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600400",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400400",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200400",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800004",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000004",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800004",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600004",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400004",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200004",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800001",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000001",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800001",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600001",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400001",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200001",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from DDR (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800002",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000002",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800002",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600002",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400002",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200002",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from DDR (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800080",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000080",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800080",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from MCDRAM (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600080",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400080",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200080",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000020080",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR",
"MSRIndex": "0x1a7",
"MSRValue": "0x0101000100",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR",
"MSRIndex": "0x1a7",
"MSRValue": "0x0080800100",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM",
"MSRIndex": "0x1a7",
"MSRValue": "0x0180600100",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR",
"MSRIndex": "0x1a7",
"MSRValue": "0x0100400100",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR",
"MSRIndex": "0x1a7",
"MSRValue": "0x0080200100",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses from DDR (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181802000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101002000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080802000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100402000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080202000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses from DDR (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800040",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000040",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800040",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400040",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200040",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800020",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000020",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800020",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600020",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400020",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200020",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000020020",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses from DDR (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181801000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101001000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080801000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses from MCDRAM (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180601000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100401000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080201000",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from DDR (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800200",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000200",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800200",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from MCDRAM (local and far)",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600200",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400200",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Local.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200200",
"Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
}
]
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