101 lines
3.5 KiB
C
101 lines
3.5 KiB
C
/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "gf100.h"
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#include "ctxgf100.h"
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#include <subdev/acr.h>
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#include <nvif/class.h>
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#include <nvfw/flcn.h>
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static const struct nvkm_acr_lsf_func
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gp10b_gr_gpccs_acr = {
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.flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD,
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.bld_size = sizeof(struct flcn_bl_dmem_desc),
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.bld_write = gm20b_gr_acr_bld_write,
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.bld_patch = gm20b_gr_acr_bld_patch,
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};
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static const struct gf100_gr_func
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gp10b_gr = {
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.oneinit_tiles = gm200_gr_oneinit_tiles,
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.oneinit_sm_id = gm200_gr_oneinit_sm_id,
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.init = gf100_gr_init,
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.init_gpc_mmu = gm200_gr_init_gpc_mmu,
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.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
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.init_zcull = gf117_gr_init_zcull,
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.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
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.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
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.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
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.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
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.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
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.init_419cc0 = gf100_gr_init_419cc0,
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.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
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.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
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.init_504430 = gm107_gr_init_504430,
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.init_shader_exceptions = gp100_gr_init_shader_exceptions,
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.trap_mp = gf100_gr_trap_mp,
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.rops = gm200_gr_rops,
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.gpc_nr = 1,
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.tpc_nr = 2,
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.ppc_nr = 1,
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.grctx = &gp100_grctx,
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.zbc = &gp100_gr_zbc,
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.sclass = {
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{ -1, -1, FERMI_TWOD_A },
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{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
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{ -1, -1, PASCAL_A, &gf100_fermi },
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{ -1, -1, PASCAL_COMPUTE_A },
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{}
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}
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};
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
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MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/sw_method_init.bin");
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#endif
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static const struct gf100_gr_fwif
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gp10b_gr_fwif[] = {
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{ 0, gm200_gr_load, &gp10b_gr, &gm20b_gr_fecs_acr, &gp10b_gr_gpccs_acr },
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{ -1, gm200_gr_nofw },
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{}
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};
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int
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gp10b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
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{
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return gf100_gr_new_(gp10b_gr_fwif, device, type, inst, pgr);
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}
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