700 lines
19 KiB
C
700 lines
19 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "gf100.h"
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#include "changf100.h"
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#include <core/client.h>
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#include <core/enum.h>
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#include <core/gpuobj.h>
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#include <subdev/bar.h>
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#include <subdev/fault.h>
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#include <engine/sw.h>
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#include <nvif/class.h>
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static void
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gf100_fifo_uevent_init(struct nvkm_fifo *fifo)
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{
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struct nvkm_device *device = fifo->engine.subdev.device;
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nvkm_mask(device, 0x002140, 0x80000000, 0x80000000);
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}
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static void
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gf100_fifo_uevent_fini(struct nvkm_fifo *fifo)
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{
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struct nvkm_device *device = fifo->engine.subdev.device;
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nvkm_mask(device, 0x002140, 0x80000000, 0x00000000);
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}
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void
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gf100_fifo_runlist_commit(struct gf100_fifo *fifo)
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{
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struct gf100_fifo_chan *chan;
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_memory *cur;
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int nr = 0;
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int target;
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mutex_lock(&fifo->base.mutex);
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cur = fifo->runlist.mem[fifo->runlist.active];
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fifo->runlist.active = !fifo->runlist.active;
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nvkm_kmap(cur);
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list_for_each_entry(chan, &fifo->chan, head) {
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nvkm_wo32(cur, (nr * 8) + 0, chan->base.chid);
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nvkm_wo32(cur, (nr * 8) + 4, 0x00000004);
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nr++;
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}
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nvkm_done(cur);
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switch (nvkm_memory_target(cur)) {
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case NVKM_MEM_TARGET_VRAM: target = 0; break;
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case NVKM_MEM_TARGET_NCOH: target = 3; break;
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default:
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mutex_unlock(&fifo->base.mutex);
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WARN_ON(1);
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return;
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}
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nvkm_wr32(device, 0x002270, (nvkm_memory_addr(cur) >> 12) |
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(target << 28));
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nvkm_wr32(device, 0x002274, 0x01f00000 | nr);
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if (wait_event_timeout(fifo->runlist.wait,
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!(nvkm_rd32(device, 0x00227c) & 0x00100000),
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msecs_to_jiffies(2000)) == 0)
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nvkm_error(subdev, "runlist update timeout\n");
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mutex_unlock(&fifo->base.mutex);
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}
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void
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gf100_fifo_runlist_remove(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan)
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{
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mutex_lock(&fifo->base.mutex);
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list_del_init(&chan->head);
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mutex_unlock(&fifo->base.mutex);
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}
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void
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gf100_fifo_runlist_insert(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan)
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{
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mutex_lock(&fifo->base.mutex);
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list_add_tail(&chan->head, &fifo->chan);
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mutex_unlock(&fifo->base.mutex);
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}
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static struct nvkm_engine *
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gf100_fifo_id_engine(struct nvkm_fifo *fifo, int engi)
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{
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enum nvkm_subdev_type type;
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int inst;
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switch (engi) {
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case GF100_FIFO_ENGN_GR : type = NVKM_ENGINE_GR ; inst = 0; break;
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case GF100_FIFO_ENGN_MSPDEC: type = NVKM_ENGINE_MSPDEC; inst = 0; break;
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case GF100_FIFO_ENGN_MSPPP : type = NVKM_ENGINE_MSPPP ; inst = 0; break;
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case GF100_FIFO_ENGN_MSVLD : type = NVKM_ENGINE_MSVLD ; inst = 0; break;
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case GF100_FIFO_ENGN_CE0 : type = NVKM_ENGINE_CE ; inst = 0; break;
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case GF100_FIFO_ENGN_CE1 : type = NVKM_ENGINE_CE ; inst = 1; break;
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case GF100_FIFO_ENGN_SW : type = NVKM_ENGINE_SW ; inst = 0; break;
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default:
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WARN_ON(1);
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return NULL;
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}
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return nvkm_device_engine(fifo->engine.subdev.device, type, inst);
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}
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static int
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gf100_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine)
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{
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switch (engine->subdev.type) {
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case NVKM_ENGINE_GR : return GF100_FIFO_ENGN_GR;
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case NVKM_ENGINE_MSPDEC: return GF100_FIFO_ENGN_MSPDEC;
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case NVKM_ENGINE_MSPPP : return GF100_FIFO_ENGN_MSPPP;
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case NVKM_ENGINE_MSVLD : return GF100_FIFO_ENGN_MSVLD;
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case NVKM_ENGINE_CE : return GF100_FIFO_ENGN_CE0 + engine->subdev.inst;
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case NVKM_ENGINE_SW : return GF100_FIFO_ENGN_SW;
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default:
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WARN_ON(1);
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return -1;
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}
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}
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static void
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gf100_fifo_recover_work(struct work_struct *w)
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{
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struct gf100_fifo *fifo = container_of(w, typeof(*fifo), recover.work);
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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struct nvkm_engine *engine;
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unsigned long flags;
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u32 engm, engn, todo;
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spin_lock_irqsave(&fifo->base.lock, flags);
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engm = fifo->recover.mask;
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fifo->recover.mask = 0ULL;
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spin_unlock_irqrestore(&fifo->base.lock, flags);
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nvkm_mask(device, 0x002630, engm, engm);
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for (todo = engm; engn = __ffs(todo), todo; todo &= ~BIT_ULL(engn)) {
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if ((engine = gf100_fifo_id_engine(&fifo->base, engn))) {
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nvkm_subdev_fini(&engine->subdev, false);
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WARN_ON(nvkm_subdev_init(&engine->subdev));
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}
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}
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gf100_fifo_runlist_commit(fifo);
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nvkm_wr32(device, 0x00262c, engm);
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nvkm_mask(device, 0x002630, engm, 0x00000000);
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}
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static void
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gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine,
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struct gf100_fifo_chan *chan)
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{
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 chid = chan->base.chid;
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int engi = gf100_fifo_engine_id(&fifo->base, engine);
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nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n",
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engine->subdev.name, chid);
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assert_spin_locked(&fifo->base.lock);
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nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000);
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list_del_init(&chan->head);
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chan->killed = true;
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if (engi >= 0 && engi != GF100_FIFO_ENGN_SW)
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fifo->recover.mask |= BIT(engi);
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schedule_work(&fifo->recover.work);
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nvkm_fifo_kevent(&fifo->base, chid);
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}
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static const struct nvkm_enum
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gf100_fifo_fault_engine[] = {
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{ 0x00, "PGRAPH", NULL, NVKM_ENGINE_GR },
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{ 0x03, "PEEPHOLE", NULL, NVKM_ENGINE_IFB },
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{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
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{ 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM },
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{ 0x07, "PFIFO", NULL, NVKM_ENGINE_FIFO },
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{ 0x10, "PMSVLD", NULL, NVKM_ENGINE_MSVLD },
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{ 0x11, "PMSPPP", NULL, NVKM_ENGINE_MSPPP },
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{ 0x13, "PCOUNTER" },
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{ 0x14, "PMSPDEC", NULL, NVKM_ENGINE_MSPDEC },
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{ 0x15, "PCE0", NULL, NVKM_ENGINE_CE, 0 },
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{ 0x16, "PCE1", NULL, NVKM_ENGINE_CE, 1 },
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{ 0x17, "PMU" },
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{}
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};
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static const struct nvkm_enum
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gf100_fifo_fault_reason[] = {
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{ 0x00, "PT_NOT_PRESENT" },
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{ 0x01, "PT_TOO_SHORT" },
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{ 0x02, "PAGE_NOT_PRESENT" },
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{ 0x03, "VM_LIMIT_EXCEEDED" },
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{ 0x04, "NO_CHANNEL" },
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{ 0x05, "PAGE_SYSTEM_ONLY" },
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{ 0x06, "PAGE_READ_ONLY" },
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{ 0x0a, "COMPRESSED_SYSRAM" },
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{ 0x0c, "INVALID_STORAGE_TYPE" },
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{}
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};
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static const struct nvkm_enum
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gf100_fifo_fault_hubclient[] = {
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{ 0x01, "PCOPY0" },
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{ 0x02, "PCOPY1" },
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{ 0x04, "DISPATCH" },
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{ 0x05, "CTXCTL" },
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{ 0x06, "PFIFO" },
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{ 0x07, "BAR_READ" },
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{ 0x08, "BAR_WRITE" },
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{ 0x0b, "PVP" },
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{ 0x0c, "PMSPPP" },
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{ 0x0d, "PMSVLD" },
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{ 0x11, "PCOUNTER" },
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{ 0x12, "PMU" },
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{ 0x14, "CCACHE" },
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{ 0x15, "CCACHE_POST" },
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{}
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};
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static const struct nvkm_enum
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gf100_fifo_fault_gpcclient[] = {
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{ 0x01, "TEX" },
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{ 0x0c, "ESETUP" },
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{ 0x0e, "CTXCTL" },
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{ 0x0f, "PROP" },
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{}
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};
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static void
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gf100_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info)
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{
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struct gf100_fifo *fifo = gf100_fifo(base);
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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const struct nvkm_enum *er, *eu, *ec;
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struct nvkm_engine *engine = NULL;
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struct nvkm_fifo_chan *chan;
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unsigned long flags;
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char gpcid[8] = "";
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er = nvkm_enum_find(gf100_fifo_fault_reason, info->reason);
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eu = nvkm_enum_find(gf100_fifo_fault_engine, info->engine);
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if (info->hub) {
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ec = nvkm_enum_find(gf100_fifo_fault_hubclient, info->client);
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} else {
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ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, info->client);
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snprintf(gpcid, sizeof(gpcid), "GPC%d/", info->gpc);
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}
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if (eu && eu->data2) {
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switch (eu->data2) {
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case NVKM_SUBDEV_BAR:
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nvkm_bar_bar1_reset(device);
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break;
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case NVKM_SUBDEV_INSTMEM:
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nvkm_bar_bar2_reset(device);
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break;
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case NVKM_ENGINE_IFB:
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nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
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break;
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default:
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engine = nvkm_device_engine(device, eu->data2, eu->inst);
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break;
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}
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}
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chan = nvkm_fifo_chan_inst(&fifo->base, info->inst, &flags);
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nvkm_error(subdev,
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"%s fault at %010llx engine %02x [%s] client %02x [%s%s] "
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"reason %02x [%s] on channel %d [%010llx %s]\n",
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info->access ? "write" : "read", info->addr,
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info->engine, eu ? eu->name : "",
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info->client, gpcid, ec ? ec->name : "",
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info->reason, er ? er->name : "", chan ? chan->chid : -1,
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info->inst, chan ? chan->object.client->name : "unknown");
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if (engine && chan)
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gf100_fifo_recover(fifo, engine, (void *)chan);
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nvkm_fifo_chan_put(&fifo->base, flags, &chan);
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}
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static const struct nvkm_enum
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gf100_fifo_sched_reason[] = {
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{ 0x0a, "CTXSW_TIMEOUT" },
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{}
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};
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static void
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gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo)
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{
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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struct nvkm_engine *engine;
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struct gf100_fifo_chan *chan;
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unsigned long flags;
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u32 engn;
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spin_lock_irqsave(&fifo->base.lock, flags);
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for (engn = 0; engn < 6; engn++) {
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u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04));
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u32 busy = (stat & 0x80000000);
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u32 save = (stat & 0x00100000); /* maybe? */
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u32 unk0 = (stat & 0x00040000);
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u32 unk1 = (stat & 0x00001000);
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u32 chid = (stat & 0x0000007f);
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(void)save;
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if (busy && unk0 && unk1) {
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list_for_each_entry(chan, &fifo->chan, head) {
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if (chan->base.chid == chid) {
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engine = gf100_fifo_id_engine(&fifo->base, engn);
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if (!engine)
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break;
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gf100_fifo_recover(fifo, engine, chan);
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break;
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}
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}
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}
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}
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spin_unlock_irqrestore(&fifo->base.lock, flags);
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}
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static void
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gf100_fifo_intr_sched(struct gf100_fifo *fifo)
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{
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 intr = nvkm_rd32(device, 0x00254c);
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u32 code = intr & 0x000000ff;
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const struct nvkm_enum *en;
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en = nvkm_enum_find(gf100_fifo_sched_reason, code);
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nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : "");
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switch (code) {
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case 0x0a:
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gf100_fifo_intr_sched_ctxsw(fifo);
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break;
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default:
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break;
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}
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}
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void
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gf100_fifo_intr_fault(struct nvkm_fifo *fifo, int unit)
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{
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struct nvkm_device *device = fifo->engine.subdev.device;
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u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
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u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
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u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
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u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));
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struct nvkm_fault_data info;
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info.inst = (u64)inst << 12;
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info.addr = ((u64)vahi << 32) | valo;
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info.time = 0;
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info.engine = unit;
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info.valid = 1;
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info.gpc = (type & 0x1f000000) >> 24;
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info.client = (type & 0x00001f00) >> 8;
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info.access = (type & 0x00000080) >> 7;
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info.hub = (type & 0x00000040) >> 6;
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info.reason = (type & 0x0000000f);
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nvkm_fifo_fault(fifo, &info);
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}
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static const struct nvkm_bitfield
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gf100_fifo_pbdma_intr[] = {
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/* { 0x00008000, "" } seen with null ib push */
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{ 0x00200000, "ILLEGAL_MTHD" },
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{ 0x00800000, "EMPTY_SUBC" },
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{}
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};
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static void
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gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit)
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{
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000));
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u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000));
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u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000));
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u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f;
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u32 subc = (addr & 0x00070000) >> 16;
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u32 mthd = (addr & 0x00003ffc);
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struct nvkm_fifo_chan *chan;
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unsigned long flags;
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u32 show= stat;
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char msg[128];
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if (stat & 0x00800000) {
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if (device->sw) {
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if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data))
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show &= ~0x00800000;
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}
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}
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if (show) {
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nvkm_snprintbf(msg, sizeof(msg), gf100_fifo_pbdma_intr, show);
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chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags);
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nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%010llx %s] "
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"subc %d mthd %04x data %08x\n",
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unit, show, msg, chid, chan ? chan->inst->addr : 0,
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chan ? chan->object.client->name : "unknown",
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subc, mthd, data);
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nvkm_fifo_chan_put(&fifo->base, flags, &chan);
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}
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nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008);
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nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat);
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}
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static void
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gf100_fifo_intr_runlist(struct gf100_fifo *fifo)
|
|
{
|
|
struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
u32 intr = nvkm_rd32(device, 0x002a00);
|
|
|
|
if (intr & 0x10000000) {
|
|
wake_up(&fifo->runlist.wait);
|
|
nvkm_wr32(device, 0x002a00, 0x10000000);
|
|
intr &= ~0x10000000;
|
|
}
|
|
|
|
if (intr) {
|
|
nvkm_error(subdev, "RUNLIST %08x\n", intr);
|
|
nvkm_wr32(device, 0x002a00, intr);
|
|
}
|
|
}
|
|
|
|
static void
|
|
gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn)
|
|
{
|
|
struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04));
|
|
u32 inte = nvkm_rd32(device, 0x002628);
|
|
u32 unkn;
|
|
|
|
nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr);
|
|
|
|
for (unkn = 0; unkn < 8; unkn++) {
|
|
u32 ints = (intr >> (unkn * 0x04)) & inte;
|
|
if (ints & 0x1) {
|
|
nvkm_fifo_uevent(&fifo->base);
|
|
ints &= ~1;
|
|
}
|
|
if (ints) {
|
|
nvkm_error(subdev, "ENGINE %d %d %01x",
|
|
engn, unkn, ints);
|
|
nvkm_mask(device, 0x002628, ints, 0);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
gf100_fifo_intr_engine(struct gf100_fifo *fifo)
|
|
{
|
|
struct nvkm_device *device = fifo->base.engine.subdev.device;
|
|
u32 mask = nvkm_rd32(device, 0x0025a4);
|
|
while (mask) {
|
|
u32 unit = __ffs(mask);
|
|
gf100_fifo_intr_engine_unit(fifo, unit);
|
|
mask &= ~(1 << unit);
|
|
}
|
|
}
|
|
|
|
static void
|
|
gf100_fifo_intr(struct nvkm_fifo *base)
|
|
{
|
|
struct gf100_fifo *fifo = gf100_fifo(base);
|
|
struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
u32 mask = nvkm_rd32(device, 0x002140);
|
|
u32 stat = nvkm_rd32(device, 0x002100) & mask;
|
|
|
|
if (stat & 0x00000001) {
|
|
u32 intr = nvkm_rd32(device, 0x00252c);
|
|
nvkm_warn(subdev, "INTR 00000001: %08x\n", intr);
|
|
nvkm_wr32(device, 0x002100, 0x00000001);
|
|
stat &= ~0x00000001;
|
|
}
|
|
|
|
if (stat & 0x00000100) {
|
|
gf100_fifo_intr_sched(fifo);
|
|
nvkm_wr32(device, 0x002100, 0x00000100);
|
|
stat &= ~0x00000100;
|
|
}
|
|
|
|
if (stat & 0x00010000) {
|
|
u32 intr = nvkm_rd32(device, 0x00256c);
|
|
nvkm_warn(subdev, "INTR 00010000: %08x\n", intr);
|
|
nvkm_wr32(device, 0x002100, 0x00010000);
|
|
stat &= ~0x00010000;
|
|
}
|
|
|
|
if (stat & 0x01000000) {
|
|
u32 intr = nvkm_rd32(device, 0x00258c);
|
|
nvkm_warn(subdev, "INTR 01000000: %08x\n", intr);
|
|
nvkm_wr32(device, 0x002100, 0x01000000);
|
|
stat &= ~0x01000000;
|
|
}
|
|
|
|
if (stat & 0x10000000) {
|
|
u32 mask = nvkm_rd32(device, 0x00259c);
|
|
while (mask) {
|
|
u32 unit = __ffs(mask);
|
|
gf100_fifo_intr_fault(&fifo->base, unit);
|
|
nvkm_wr32(device, 0x00259c, (1 << unit));
|
|
mask &= ~(1 << unit);
|
|
}
|
|
stat &= ~0x10000000;
|
|
}
|
|
|
|
if (stat & 0x20000000) {
|
|
u32 mask = nvkm_rd32(device, 0x0025a0);
|
|
while (mask) {
|
|
u32 unit = __ffs(mask);
|
|
gf100_fifo_intr_pbdma(fifo, unit);
|
|
nvkm_wr32(device, 0x0025a0, (1 << unit));
|
|
mask &= ~(1 << unit);
|
|
}
|
|
stat &= ~0x20000000;
|
|
}
|
|
|
|
if (stat & 0x40000000) {
|
|
gf100_fifo_intr_runlist(fifo);
|
|
stat &= ~0x40000000;
|
|
}
|
|
|
|
if (stat & 0x80000000) {
|
|
gf100_fifo_intr_engine(fifo);
|
|
stat &= ~0x80000000;
|
|
}
|
|
|
|
if (stat) {
|
|
nvkm_error(subdev, "INTR %08x\n", stat);
|
|
nvkm_mask(device, 0x002140, stat, 0x00000000);
|
|
nvkm_wr32(device, 0x002100, stat);
|
|
}
|
|
}
|
|
|
|
static int
|
|
gf100_fifo_oneinit(struct nvkm_fifo *base)
|
|
{
|
|
struct gf100_fifo *fifo = gf100_fifo(base);
|
|
struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
struct nvkm_vmm *bar = nvkm_bar_bar1_vmm(device);
|
|
int ret;
|
|
|
|
/* Determine number of PBDMAs by checking valid enable bits. */
|
|
nvkm_wr32(device, 0x002204, 0xffffffff);
|
|
fifo->pbdma_nr = hweight32(nvkm_rd32(device, 0x002204));
|
|
nvkm_debug(subdev, "%d PBDMA(s)\n", fifo->pbdma_nr);
|
|
|
|
|
|
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
|
|
false, &fifo->runlist.mem[0]);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
|
|
false, &fifo->runlist.mem[1]);
|
|
if (ret)
|
|
return ret;
|
|
|
|
init_waitqueue_head(&fifo->runlist.wait);
|
|
|
|
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 0x1000,
|
|
0x1000, false, &fifo->user.mem);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nvkm_vmm_get(bar, 12, nvkm_memory_size(fifo->user.mem),
|
|
&fifo->user.bar);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return nvkm_memory_map(fifo->user.mem, 0, bar, fifo->user.bar, NULL, 0);
|
|
}
|
|
|
|
static void
|
|
gf100_fifo_fini(struct nvkm_fifo *base)
|
|
{
|
|
struct gf100_fifo *fifo = gf100_fifo(base);
|
|
flush_work(&fifo->recover.work);
|
|
}
|
|
|
|
static void
|
|
gf100_fifo_init(struct nvkm_fifo *base)
|
|
{
|
|
struct gf100_fifo *fifo = gf100_fifo(base);
|
|
struct nvkm_device *device = fifo->base.engine.subdev.device;
|
|
int i;
|
|
|
|
/* Enable PBDMAs. */
|
|
nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1);
|
|
nvkm_wr32(device, 0x002204, (1 << fifo->pbdma_nr) - 1);
|
|
|
|
/* Assign engines to PBDMAs. */
|
|
if (fifo->pbdma_nr >= 3) {
|
|
nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */
|
|
nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */
|
|
nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */
|
|
nvkm_wr32(device, 0x002214, ~(1 << 1)); /* PMSVLD */
|
|
nvkm_wr32(device, 0x002218, ~(1 << 2)); /* PCE0 */
|
|
nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */
|
|
}
|
|
|
|
/* PBDMA[n] */
|
|
for (i = 0; i < fifo->pbdma_nr; i++) {
|
|
nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
|
|
nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
|
|
nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
|
|
}
|
|
|
|
nvkm_mask(device, 0x002200, 0x00000001, 0x00000001);
|
|
nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar->addr >> 12);
|
|
|
|
nvkm_wr32(device, 0x002100, 0xffffffff);
|
|
nvkm_wr32(device, 0x002140, 0x7fffffff);
|
|
nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */
|
|
}
|
|
|
|
static void *
|
|
gf100_fifo_dtor(struct nvkm_fifo *base)
|
|
{
|
|
struct gf100_fifo *fifo = gf100_fifo(base);
|
|
struct nvkm_device *device = fifo->base.engine.subdev.device;
|
|
nvkm_vmm_put(nvkm_bar_bar1_vmm(device), &fifo->user.bar);
|
|
nvkm_memory_unref(&fifo->user.mem);
|
|
nvkm_memory_unref(&fifo->runlist.mem[0]);
|
|
nvkm_memory_unref(&fifo->runlist.mem[1]);
|
|
return fifo;
|
|
}
|
|
|
|
static const struct nvkm_fifo_func
|
|
gf100_fifo = {
|
|
.dtor = gf100_fifo_dtor,
|
|
.oneinit = gf100_fifo_oneinit,
|
|
.init = gf100_fifo_init,
|
|
.fini = gf100_fifo_fini,
|
|
.intr = gf100_fifo_intr,
|
|
.fault = gf100_fifo_fault,
|
|
.engine_id = gf100_fifo_engine_id,
|
|
.id_engine = gf100_fifo_id_engine,
|
|
.uevent_init = gf100_fifo_uevent_init,
|
|
.uevent_fini = gf100_fifo_uevent_fini,
|
|
.chan = {
|
|
&gf100_fifo_gpfifo_oclass,
|
|
NULL
|
|
},
|
|
};
|
|
|
|
int
|
|
gf100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
|
|
struct nvkm_fifo **pfifo)
|
|
{
|
|
struct gf100_fifo *fifo;
|
|
|
|
if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
|
|
return -ENOMEM;
|
|
INIT_LIST_HEAD(&fifo->chan);
|
|
INIT_WORK(&fifo->recover.work, gf100_fifo_recover_work);
|
|
*pfifo = &fifo->base;
|
|
|
|
return nvkm_fifo_ctor(&gf100_fifo, device, type, inst, 128, &fifo->base);
|
|
}
|