260 lines
6.5 KiB
C
260 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2020-2021 NXP
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*/
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#include <linux/init.h>
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#include <linux/interconnect.h>
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#include <linux/ioctl.h>
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#include <linux/list.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/firmware/imx/ipc.h>
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#include <linux/firmware/imx/svc/misc.h>
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#include "vpu.h"
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#include "vpu_rpc.h"
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#include "vpu_imx8q.h"
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#include "vpu_windsor.h"
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#include "vpu_malone.h"
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int vpu_iface_check_memory_region(struct vpu_core *core, dma_addr_t addr, u32 size)
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{
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struct vpu_iface_ops *ops = vpu_core_get_iface(core);
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if (!ops || !ops->check_memory_region)
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return VPU_CORE_MEMORY_INVALID;
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return ops->check_memory_region(core->fw.phys, addr, size);
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}
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static u32 vpu_rpc_check_buffer_space(struct vpu_rpc_buffer_desc *desc, bool write)
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{
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u32 ptr1;
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u32 ptr2;
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u32 size;
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size = desc->end - desc->start;
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if (write) {
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ptr1 = desc->wptr;
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ptr2 = desc->rptr;
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} else {
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ptr1 = desc->rptr;
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ptr2 = desc->wptr;
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}
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if (ptr1 == ptr2) {
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if (!write)
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return 0;
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else
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return size;
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}
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return (ptr2 + size - ptr1) % size;
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}
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static int vpu_rpc_send_cmd_buf(struct vpu_shared_addr *shared, struct vpu_rpc_event *cmd)
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{
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struct vpu_rpc_buffer_desc *desc;
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u32 space = 0;
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u32 *data;
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u32 wptr;
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u32 i;
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if (cmd->hdr.num > 0xff || cmd->hdr.num >= ARRAY_SIZE(cmd->data))
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return -EINVAL;
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desc = shared->cmd_desc;
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space = vpu_rpc_check_buffer_space(desc, true);
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if (space < (((cmd->hdr.num + 1) << 2) + 16))
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return -EINVAL;
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wptr = desc->wptr;
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data = (u32 *)(shared->cmd_mem_vir + desc->wptr - desc->start);
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*data = 0;
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*data |= ((cmd->hdr.index & 0xff) << 24);
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*data |= ((cmd->hdr.num & 0xff) << 16);
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*data |= (cmd->hdr.id & 0x3fff);
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wptr += 4;
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data++;
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if (wptr >= desc->end) {
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wptr = desc->start;
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data = shared->cmd_mem_vir;
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}
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for (i = 0; i < cmd->hdr.num; i++) {
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*data = cmd->data[i];
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wptr += 4;
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data++;
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if (wptr >= desc->end) {
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wptr = desc->start;
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data = shared->cmd_mem_vir;
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}
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}
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/*update wptr after data is written*/
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mb();
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desc->wptr = wptr;
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return 0;
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}
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static bool vpu_rpc_check_msg(struct vpu_shared_addr *shared)
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{
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struct vpu_rpc_buffer_desc *desc;
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u32 space = 0;
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u32 msgword;
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u32 msgnum;
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desc = shared->msg_desc;
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space = vpu_rpc_check_buffer_space(desc, 0);
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space = (space >> 2);
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if (space) {
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msgword = *(u32 *)(shared->msg_mem_vir + desc->rptr - desc->start);
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msgnum = (msgword & 0xff0000) >> 16;
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if (msgnum <= space)
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return true;
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}
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return false;
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}
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static int vpu_rpc_receive_msg_buf(struct vpu_shared_addr *shared, struct vpu_rpc_event *msg)
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{
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struct vpu_rpc_buffer_desc *desc;
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u32 *data;
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u32 msgword;
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u32 rptr;
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u32 i;
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if (!vpu_rpc_check_msg(shared))
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return -EINVAL;
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desc = shared->msg_desc;
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data = (u32 *)(shared->msg_mem_vir + desc->rptr - desc->start);
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rptr = desc->rptr;
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msgword = *data;
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data++;
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rptr += 4;
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if (rptr >= desc->end) {
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rptr = desc->start;
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data = shared->msg_mem_vir;
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}
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msg->hdr.index = (msgword >> 24) & 0xff;
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msg->hdr.num = (msgword >> 16) & 0xff;
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msg->hdr.id = msgword & 0x3fff;
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if (msg->hdr.num > ARRAY_SIZE(msg->data))
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return -EINVAL;
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for (i = 0; i < msg->hdr.num; i++) {
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msg->data[i] = *data;
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data++;
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rptr += 4;
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if (rptr >= desc->end) {
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rptr = desc->start;
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data = shared->msg_mem_vir;
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}
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}
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/*update rptr after data is read*/
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mb();
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desc->rptr = rptr;
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return 0;
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}
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static struct vpu_iface_ops imx8q_rpc_ops[] = {
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[VPU_CORE_TYPE_ENC] = {
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.check_codec = vpu_imx8q_check_codec,
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.check_fmt = vpu_imx8q_check_fmt,
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.boot_core = vpu_imx8q_boot_core,
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.get_power_state = vpu_imx8q_get_power_state,
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.on_firmware_loaded = vpu_imx8q_on_firmware_loaded,
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.get_data_size = vpu_windsor_get_data_size,
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.check_memory_region = vpu_imx8q_check_memory_region,
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.init_rpc = vpu_windsor_init_rpc,
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.set_log_buf = vpu_windsor_set_log_buf,
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.set_system_cfg = vpu_windsor_set_system_cfg,
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.get_version = vpu_windsor_get_version,
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.send_cmd_buf = vpu_rpc_send_cmd_buf,
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.receive_msg_buf = vpu_rpc_receive_msg_buf,
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.pack_cmd = vpu_windsor_pack_cmd,
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.convert_msg_id = vpu_windsor_convert_msg_id,
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.unpack_msg_data = vpu_windsor_unpack_msg_data,
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.config_memory_resource = vpu_windsor_config_memory_resource,
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.get_stream_buffer_size = vpu_windsor_get_stream_buffer_size,
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.config_stream_buffer = vpu_windsor_config_stream_buffer,
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.get_stream_buffer_desc = vpu_windsor_get_stream_buffer_desc,
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.update_stream_buffer = vpu_windsor_update_stream_buffer,
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.set_encode_params = vpu_windsor_set_encode_params,
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.input_frame = vpu_windsor_input_frame,
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.get_max_instance_count = vpu_windsor_get_max_instance_count,
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},
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[VPU_CORE_TYPE_DEC] = {
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.check_codec = vpu_imx8q_check_codec,
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.check_fmt = vpu_malone_check_fmt,
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.boot_core = vpu_imx8q_boot_core,
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.get_power_state = vpu_imx8q_get_power_state,
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.on_firmware_loaded = vpu_imx8q_on_firmware_loaded,
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.get_data_size = vpu_malone_get_data_size,
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.check_memory_region = vpu_imx8q_check_memory_region,
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.init_rpc = vpu_malone_init_rpc,
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.set_log_buf = vpu_malone_set_log_buf,
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.set_system_cfg = vpu_malone_set_system_cfg,
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.get_version = vpu_malone_get_version,
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.send_cmd_buf = vpu_rpc_send_cmd_buf,
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.receive_msg_buf = vpu_rpc_receive_msg_buf,
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.get_stream_buffer_size = vpu_malone_get_stream_buffer_size,
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.config_stream_buffer = vpu_malone_config_stream_buffer,
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.set_decode_params = vpu_malone_set_decode_params,
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.pack_cmd = vpu_malone_pack_cmd,
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.convert_msg_id = vpu_malone_convert_msg_id,
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.unpack_msg_data = vpu_malone_unpack_msg_data,
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.get_stream_buffer_desc = vpu_malone_get_stream_buffer_desc,
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.update_stream_buffer = vpu_malone_update_stream_buffer,
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.add_scode = vpu_malone_add_scode,
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.input_frame = vpu_malone_input_frame,
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.pre_send_cmd = vpu_malone_pre_cmd,
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.post_send_cmd = vpu_malone_post_cmd,
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.init_instance = vpu_malone_init_instance,
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.get_max_instance_count = vpu_malone_get_max_instance_count,
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},
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};
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static struct vpu_iface_ops *vpu_get_iface(struct vpu_dev *vpu, enum vpu_core_type type)
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{
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struct vpu_iface_ops *rpc_ops = NULL;
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u32 size = 0;
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switch (vpu->res->plat_type) {
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case IMX8QXP:
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case IMX8QM:
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rpc_ops = imx8q_rpc_ops;
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size = ARRAY_SIZE(imx8q_rpc_ops);
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break;
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default:
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return NULL;
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}
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if (type >= size)
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return NULL;
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return &rpc_ops[type];
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}
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struct vpu_iface_ops *vpu_core_get_iface(struct vpu_core *core)
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{
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return vpu_get_iface(core->vpu, core->type);
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}
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struct vpu_iface_ops *vpu_inst_get_iface(struct vpu_inst *inst)
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{
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if (inst->core)
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return vpu_core_get_iface(inst->core);
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return vpu_get_iface(inst->vpu, inst->type);
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}
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