272 lines
5.9 KiB
C
272 lines
5.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2020-2021 NXP
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*/
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/ioctl.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include "vpu.h"
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#include "vpu_core.h"
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#include "vpu_imx8q.h"
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#include "vpu_rpc.h"
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#define IMX8Q_CSR_CM0Px_ADDR_OFFSET 0x00000000
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#define IMX8Q_CSR_CM0Px_CPUWAIT 0x00000004
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#ifdef CONFIG_IMX_SCU
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#include <linux/firmware/imx/ipc.h>
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#include <linux/firmware/imx/svc/misc.h>
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#define VPU_DISABLE_BITS 0x7
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#define VPU_IMX_DECODER_FUSE_OFFSET 14
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#define VPU_ENCODER_MASK 0x1
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#define VPU_DECODER_MASK 0x3UL
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#define VPU_DECODER_H264_MASK 0x2UL
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#define VPU_DECODER_HEVC_MASK 0x1UL
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static u32 imx8q_fuse;
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struct vpu_sc_msg_misc {
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struct imx_sc_rpc_msg hdr;
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u32 word;
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} __packed;
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#endif
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int vpu_imx8q_setup_dec(struct vpu_dev *vpu)
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{
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const off_t offset = DEC_MFD_XREG_SLV_BASE + MFD_BLK_CTRL;
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vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET, 0x1f);
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vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_SET, 0xffffffff);
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return 0;
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}
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int vpu_imx8q_setup_enc(struct vpu_dev *vpu)
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{
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return 0;
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}
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int vpu_imx8q_setup(struct vpu_dev *vpu)
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{
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const off_t offset = SCB_XREG_SLV_BASE + SCB_SCB_BLK_CTRL;
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vpu_readl(vpu, offset + 0x108);
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vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0x1);
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vpu_writel(vpu, offset + 0x190, 0xffffffff);
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vpu_writel(vpu, offset + SCB_BLK_CTRL_XMEM_RESET_SET, 0xffffffff);
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vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0xE);
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vpu_writel(vpu, offset + SCB_BLK_CTRL_CACHE_RESET_SET, 0x7);
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vpu_writel(vpu, XMEM_CONTROL, 0x102);
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vpu_readl(vpu, offset + 0x108);
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return 0;
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}
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static int vpu_imx8q_reset_enc(struct vpu_dev *vpu)
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{
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return 0;
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}
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static int vpu_imx8q_reset_dec(struct vpu_dev *vpu)
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{
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const off_t offset = DEC_MFD_XREG_SLV_BASE + MFD_BLK_CTRL;
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vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_CLR, 0xffffffff);
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return 0;
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}
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int vpu_imx8q_reset(struct vpu_dev *vpu)
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{
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const off_t offset = SCB_XREG_SLV_BASE + SCB_SCB_BLK_CTRL;
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vpu_writel(vpu, offset + SCB_BLK_CTRL_CACHE_RESET_CLR, 0x7);
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vpu_imx8q_reset_enc(vpu);
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vpu_imx8q_reset_dec(vpu);
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return 0;
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}
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int vpu_imx8q_set_system_cfg_common(struct vpu_rpc_system_config *config, u32 regs, u32 core_id)
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{
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if (!config)
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return -EINVAL;
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switch (core_id) {
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case 0:
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config->malone_base_addr[0] = regs + DEC_MFD_XREG_SLV_BASE;
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config->num_malones = 1;
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config->num_windsors = 0;
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break;
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case 1:
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config->windsor_base_addr[0] = regs + ENC_MFD_XREG_SLV_0_BASE;
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config->num_windsors = 1;
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config->num_malones = 0;
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break;
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case 2:
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config->windsor_base_addr[0] = regs + ENC_MFD_XREG_SLV_1_BASE;
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config->num_windsors = 1;
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config->num_malones = 0;
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break;
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default:
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return -EINVAL;
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}
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if (config->num_windsors) {
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config->windsor_irq_pin[0x0][0x0] = WINDSOR_PAL_IRQ_PIN_L;
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config->windsor_irq_pin[0x0][0x1] = WINDSOR_PAL_IRQ_PIN_H;
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}
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config->malone_base_addr[0x1] = 0x0;
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config->hif_offset[0x0] = MFD_HIF;
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config->hif_offset[0x1] = 0x0;
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config->dpv_base_addr = 0x0;
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config->dpv_irq_pin = 0x0;
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config->pixif_base_addr = regs + DEC_MFD_XREG_SLV_BASE + MFD_PIX_IF;
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config->cache_base_addr[0] = regs + MC_CACHE_0_BASE;
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config->cache_base_addr[1] = regs + MC_CACHE_1_BASE;
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return 0;
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}
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int vpu_imx8q_boot_core(struct vpu_core *core)
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{
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csr_writel(core, IMX8Q_CSR_CM0Px_ADDR_OFFSET, core->fw.phys);
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csr_writel(core, IMX8Q_CSR_CM0Px_CPUWAIT, 0);
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return 0;
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}
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int vpu_imx8q_get_power_state(struct vpu_core *core)
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{
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if (csr_readl(core, IMX8Q_CSR_CM0Px_CPUWAIT) == 1)
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return 0;
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return 1;
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}
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int vpu_imx8q_on_firmware_loaded(struct vpu_core *core)
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{
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u8 *p;
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p = core->fw.virt;
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p[16] = core->vpu->res->plat_type;
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p[17] = core->id;
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p[18] = 1;
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return 0;
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}
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int vpu_imx8q_check_memory_region(dma_addr_t base, dma_addr_t addr, u32 size)
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{
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const struct vpu_rpc_region_t imx8q_regions[] = {
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{0x00000000, 0x08000000, VPU_CORE_MEMORY_CACHED},
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{0x08000000, 0x10000000, VPU_CORE_MEMORY_UNCACHED},
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{0x10000000, 0x20000000, VPU_CORE_MEMORY_CACHED},
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{0x20000000, 0x40000000, VPU_CORE_MEMORY_UNCACHED}
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};
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int i;
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if (addr < base)
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return VPU_CORE_MEMORY_INVALID;
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addr -= base;
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for (i = 0; i < ARRAY_SIZE(imx8q_regions); i++) {
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const struct vpu_rpc_region_t *region = &imx8q_regions[i];
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if (addr >= region->start && addr + size < region->end)
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return region->type;
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}
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return VPU_CORE_MEMORY_INVALID;
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}
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#ifdef CONFIG_IMX_SCU
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static u32 vpu_imx8q_get_fuse(void)
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{
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static u32 fuse_got;
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struct imx_sc_ipc *ipc;
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struct vpu_sc_msg_misc msg;
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struct imx_sc_rpc_msg *hdr = &msg.hdr;
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int ret;
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if (fuse_got)
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return imx8q_fuse;
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ret = imx_scu_get_handle(&ipc);
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if (ret) {
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pr_err("error: get sct handle fail: %d\n", ret);
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return 0;
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}
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hdr->ver = IMX_SC_RPC_VERSION;
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hdr->svc = IMX_SC_RPC_SVC_MISC;
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hdr->func = IMX_SC_MISC_FUNC_OTP_FUSE_READ;
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hdr->size = 2;
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msg.word = VPU_DISABLE_BITS;
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ret = imx_scu_call_rpc(ipc, &msg, true);
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if (ret)
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return 0;
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imx8q_fuse = msg.word;
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fuse_got = 1;
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return imx8q_fuse;
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}
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bool vpu_imx8q_check_codec(enum vpu_core_type type)
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{
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u32 fuse = vpu_imx8q_get_fuse();
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if (type == VPU_CORE_TYPE_ENC) {
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if (fuse & VPU_ENCODER_MASK)
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return false;
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} else if (type == VPU_CORE_TYPE_DEC) {
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fuse >>= VPU_IMX_DECODER_FUSE_OFFSET;
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fuse &= VPU_DECODER_MASK;
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if (fuse == VPU_DECODER_MASK)
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return false;
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}
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return true;
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}
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bool vpu_imx8q_check_fmt(enum vpu_core_type type, u32 pixelfmt)
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{
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u32 fuse = vpu_imx8q_get_fuse();
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if (type == VPU_CORE_TYPE_DEC) {
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fuse >>= VPU_IMX_DECODER_FUSE_OFFSET;
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fuse &= VPU_DECODER_MASK;
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if (fuse == VPU_DECODER_HEVC_MASK && pixelfmt == V4L2_PIX_FMT_HEVC)
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return false;
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if (fuse == VPU_DECODER_H264_MASK && pixelfmt == V4L2_PIX_FMT_H264)
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return false;
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if (fuse == VPU_DECODER_MASK)
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return false;
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}
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return true;
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}
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#else
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bool vpu_imx8q_check_codec(enum vpu_core_type type)
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{
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return true;
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}
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bool vpu_imx8q_check_fmt(enum vpu_core_type type, u32 pixelfmt)
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{
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return true;
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}
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#endif
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