318 lines
10 KiB
C
318 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/********************************************************************************
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*
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* Copyright (C) 2016 NEXTCHIP Inc. All rights reserved.
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* Module : Jaguar1 Device Driver
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* Description : MIPI
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* Author :
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* Date :
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* Version : Version 1.0
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*
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********************************************************************************
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* History :
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*
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*
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********************************************************************************/
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#include <linux/string.h>
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#include <linux/delay.h>
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#include "jaguar1_common.h"
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#include "jaguar1_mipi.h"
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#include "jaguar1_mipi_table.h"
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static unsigned char mipi_dtype, arb_dtype, en_param;
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/*-------------------------------------------------------------------
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Arbiter function
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-------------------------------------------------------------------*/
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static void arb_scale_set(video_input_init *dev_ch_info, unsigned char val)
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{
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int devnum = dev_ch_info->ch / 4;
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unsigned char arb_scale = 0;
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gpio_i2c_write(jaguar1_i2c_addr[devnum], 0xFF, 0x20);
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arb_scale = gpio_i2c_read(jaguar1_i2c_addr[devnum], 0x01);
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arb_scale &= ~(0x3<<(dev_ch_info->ch*2));
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arb_scale |= val<<(dev_ch_info->ch*2);
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gpio_i2c_write(jaguar1_i2c_addr[devnum], 0x01, arb_scale);
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}
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void arb_enable(int dev_num)
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{
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if((dev_num < 0) || (dev_num > 3))
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{
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printk("[DRV] %s input channel Error (%d)\n",__func__, dev_num);
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return;
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}
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xff, 0x20);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x00, en_param);
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printk("VDEC_ARBITER_INIT done 0x%X\n", en_param);
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}
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void arb_disable(int dev_num)
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{
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xff, 0x20);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x00, 0x00);
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}
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void arb_init(int dev_num)
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{
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arb_disable(dev_num);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xff, 0x20);
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// ARB RESET High
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x40, 0x01);
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// MIPI Video type Init
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x0F, arb_dtype);
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// ARB 32Bit Mode
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if(2 == jaguar1_lane)
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x0D, 0x00);
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else
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x0D, 0x01);
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// ARB RESET Low
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x40, 0x00);
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arb_enable(dev_num);
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}
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/*-------------------------------------------------------------------
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MIPI function
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-------------------------------------------------------------------*/
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static void mipi_frame_opt_set(video_input_init *dev_ch_info, unsigned char val)
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{
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int devnum = dev_ch_info->ch / 4;
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unsigned char mipi_frame_opt;
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gpio_i2c_write(jaguar1_i2c_addr[devnum], 0xFF, 0x21);
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switch(dev_ch_info->ch)
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{
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case 0 :
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mipi_frame_opt = gpio_i2c_read(jaguar1_i2c_addr[devnum], 0x3E);
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mipi_frame_opt = (mipi_frame_opt & 0xF0) | val;
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gpio_i2c_write(jaguar1_i2c_addr[devnum], 0x3E, mipi_frame_opt);
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break;
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case 1 :
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mipi_frame_opt = gpio_i2c_read(jaguar1_i2c_addr[devnum], 0x3E);
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mipi_frame_opt = (mipi_frame_opt & 0x0F) | val;
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gpio_i2c_write(jaguar1_i2c_addr[devnum], 0x3E, mipi_frame_opt);
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break;
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case 2 :
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mipi_frame_opt = gpio_i2c_read(jaguar1_i2c_addr[devnum], 0x3F);
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mipi_frame_opt = (mipi_frame_opt & 0xF0) | val;
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gpio_i2c_write(jaguar1_i2c_addr[devnum], 0x3F, mipi_frame_opt);
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break;
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case 3 :
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mipi_frame_opt = gpio_i2c_read(jaguar1_i2c_addr[devnum], 0x3F);
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mipi_frame_opt = (mipi_frame_opt & 0x0F) | val;
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gpio_i2c_write(jaguar1_i2c_addr[devnum], 0x3F, mipi_frame_opt);
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break;
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}
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}
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void mipi_video_format_set(video_input_init *dev_ch_info)
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{
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mipi_vdfmt_set_s mipi_vd_fmt = (mipi_vdfmt_set_s)decoder_mipi_fmtdef[dev_ch_info->format];
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if(dev_ch_info->interface != DISABLE)
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{
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en_param |= 0x11<<(dev_ch_info->ch);
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}
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mipi_frame_opt_set(dev_ch_info, mipi_vd_fmt.mipi_frame_opt);
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arb_scale_set(dev_ch_info, mipi_vd_fmt.arb_scale);
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}
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int mipi_datatype_set(unsigned char data_type)
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{
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int ret = 0;
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switch(data_type)
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{
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case VD_DATA_TYPE_YUV422 :
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mipi_dtype = 0x1E;
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arb_dtype = 0x00;
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break;
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case VD_DATA_TYPE_YUV420 :
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mipi_dtype = 0x18;
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arb_dtype = 0xAA;
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break;
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case VD_DATA_TYPE_LEGACY420 :
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mipi_dtype = 0x1A;
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arb_dtype = 0x55;
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break;
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default :
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printk("[DRV]%s : invalid data type [0x%X]\n", __func__, data_type);
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ret = -1;
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break;
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}
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return ret;
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}
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void mipi_tx_init(int dev_num)
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{
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xFF, 0x21);
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pr_info("%s: mclk: %d\n", __func__, jaguar1_mclk);
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switch(jaguar1_mclk)
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{
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case 3:
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printk("[DRV] SET_MIPI_1242MHZ\n");
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x40, 0xB4);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x41, 0x00);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x42, 0x03);
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break;
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// case 3:
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// printk("[DRV]_MIPI_252MHZ_TEST_\n");
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// gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x40, 0xDC);
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// gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x41, 0x20);
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// gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x42, 0x05);
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// break;
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case 2:
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printk("[DRV] SET_MIPI_378MHZ\n");
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x40, 0xDC);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x41, 0x20);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x42, 0x03);
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break;
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case 1:
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printk("[DRV] SET_MIPI_594MHZ\n");
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x40, 0xCC);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x41, 0x10);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x42, 0x03);
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break;
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default:
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printk("[DRV] SET_MIPI_756MHZ\n");
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x40, 0xDC);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x41, 0x10);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x42, 0x03);
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break;
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}
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x43, 0x43);
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switch(jaguar1_mclk)
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{
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case 3: // 1242MHz MIPI_CLK for FHD*4ch
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x11, 0x08);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x10, 0x13);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x12, 0x0B);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x13, 0x12);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x17, 0x02);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x18, 0x12);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x15, 0x07);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x14, 0x2D);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x16, 0x0B);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x19, 0x09);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1A, 0x15);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1B, 0x11);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1C, 0x0E);
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break;
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case 2: // 378MHz MIPI_CLK for low-clock test
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x11, 0x03);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x10, 0x07);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x12, 0x04);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x13, 0x06);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x17, 0x01);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x18, 0x0B);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x15, 0x02);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x14, 0x0E);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x16, 0x04);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x19, 0x03);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1A, 0x07);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1B, 0x06);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1C, 0x05);
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break;
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case 1: // 594MHz MIPI_CLK for HD*4ch
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x11, 0x04);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x10, 0x0A);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x12, 0x06);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x13, 0x09);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x17, 0x01);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x18, 0x0D);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x15, 0x04);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x14, 0x16);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x16, 0x05);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x19, 0x05);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1A, 0x0A);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1B, 0x08);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1C, 0x07);
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break;
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default: // 756MHz MIPI_CLK
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x11, 0x05);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x10, 0x0C);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x12, 0x07);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x13, 0x0B);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x17, 0x01);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x18, 0x0E);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x15, 0x04);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x14, 0x1C);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x16, 0x07);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x19, 0x06);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1A, 0x0D);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1B, 0x0B);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x1C, 0x09);
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break;
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}
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// MIPI setting
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x44, 0x00);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x49, 0xF3);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x49, 0xF0);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x44, 0x02);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x08, 0x40);
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// MIPI_TX_FRAME_CNT_EN
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x0F, 0x01);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x38, mipi_dtype);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x39, mipi_dtype);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x3A, mipi_dtype);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x3B, mipi_dtype);
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// MIPI Enable
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if(2 == jaguar1_lane)
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{
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x07, 0x07); //two lanes test
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x2D, 0x00);
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printk("NOTE >>> 2 lanes mode enabled\n");
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}
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else
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{
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x07, 0x0F);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0x2D, 0x01);
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}
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printk("[DRV]VDEC_MIPI_TX_INIT done\n");
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}
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void disable_parallel(int dev_num)
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{
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xFF, 0x01);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xC8, 0x00);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xC9, 0x00);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xCA, 0x00);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xCB, 0x00);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xCC, 0x00);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xCD, 0x00);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xCE, 0x00);
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gpio_i2c_write(jaguar1_i2c_addr[dev_num], 0xCF, 0x00);
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printk("[DRV]Parallel block Disable\n");
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}
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