507 lines
11 KiB
C
507 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Driver for Zarlink zl10036 DVB-S silicon tuner
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*
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* Copyright (C) 2006 Tino Reichardt
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* Copyright (C) 2007-2009 Matthias Schwarzott <zzam@gentoo.de>
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*
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**
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* The data sheet for this tuner can be found at:
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* http://www.mcmilk.de/projects/dvb-card/datasheets/ZL10036.pdf
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*
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* This one is working: (at my Avermedia DVB-S Pro)
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* - zl10036 (40pin, FTA)
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*
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* A driver for zl10038 should be very similar.
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*/
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#include <linux/module.h>
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#include <linux/dvb/frontend.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include "zl10036.h"
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static int zl10036_debug;
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#define dprintk(level, args...) \
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do { if (zl10036_debug & level) printk(KERN_DEBUG "zl10036: " args); \
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} while (0)
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#define deb_info(args...) dprintk(0x01, args)
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#define deb_i2c(args...) dprintk(0x02, args)
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struct zl10036_state {
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struct i2c_adapter *i2c;
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const struct zl10036_config *config;
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u32 frequency;
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u8 br, bf;
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};
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/* This driver assumes the tuner is driven by a 10.111MHz Cristal */
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#define _XTAL 10111
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/* Some of the possible dividers:
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* 64, (write 0x05 to reg), freq step size 158kHz
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* 10, (write 0x0a to reg), freq step size 1.011kHz (used here)
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* 5, (write 0x09 to reg), freq step size 2.022kHz
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*/
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#define _RDIV 10
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#define _RDIV_REG 0x0a
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#define _FR (_XTAL/_RDIV)
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#define STATUS_POR 0x80 /* Power on Reset */
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#define STATUS_FL 0x40 /* Frequency & Phase Lock */
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/* read/write for zl10036 and zl10038 */
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static int zl10036_read_status_reg(struct zl10036_state *state)
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{
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u8 status;
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struct i2c_msg msg[1] = {
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{ .addr = state->config->tuner_address, .flags = I2C_M_RD,
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.buf = &status, .len = sizeof(status) },
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};
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if (i2c_transfer(state->i2c, msg, 1) != 1) {
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printk(KERN_ERR "%s: i2c read failed at addr=%02x\n",
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__func__, state->config->tuner_address);
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return -EIO;
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}
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deb_i2c("R(status): %02x [FL=%d]\n", status,
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(status & STATUS_FL) ? 1 : 0);
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if (status & STATUS_POR)
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deb_info("%s: Power-On-Reset bit enabled - need to initialize the tuner\n",
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__func__);
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return status;
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}
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static int zl10036_write(struct zl10036_state *state, u8 buf[], u8 count)
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{
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struct i2c_msg msg[1] = {
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{ .addr = state->config->tuner_address, .flags = 0,
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.buf = buf, .len = count },
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};
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u8 reg = 0;
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int ret;
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if (zl10036_debug & 0x02) {
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/* every 8bit-value satisifes this!
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* so only check for debug log */
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if ((buf[0] & 0x80) == 0x00)
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reg = 2;
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else if ((buf[0] & 0xc0) == 0x80)
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reg = 4;
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else if ((buf[0] & 0xf0) == 0xc0)
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reg = 6;
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else if ((buf[0] & 0xf0) == 0xd0)
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reg = 8;
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else if ((buf[0] & 0xf0) == 0xe0)
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reg = 10;
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else if ((buf[0] & 0xf0) == 0xf0)
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reg = 12;
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deb_i2c("W(%d):", reg);
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{
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int i;
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for (i = 0; i < count; i++)
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printk(KERN_CONT " %02x", buf[i]);
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printk(KERN_CONT "\n");
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}
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}
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ret = i2c_transfer(state->i2c, msg, 1);
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if (ret != 1) {
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printk(KERN_ERR "%s: i2c error, ret=%d\n", __func__, ret);
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return -EIO;
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}
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return 0;
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}
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static void zl10036_release(struct dvb_frontend *fe)
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{
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struct zl10036_state *state = fe->tuner_priv;
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fe->tuner_priv = NULL;
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kfree(state);
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}
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static int zl10036_sleep(struct dvb_frontend *fe)
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{
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struct zl10036_state *state = fe->tuner_priv;
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u8 buf[] = { 0xf0, 0x80 }; /* regs 12/13 */
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int ret;
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deb_info("%s\n", __func__);
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
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ret = zl10036_write(state, buf, sizeof(buf));
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
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return ret;
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}
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/*
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* register map of the ZL10036/ZL10038
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*
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* reg[default] content
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* 2[0x00]: 0 | N14 | N13 | N12 | N11 | N10 | N9 | N8
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* 3[0x00]: N7 | N6 | N5 | N4 | N3 | N2 | N1 | N0
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* 4[0x80]: 1 | 0 | RFG | BA1 | BA0 | BG1 | BG0 | LEN
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* 5[0x00]: P0 | C1 | C0 | R4 | R3 | R2 | R1 | R0
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* 6[0xc0]: 1 | 1 | 0 | 0 | RSD | 0 | 0 | 0
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* 7[0x20]: P1 | BF6 | BF5 | BF4 | BF3 | BF2 | BF1 | 0
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* 8[0xdb]: 1 | 1 | 0 | 1 | 0 | CC | 1 | 1
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* 9[0x30]: VSD | V2 | V1 | V0 | S3 | S2 | S1 | S0
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* 10[0xe1]: 1 | 1 | 1 | 0 | 0 | LS2 | LS1 | LS0
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* 11[0xf5]: WS | WH2 | WH1 | WH0 | WL2 | WL1 | WL0 | WRE
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* 12[0xf0]: 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0
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* 13[0x28]: PD | BR4 | BR3 | BR2 | BR1 | BR0 | CLR | TL
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*/
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static int zl10036_set_frequency(struct zl10036_state *state, u32 frequency)
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{
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u8 buf[2];
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u32 div, foffset;
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div = (frequency + _FR/2) / _FR;
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state->frequency = div * _FR;
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foffset = frequency - state->frequency;
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buf[0] = (div >> 8) & 0x7f;
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buf[1] = (div >> 0) & 0xff;
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deb_info("%s: ftodo=%u fpriv=%u ferr=%d div=%u\n", __func__,
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frequency, state->frequency, foffset, div);
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return zl10036_write(state, buf, sizeof(buf));
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}
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static int zl10036_set_bandwidth(struct zl10036_state *state, u32 fbw)
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{
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/* fbw is measured in kHz */
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u8 br, bf;
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int ret;
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u8 buf_bf[] = {
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0xc0, 0x00, /* 6/7: rsd=0 bf=0 */
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};
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u8 buf_br[] = {
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0xf0, 0x00, /* 12/13: br=0xa clr=0 tl=0*/
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};
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u8 zl10036_rsd_off[] = { 0xc8 }; /* set RSD=1 */
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/* ensure correct values */
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if (fbw > 35000)
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fbw = 35000;
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if (fbw < 8000)
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fbw = 8000;
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#define _BR_MAXIMUM (_XTAL/575) /* _XTAL / 575kHz = 17 */
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/* <= 28,82 MHz */
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if (fbw <= 28820) {
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br = _BR_MAXIMUM;
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} else {
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/*
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* f(bw)=34,6MHz f(xtal)=10.111MHz
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* br = (10111/34600) * 63 * 1/K = 14;
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*/
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br = ((_XTAL * 21 * 1000) / (fbw * 419));
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}
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/* ensure correct values */
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if (br < 4)
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br = 4;
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if (br > _BR_MAXIMUM)
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br = _BR_MAXIMUM;
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/*
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* k = 1.257
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* bf = fbw/_XTAL * br * k - 1 */
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bf = (fbw * br * 1257) / (_XTAL * 1000) - 1;
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/* ensure correct values */
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if (bf > 62)
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bf = 62;
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buf_bf[1] = (bf << 1) & 0x7e;
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buf_br[1] = (br << 2) & 0x7c;
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deb_info("%s: BW=%d br=%u bf=%u\n", __func__, fbw, br, bf);
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if (br != state->br) {
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ret = zl10036_write(state, buf_br, sizeof(buf_br));
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if (ret < 0)
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return ret;
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}
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if (bf != state->bf) {
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ret = zl10036_write(state, buf_bf, sizeof(buf_bf));
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if (ret < 0)
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return ret;
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/* time = br/(32* fxtal) */
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/* minimal sleep time to be calculated
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* maximum br is 63 -> max time = 2 /10 MHz = 2e-7 */
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msleep(1);
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ret = zl10036_write(state, zl10036_rsd_off,
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sizeof(zl10036_rsd_off));
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if (ret < 0)
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return ret;
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}
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state->br = br;
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state->bf = bf;
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return 0;
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}
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static int zl10036_set_gain_params(struct zl10036_state *state,
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int c)
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{
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u8 buf[2];
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u8 rfg, ba, bg;
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/* default values */
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rfg = 0; /* enable when using an lna */
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ba = 1;
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bg = 1;
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/* reg 4 */
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buf[0] = 0x80 | ((rfg << 5) & 0x20)
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| ((ba << 3) & 0x18) | ((bg << 1) & 0x06);
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if (!state->config->rf_loop_enable)
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buf[0] |= 0x01;
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/* P0=0 */
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buf[1] = _RDIV_REG | ((c << 5) & 0x60);
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deb_info("%s: c=%u rfg=%u ba=%u bg=%u\n", __func__, c, rfg, ba, bg);
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return zl10036_write(state, buf, sizeof(buf));
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}
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static int zl10036_set_params(struct dvb_frontend *fe)
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{
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struct dtv_frontend_properties *p = &fe->dtv_property_cache;
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struct zl10036_state *state = fe->tuner_priv;
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int ret = 0;
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u32 frequency = p->frequency;
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u32 fbw;
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int i;
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u8 c;
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/* ensure correct values
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* maybe redundant as core already checks this */
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if ((frequency < fe->ops.info.frequency_min_hz / kHz)
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|| (frequency > fe->ops.info.frequency_max_hz / kHz))
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return -EINVAL;
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/*
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* alpha = 1.35 for dvb-s
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* fBW = (alpha*symbolrate)/(2*0.8)
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* 1.35 / (2*0.8) = 27 / 32
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*/
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fbw = (27 * p->symbol_rate) / 32;
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/* scale to kHz */
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fbw /= 1000;
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/* Add safe margin of 3MHz */
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fbw += 3000;
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/* setting the charge pump - guessed values */
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if (frequency < 950000)
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return -EINVAL;
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else if (frequency < 1250000)
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c = 0;
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else if (frequency < 1750000)
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c = 1;
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else if (frequency < 2175000)
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c = 2;
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else
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return -EINVAL;
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
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ret = zl10036_set_gain_params(state, c);
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if (ret < 0)
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goto error;
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ret = zl10036_set_frequency(state, p->frequency);
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if (ret < 0)
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goto error;
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ret = zl10036_set_bandwidth(state, fbw);
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if (ret < 0)
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goto error;
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/* wait for tuner lock - no idea if this is really needed */
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for (i = 0; i < 20; i++) {
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ret = zl10036_read_status_reg(state);
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if (ret < 0)
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goto error;
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/* check Frequency & Phase Lock Bit */
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if (ret & STATUS_FL)
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break;
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msleep(10);
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}
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error:
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
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return ret;
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}
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static int zl10036_get_frequency(struct dvb_frontend *fe, u32 *frequency)
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{
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struct zl10036_state *state = fe->tuner_priv;
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*frequency = state->frequency;
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return 0;
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}
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static int zl10036_init_regs(struct zl10036_state *state)
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{
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int ret;
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int i;
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/* could also be one block from reg 2 to 13 and additional 10/11 */
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u8 zl10036_init_tab[][2] = {
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{ 0x04, 0x00 }, /* 2/3: div=0x400 - arbitrary value */
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{ 0x8b, _RDIV_REG }, /* 4/5: rfg=0 ba=1 bg=1 len=? */
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/* p0=0 c=0 r=_RDIV_REG */
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{ 0xc0, 0x20 }, /* 6/7: rsd=0 bf=0x10 */
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{ 0xd3, 0x40 }, /* 8/9: from datasheet */
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{ 0xe3, 0x5b }, /* 10/11: lock window level */
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{ 0xf0, 0x28 }, /* 12/13: br=0xa clr=0 tl=0*/
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{ 0xe3, 0xf9 }, /* 10/11: unlock window level */
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};
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/* invalid values to trigger writing */
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state->br = 0xff;
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state->bf = 0xff;
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if (!state->config->rf_loop_enable)
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zl10036_init_tab[1][0] |= 0x01;
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deb_info("%s\n", __func__);
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for (i = 0; i < ARRAY_SIZE(zl10036_init_tab); i++) {
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ret = zl10036_write(state, zl10036_init_tab[i], 2);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int zl10036_init(struct dvb_frontend *fe)
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{
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struct zl10036_state *state = fe->tuner_priv;
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int ret = 0;
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
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ret = zl10036_read_status_reg(state);
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if (ret < 0)
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return ret;
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/* Only init if Power-on-Reset bit is set? */
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ret = zl10036_init_regs(state);
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
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return ret;
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}
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static const struct dvb_tuner_ops zl10036_tuner_ops = {
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.info = {
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.name = "Zarlink ZL10036",
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.frequency_min_hz = 950 * MHz,
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.frequency_max_hz = 2175 * MHz
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},
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.init = zl10036_init,
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.release = zl10036_release,
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.sleep = zl10036_sleep,
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.set_params = zl10036_set_params,
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.get_frequency = zl10036_get_frequency,
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};
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struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe,
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const struct zl10036_config *config,
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struct i2c_adapter *i2c)
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{
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struct zl10036_state *state;
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int ret;
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if (!config) {
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printk(KERN_ERR "%s: no config specified", __func__);
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return NULL;
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}
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state = kzalloc(sizeof(struct zl10036_state), GFP_KERNEL);
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if (!state)
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return NULL;
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state->config = config;
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state->i2c = i2c;
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
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ret = zl10036_read_status_reg(state);
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if (ret < 0) {
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printk(KERN_ERR "%s: No zl10036 found\n", __func__);
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goto error;
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}
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ret = zl10036_init_regs(state);
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if (ret < 0) {
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printk(KERN_ERR "%s: tuner initialization failed\n",
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__func__);
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goto error;
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}
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
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fe->tuner_priv = state;
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memcpy(&fe->ops.tuner_ops, &zl10036_tuner_ops,
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sizeof(struct dvb_tuner_ops));
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printk(KERN_INFO "%s: tuner initialization (%s addr=0x%02x) ok\n",
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__func__, fe->ops.tuner_ops.info.name, config->tuner_address);
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return fe;
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error:
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kfree(state);
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return NULL;
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}
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EXPORT_SYMBOL_GPL(zl10036_attach);
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module_param_named(debug, zl10036_debug, int, 0644);
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MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
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MODULE_DESCRIPTION("DVB ZL10036 driver");
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MODULE_AUTHOR("Tino Reichardt");
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MODULE_AUTHOR("Matthias Schwarzott");
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MODULE_LICENSE("GPL");
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