391 lines
10 KiB
C
391 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Samsung s5h1432 DVB-T demodulator driver
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*
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* Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <media/dvb_frontend.h>
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#include "s5h1432.h"
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struct s5h1432_state {
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struct i2c_adapter *i2c;
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/* configuration settings */
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const struct s5h1432_config *config;
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struct dvb_frontend frontend;
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enum fe_modulation current_modulation;
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unsigned int first_tune:1;
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u32 current_frequency;
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int if_freq;
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u8 inversion;
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};
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static int debug;
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#define dprintk(arg...) do { \
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if (debug) \
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printk(arg); \
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} while (0)
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static int s5h1432_writereg(struct s5h1432_state *state,
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u8 addr, u8 reg, u8 data)
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{
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int ret;
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u8 buf[] = { reg, data };
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struct i2c_msg msg = {.addr = addr, .flags = 0, .buf = buf, .len = 2 };
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ret = i2c_transfer(state->i2c, &msg, 1);
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if (ret != 1)
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printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, ret == %i)\n",
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__func__, addr, reg, data, ret);
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return (ret != 1) ? -1 : 0;
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}
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static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg)
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{
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int ret;
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u8 b0[] = { reg };
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u8 b1[] = { 0 };
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struct i2c_msg msg[] = {
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{.addr = addr, .flags = 0, .buf = b0, .len = 1},
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{.addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1}
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};
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2)
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printk(KERN_ERR "%s: readreg error (ret == %i)\n",
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__func__, ret);
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return b1[0];
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}
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static int s5h1432_sleep(struct dvb_frontend *fe)
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{
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return 0;
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}
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static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe,
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u32 bandwidth)
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{
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struct s5h1432_state *state = fe->demodulator_priv;
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u8 reg = 0;
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/* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */
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reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);
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reg &= ~(0x0C);
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switch (bandwidth) {
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case 6:
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reg |= 0x08;
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break;
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case 7:
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reg |= 0x04;
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break;
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case 8:
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reg |= 0x00;
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break;
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default:
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return 0;
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}
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg);
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return 1;
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}
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static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz)
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{
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struct s5h1432_state *state = fe->demodulator_priv;
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switch (ifFreqHz) {
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case TAIWAN_HI_IF_FREQ_44_MHZ:
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x15);
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break;
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case EUROPE_HI_IF_FREQ_36_MHZ:
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x40);
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break;
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case IF_FREQ_6_MHZ:
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xe0);
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break;
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case IF_FREQ_3point3_MHZ:
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
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break;
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case IF_FREQ_3point5_MHZ:
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xED);
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break;
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case IF_FREQ_4_MHZ:
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0xAA);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0xAA);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEA);
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break;
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default:
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{
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u32 value = 0;
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value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *
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(u32) 32768) / (48 * 1000));
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printk(KERN_INFO
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"Default IFFreq %d :reg value = 0x%x\n",
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ifFreqHz, value);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4,
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(u8) value & 0xFF);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5,
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(u8) (value >> 8) & 0xFF);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7,
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(u8) (value >> 16) & 0xFF);
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break;
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}
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}
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return 1;
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}
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/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
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static int s5h1432_set_frontend(struct dvb_frontend *fe)
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{
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struct dtv_frontend_properties *p = &fe->dtv_property_cache;
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u32 dvb_bandwidth = 8;
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struct s5h1432_state *state = fe->demodulator_priv;
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if (p->frequency == state->current_frequency) {
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/*current_frequency = p->frequency; */
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/*state->current_frequency = p->frequency; */
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} else {
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fe->ops.tuner_ops.set_params(fe);
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msleep(300);
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s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
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switch (p->bandwidth_hz) {
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case 6000000:
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dvb_bandwidth = 6;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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case 7000000:
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dvb_bandwidth = 7;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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case 8000000:
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dvb_bandwidth = 8;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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default:
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return 0;
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}
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/*fe->ops.tuner_ops.set_params(fe); */
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/*Soft Reset chip*/
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
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s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
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switch (p->bandwidth_hz) {
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case 6000000:
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dvb_bandwidth = 6;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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case 7000000:
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dvb_bandwidth = 7;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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case 8000000:
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dvb_bandwidth = 8;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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default:
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return 0;
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}
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/*fe->ops.tuner_ops.set_params(fe); */
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/*Soft Reset chip*/
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
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}
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state->current_frequency = p->frequency;
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return 0;
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}
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static int s5h1432_init(struct dvb_frontend *fe)
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{
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struct s5h1432_state *state = fe->demodulator_priv;
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u8 reg = 0;
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state->current_frequency = 0;
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printk(KERN_INFO " s5h1432_init().\n");
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/*Set VSB mode as default, this also does a soft reset */
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/*Initialize registers */
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);
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/* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1); */
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);
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/*For NXP tuner*/
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/*Set 3.3MHz as default IF frequency */
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
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/* Set reg 0x1E to get the full dynamic range */
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);
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/* Mode setting in demod */
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reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);
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reg |= 0x80;
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);
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/* Serial mode */
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/* Soft Reset chip */
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
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return 0;
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}
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static int s5h1432_read_status(struct dvb_frontend *fe, enum fe_status *status)
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{
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return 0;
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}
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static int s5h1432_read_signal_strength(struct dvb_frontend *fe,
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u16 *signal_strength)
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{
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return 0;
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}
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static int s5h1432_read_snr(struct dvb_frontend *fe, u16 *snr)
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{
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return 0;
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}
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static int s5h1432_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
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{
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return 0;
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}
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static int s5h1432_read_ber(struct dvb_frontend *fe, u32 *ber)
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{
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return 0;
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}
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static int s5h1432_get_tune_settings(struct dvb_frontend *fe,
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struct dvb_frontend_tune_settings *tune)
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{
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return 0;
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}
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static void s5h1432_release(struct dvb_frontend *fe)
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{
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struct s5h1432_state *state = fe->demodulator_priv;
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kfree(state);
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}
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static const struct dvb_frontend_ops s5h1432_ops;
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struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config,
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struct i2c_adapter *i2c)
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{
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struct s5h1432_state *state = NULL;
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printk(KERN_INFO " Enter s5h1432_attach(). attach success!\n");
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/* allocate memory for the internal state */
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state = kmalloc(sizeof(struct s5h1432_state), GFP_KERNEL);
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if (!state)
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return NULL;
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/* setup the state */
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state->config = config;
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state->i2c = i2c;
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state->current_modulation = QAM_16;
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state->inversion = state->config->inversion;
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/* create dvb_frontend */
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memcpy(&state->frontend.ops, &s5h1432_ops,
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sizeof(struct dvb_frontend_ops));
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state->frontend.demodulator_priv = state;
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return &state->frontend;
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}
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EXPORT_SYMBOL_GPL(s5h1432_attach);
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static const struct dvb_frontend_ops s5h1432_ops = {
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.delsys = { SYS_DVBT },
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.info = {
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.name = "Samsung s5h1432 DVB-T Frontend",
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.frequency_min_hz = 177 * MHz,
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.frequency_max_hz = 858 * MHz,
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.frequency_stepsize_hz = 166666,
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.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
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FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
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FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
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FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
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FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER},
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.init = s5h1432_init,
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.sleep = s5h1432_sleep,
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.set_frontend = s5h1432_set_frontend,
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.get_tune_settings = s5h1432_get_tune_settings,
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.read_status = s5h1432_read_status,
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.read_ber = s5h1432_read_ber,
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.read_signal_strength = s5h1432_read_signal_strength,
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.read_snr = s5h1432_read_snr,
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.read_ucblocks = s5h1432_read_ucblocks,
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.release = s5h1432_release,
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};
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module_param(debug, int, 0644);
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MODULE_PARM_DESC(debug, "Enable verbose debug messages");
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MODULE_DESCRIPTION("Samsung s5h1432 DVB-T Demodulator driver");
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MODULE_AUTHOR("Bill Liu");
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MODULE_LICENSE("GPL");
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