691 lines
18 KiB
C
691 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) Rockchip Electronics Co., Ltd.
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* Author:Mark Yao <mark.yao@rock-chips.com>
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*
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* based on exynos_drm_drv.h
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*/
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#ifndef _ROCKCHIP_DRM_DRV_H
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#define _ROCKCHIP_DRM_DRV_H
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#include <drm/drm_atomic_helper.h>
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#include <drm/display/drm_dsc.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_gem.h>
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#include <drm/rockchip_drm.h>
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#include <linux/media-bus-format.h>
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#include <linux/module.h>
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#include <linux/component.h>
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#include <soc/rockchip/rockchip_dmc.h>
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#include "../panel/panel-simple.h"
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#include "rockchip_drm_debugfs.h"
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#define ROCKCHIP_MAX_FB_BUFFER 3
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#define ROCKCHIP_MAX_CONNECTOR 2
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#define ROCKCHIP_MAX_CRTC 4
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#define ROCKCHIP_MAX_LAYER 16
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struct drm_device;
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struct drm_connector;
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struct iommu_domain;
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#define VOP_COLOR_KEY_NONE (0 << 31)
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#define VOP_COLOR_KEY_MASK (1 << 31)
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#define VOP_OUTPUT_IF_RGB BIT(0)
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#define VOP_OUTPUT_IF_BT1120 BIT(1)
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#define VOP_OUTPUT_IF_BT656 BIT(2)
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#define VOP_OUTPUT_IF_LVDS0 BIT(3)
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#define VOP_OUTPUT_IF_LVDS1 BIT(4)
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#define VOP_OUTPUT_IF_MIPI0 BIT(5)
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#define VOP_OUTPUT_IF_MIPI1 BIT(6)
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#define VOP_OUTPUT_IF_eDP0 BIT(7)
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#define VOP_OUTPUT_IF_eDP1 BIT(8)
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#define VOP_OUTPUT_IF_DP0 BIT(9)
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#define VOP_OUTPUT_IF_DP1 BIT(10)
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#define VOP_OUTPUT_IF_HDMI0 BIT(11)
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#define VOP_OUTPUT_IF_HDMI1 BIT(12)
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#define VOP_OUTPUT_IF_DP2 BIT(13)
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#define RK_IF_PROP_COLOR_DEPTH "color_depth"
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#define RK_IF_PROP_COLOR_FORMAT "color_format"
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#define RK_IF_PROP_COLOR_DEPTH_CAPS "color_depth_caps"
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#define RK_IF_PROP_COLOR_FORMAT_CAPS "color_format_caps"
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#define RK_IF_PROP_ENCRYPTED "hdcp_encrypted"
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enum rockchip_drm_debug_category {
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VOP_DEBUG_PLANE = BIT(0),
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VOP_DEBUG_OVERLAY = BIT(1),
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VOP_DEBUG_WB = BIT(2),
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VOP_DEBUG_CFG_DONE = BIT(3),
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VOP_DEBUG_CLK = BIT(4),
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VOP_DEBUG_IOMMU_MAP = BIT(5),
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VOP_DEBUG_VSYNC = BIT(7),
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VOP_DEBUG_PIXEL_SHIFT = BIT(8),
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};
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enum rk_if_color_depth {
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RK_IF_DEPTH_8,
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RK_IF_DEPTH_10,
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RK_IF_DEPTH_12,
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RK_IF_DEPTH_16,
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RK_IF_DEPTH_420_10,
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RK_IF_DEPTH_420_12,
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RK_IF_DEPTH_420_16,
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RK_IF_DEPTH_6,
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RK_IF_DEPTH_MAX,
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};
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enum rk_if_color_format {
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RK_IF_FORMAT_RGB, /* default RGB */
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RK_IF_FORMAT_YCBCR444, /* YCBCR 444 */
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RK_IF_FORMAT_YCBCR422, /* YCBCR 422 */
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RK_IF_FORMAT_YCBCR420, /* YCBCR 420 */
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RK_IF_FORMAT_YCBCR_HQ, /* Highest subsampled YUV */
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RK_IF_FORMAT_YCBCR_LQ, /* Lowest subsampled YUV */
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RK_IF_FORMAT_MAX,
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};
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enum rockchip_hdcp_encrypted {
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RK_IF_HDCP_ENCRYPTED_NONE = 0,
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RK_IF_HDCP_ENCRYPTED_LEVEL1,
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RK_IF_HDCP_ENCRYPTED_LEVEL2,
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};
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enum rockchip_color_bar_mode {
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ROCKCHIP_COLOR_BAR_OFF = 0,
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ROCKCHIP_COLOR_BAR_HORIZONTAL = 1,
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ROCKCHIP_COLOR_BAR_VERTICAL = 2,
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};
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enum rockchip_drm_split_area {
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ROCKCHIP_DRM_SPLIT_UNSET = 0,
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ROCKCHIP_DRM_SPLIT_LEFT_SIDE = 1,
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ROCKCHIP_DRM_SPLIT_RIGHT_SIDE = 2,
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};
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enum rockchip_drm_vop_aclk_mode {
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ROCKCHIP_VOP_ACLK_NORMAL_MODE = 0,
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ROCKCHIP_VOP_ACLK_RESET_MODE,
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ROCKCHIP_VOP_ACLK_ADVANCED_MODE,
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ROCKCHIP_VOP_ACLK_MAX_MODE,
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};
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struct rockchip_drm_sub_dev {
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struct list_head list;
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struct drm_connector *connector;
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struct device_node *of_node;
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int (*loader_protect)(struct drm_encoder *encoder, bool on);
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void (*update_vfp_for_vrr)(struct drm_connector *connector, struct drm_display_mode *mode,
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int vfp);
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};
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struct rockchip_sdr2hdr_state {
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int sdr2hdr_func;
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bool bt1886eotf_pre_conv_en;
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bool rgb2rgb_pre_conv_en;
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bool rgb2rgb_pre_conv_mode;
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bool st2084oetf_pre_conv_en;
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bool bt1886eotf_post_conv_en;
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bool rgb2rgb_post_conv_en;
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bool rgb2rgb_post_conv_mode;
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bool st2084oetf_post_conv_en;
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};
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struct rockchip_hdr_state {
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bool pre_overlay;
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bool hdr2sdr_en;
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struct rockchip_sdr2hdr_state sdr2hdr_state;
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};
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struct rockchip_bcsh_state {
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int brightness;
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int contrast;
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int saturation;
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int sin_hue;
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int cos_hue;
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};
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struct rockchip_crtc {
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struct drm_crtc crtc;
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#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
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/**
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* @vop_dump_status the status of vop dump control
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* @vop_dump_times control the dump times
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* @vop_dump_frame_count the frame of dump buf
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*/
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enum vop_dump_status vop_dump_status;
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int vop_dump_times;
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int vop_dump_frame_count;
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#endif
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};
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struct rockchip_dsc_sink_cap {
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/**
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* @slice_width: the number of pixel columns that comprise the slice width
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* @slice_height: the number of pixel rows that comprise the slice height
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* @block_pred: Does block prediction
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* @native_420: Does sink support DSC with 4:2:0 compression
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* @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc
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* @version_major: DSC major version
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* @version_minor: DSC minor version
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* @target_bits_per_pixel_x16: bits num after compress and multiply 16
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*/
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u16 slice_width;
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u16 slice_height;
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bool block_pred;
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bool native_420;
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u8 bpc_supported;
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u8 version_major;
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u8 version_minor;
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u16 target_bits_per_pixel_x16;
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};
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#define ACM_GAIN_LUT_HY_LENGTH (9*17)
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#define ACM_GAIN_LUT_HY_TOTAL_LENGTH (ACM_GAIN_LUT_HY_LENGTH * 3)
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#define ACM_GAIN_LUT_HS_LENGTH (13*17)
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#define ACM_GAIN_LUT_HS_TOTAL_LENGTH (ACM_GAIN_LUT_HS_LENGTH * 3)
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#define ACM_DELTA_LUT_H_LENGTH 65
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#define ACM_DELTA_LUT_H_TOTAL_LENGTH (ACM_DELTA_LUT_H_LENGTH * 3)
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struct post_acm {
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s16 delta_lut_h[ACM_DELTA_LUT_H_TOTAL_LENGTH];
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s16 gain_lut_hy[ACM_GAIN_LUT_HY_TOTAL_LENGTH];
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s16 gain_lut_hs[ACM_GAIN_LUT_HS_TOTAL_LENGTH];
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u16 y_gain;
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u16 h_gain;
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u16 s_gain;
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u16 acm_enable;
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};
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struct post_csc {
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u16 hue;
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u16 saturation;
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u16 contrast;
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u16 brightness;
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u16 r_gain;
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u16 g_gain;
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u16 b_gain;
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u16 r_offset;
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u16 g_offset;
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u16 b_offset;
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u16 csc_enable;
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};
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#define ROCKCHIP_VOP_DCI_LUT_LENGTH 5632
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struct dci_data {
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u32 plat; /* Reserved to distinguish later platform */
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u8 dci_lut_data[ROCKCHIP_VOP_DCI_LUT_LENGTH];
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u32 blk_size_h_ratio;
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u32 blk_size_v_ratio;
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u32 dci_act_w;
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u32 dci_act_h;
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u32 adj0;
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u32 adj1;
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u32 uv_adj;
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u32 dci_en;
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};
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#define SHARP_REG_LENGTH 692
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struct post_sharp {
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u32 plat; /* Reserved to distinguish later platform */
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u32 regs[SHARP_REG_LENGTH / 4];
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};
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struct rockchip_crtc_state {
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struct drm_crtc_state base;
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int vp_id;
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int output_type;
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int output_mode;
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int output_bpc;
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int output_flags;
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bool enable_afbc;
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/**
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* @splice_mode: enabled when display a hdisplay > 4096 on rk3588
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*/
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bool splice_mode;
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/**
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* @hold_mode: enabled when it's:
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* (1) mcu hold mode
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* (2) mipi dsi cmd mode
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* (3) edp psr mode
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*/
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bool hold_mode;
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/**
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* when enable soft_te, use gpio irq to triggle new fs,
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* otherwise use hardware te
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*/
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bool soft_te;
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/**
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* sharp and post scaler share line buffer,
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* So they are mutually exclusive.
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*/
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bool sharp_en;
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struct drm_tv_connector_state *tv_state;
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int left_margin;
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int right_margin;
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int top_margin;
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int bottom_margin;
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int vdisplay;
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int afbdc_win_format;
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int afbdc_win_width;
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int afbdc_win_height;
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int afbdc_win_ptr;
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int afbdc_win_id;
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int afbdc_en;
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int afbdc_win_vir_width;
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int afbdc_win_xoffset;
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int afbdc_win_yoffset;
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int dsp_layer_sel;
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u32 output_if;
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u32 output_if_left_panel;
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u32 bus_format;
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u32 bus_flags;
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int yuv_overlay;
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int post_r2y_en;
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int post_y2r_en;
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int post_csc_mode;
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int bcsh_en;
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enum drm_color_encoding color_encoding;
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enum drm_color_range color_range;
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int eotf;
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u32 background;
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u32 line_flag;
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u8 mode_update;
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u8 dsc_id;
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u8 dsc_enable;
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u8 dsc_slice_num;
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u8 dsc_pixel_num;
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u64 dsc_txp_clk_rate;
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u64 dsc_pxl_clk_rate;
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u64 dsc_cds_clk_rate;
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struct drm_dsc_picture_parameter_set pps;
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struct rockchip_dsc_sink_cap dsc_sink_cap;
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struct rockchip_hdr_state hdr;
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struct drm_property_blob *hdr_ext_data;
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struct drm_property_blob *acm_lut_data;
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struct drm_property_blob *post_csc_data;
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struct drm_property_blob *post_sharp_data;
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struct drm_property_blob *cubic_lut_data;
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int request_refresh_rate;
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int max_refresh_rate;
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int min_refresh_rate;
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int shift_x;
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int shift_y;
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};
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#define to_rockchip_crtc_state(s) \
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container_of(s, struct rockchip_crtc_state, base)
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struct rockchip_drm_vcnt {
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struct drm_pending_vblank_event *event;
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__u32 sequence;
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int pipe;
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};
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struct rockchip_drm_error_event {
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wait_queue_head_t wait;
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struct task_struct *thread;
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struct list_head event_list;
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struct drm_event_vblank event;
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bool error_state;
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spinlock_t lock;
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};
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struct rockchip_logo {
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dma_addr_t dma_addr;
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struct drm_mm_node logo_reserved_node;
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void *kvaddr;
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phys_addr_t start;
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phys_addr_t size;
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int count;
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};
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struct rockchip_mcu_timing {
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int mcu_pix_total;
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int mcu_cs_pst;
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int mcu_cs_pend;
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int mcu_rw_pst;
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int mcu_rw_pend;
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int mcu_hold_mode;
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};
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struct vop_mcu_bypass_cfg {
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const struct rockchip_mcu_timing timing;
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unsigned long dclk_rate;
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};
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struct loader_cubic_lut {
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bool enable;
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u32 offset;
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};
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struct rockchip_drm_dsc_cap {
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bool v_1p2;
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bool native_420;
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bool all_bpp;
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u8 bpc_supported;
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u8 max_slices;
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u8 max_lanes;
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u8 max_frl_rate_per_lane;
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u8 total_chunk_kbytes;
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int clk_per_slice;
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};
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struct ver_26_v0 {
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u8 yuv422_12bit;
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u8 support_2160p_60;
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u8 global_dimming;
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u8 dm_major_ver;
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u8 dm_minor_ver;
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u16 t_min_pq;
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u16 t_max_pq;
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u16 rx;
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u16 ry;
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u16 gx;
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u16 gy;
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u16 bx;
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u16 by;
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u16 wx;
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u16 wy;
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} __packed;
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struct ver_15_v1 {
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u8 yuv422_12bit;
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u8 support_2160p_60;
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u8 global_dimming;
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u8 dm_version;
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u8 colorimetry;
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u8 t_max_lum;
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u8 t_min_lum;
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u8 rx;
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u8 ry;
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u8 gx;
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u8 gy;
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u8 bx;
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u8 by;
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} __packed;
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struct ver_12_v1 {
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u8 yuv422_12bit;
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u8 support_2160p_60;
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u8 global_dimming;
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u8 dm_version;
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u8 colorimetry;
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u8 low_latency;
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u8 t_max_lum;
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u8 t_min_lum;
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u8 unique_rx;
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u8 unique_ry;
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u8 unique_gx;
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u8 unique_gy;
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u8 unique_bx;
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u8 unique_by;
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} __packed;
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struct ver_12_v2 {
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u8 yuv422_12bit;
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u8 backlt_ctrl;
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u8 global_dimming;
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u8 dm_version;
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u8 backlt_min_luma;
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u8 interface;
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u8 yuv444_10b_12b;
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u8 t_min_pq_v2;
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u8 t_max_pq_v2;
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u8 unique_rx;
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u8 unique_ry;
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u8 unique_gx;
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u8 unique_gy;
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u8 unique_bx;
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u8 unique_by;
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} __packed;
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struct next_hdr_sink_data {
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u8 version;
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struct ver_26_v0 ver_26_v0;
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struct ver_15_v1 ver_15_v1;
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struct ver_12_v1 ver_12_v1;
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struct ver_12_v2 ver_12_v2;
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} __packed;
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/*
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* Rockchip drm private crtc funcs.
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* @loader_protect: protect loader logo crtc's power
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* @enable_vblank: enable crtc vblank irq.
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* @disable_vblank: disable crtc vblank irq.
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* @bandwidth: report present crtc bandwidth consume.
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* @cancel_pending_vblank: cancel pending vblank.
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* @debugfs_init: init crtc debugfs.
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* @debugfs_dump: debugfs to dump crtc and plane state.
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* @regs_dump: dump vop current register config.
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* @mode_valid: verify that the current mode is supported.
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* @crtc_close: close vop.
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* @crtc_send_mcu_cmd: send mcu panel init cmd.
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* @te_handler: soft te hand for cmd mode panel.
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* @wait_vact_end: wait the last active line.
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*/
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struct rockchip_crtc_funcs {
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int (*loader_protect)(struct drm_crtc *crtc, bool on, void *data);
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int (*enable_vblank)(struct drm_crtc *crtc);
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void (*disable_vblank)(struct drm_crtc *crtc);
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size_t (*bandwidth)(struct drm_crtc *crtc,
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struct drm_crtc_state *crtc_state,
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struct dmcfreq_vop_info *vop_bw_info);
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void (*cancel_pending_vblank)(struct drm_crtc *crtc,
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struct drm_file *file_priv);
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int (*sysfs_init)(struct device *dev, struct drm_crtc *crtc);
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int (*sysfs_fini)(struct device *dev, struct drm_crtc *crtc);
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int (*debugfs_init)(struct drm_minor *minor, struct drm_crtc *crtc);
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int (*debugfs_dump)(struct drm_crtc *crtc, struct seq_file *s);
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void (*regs_dump)(struct drm_crtc *crtc, struct seq_file *s);
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void (*active_regs_dump)(struct drm_crtc *crtc, struct seq_file *s);
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int (*regs_write)(struct drm_crtc *crtc, phys_addr_t address, u32 val);
|
|
enum drm_mode_status (*mode_valid)(struct drm_crtc *crtc,
|
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const struct drm_display_mode *mode,
|
|
int output_type);
|
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void (*crtc_close)(struct drm_crtc *crtc);
|
|
void (*crtc_send_mcu_cmd)(struct drm_crtc *crtc, u32 type, u32 value);
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void (*te_handler)(struct drm_crtc *crtc);
|
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int (*wait_vact_end)(struct drm_crtc *crtc, unsigned int mstimeout);
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void (*crtc_standby)(struct drm_crtc *crtc, bool standby);
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void (*crtc_output_post_enable)(struct drm_crtc *crtc, int intf);
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void (*crtc_output_pre_disable)(struct drm_crtc *crtc, int intf);
|
|
int (*crtc_set_color_bar)(struct drm_crtc *crtc, enum rockchip_color_bar_mode mode);
|
|
int (*set_aclk)(struct drm_crtc *crtc, enum rockchip_drm_vop_aclk_mode aclk_mode, struct dmcfreq_vop_info *vop_bw_info);
|
|
int (*get_crc)(struct drm_crtc *crtc);
|
|
void (*iommu_fault_handler)(struct drm_crtc *crtc, struct iommu_domain *iommu);
|
|
};
|
|
|
|
struct rockchip_dclk_pll {
|
|
struct clk *pll;
|
|
unsigned int use_count;
|
|
};
|
|
|
|
/*
|
|
* Rockchip drm private structure.
|
|
*
|
|
* @crtc: array of enabled CRTCs, used to map from "pipe" to drm_crtc.
|
|
* @num_pipe: number of pipes for this device.
|
|
* @mm_lock: protect drm_mm on multi-threads.
|
|
*/
|
|
struct rockchip_drm_private {
|
|
struct rockchip_logo *logo;
|
|
struct drm_fb_helper *fbdev_helper;
|
|
struct drm_gem_object *fbdev_bo;
|
|
struct iommu_domain *domain;
|
|
struct device *iommu_dev;
|
|
struct gen_pool *secure_buffer_pool;
|
|
struct mutex mm_lock;
|
|
struct drm_mm mm;
|
|
struct list_head psr_list;
|
|
struct mutex psr_list_lock;
|
|
struct mutex commit_lock;
|
|
|
|
/* private crtc prop */
|
|
struct drm_property *soc_id_prop;
|
|
struct drm_property *port_id_prop;
|
|
struct drm_property *aclk_prop;
|
|
struct drm_property *bg_prop;
|
|
struct drm_property *line_flag_prop;
|
|
struct drm_property *cubic_lut_prop;
|
|
struct drm_property *cubic_lut_size_prop;
|
|
|
|
/* private plane prop */
|
|
struct drm_property *eotf_prop;
|
|
struct drm_property *async_commit_prop;
|
|
struct drm_property *share_id_prop;
|
|
|
|
/* private connector prop */
|
|
struct drm_property *connector_id_prop;
|
|
struct drm_property *split_area_prop;
|
|
|
|
const struct rockchip_crtc_funcs *crtc_funcs[ROCKCHIP_MAX_CRTC];
|
|
|
|
uint64_t iommu_fault_count;
|
|
|
|
struct rockchip_dclk_pll default_pll;
|
|
struct rockchip_dclk_pll hdmi_pll;
|
|
|
|
/*
|
|
* protect some shared overlay resource
|
|
* OVL_LAYER_SEL/OVL_PORT_SEL
|
|
*/
|
|
struct mutex ovl_lock;
|
|
|
|
struct rockchip_drm_vcnt vcnt[ROCKCHIP_MAX_CRTC];
|
|
struct rockchip_drm_error_event error_event;
|
|
|
|
/**
|
|
* @loader_protect
|
|
* ignore restore_fbdev_mode_atomic when in logo on state
|
|
*/
|
|
bool loader_protect;
|
|
|
|
dma_addr_t cubic_lut_dma_addr;
|
|
void *cubic_lut_kvaddr;
|
|
int aclk_adjust_frame_num;
|
|
struct drm_mm_node *clut_reserved_node;
|
|
struct loader_cubic_lut cubic_lut[ROCKCHIP_MAX_CRTC];
|
|
|
|
struct device *sysfs_devs[ROCKCHIP_MAX_CRTC];
|
|
};
|
|
|
|
struct rockchip_encoder {
|
|
int crtc_endpoint_id;
|
|
struct drm_encoder encoder;
|
|
};
|
|
|
|
void rockchip_connector_update_vfp_for_vrr(struct drm_crtc *crtc, struct drm_display_mode *mode,
|
|
int vfp);
|
|
int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
|
|
struct device *dev);
|
|
void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
|
|
struct device *dev);
|
|
void rockchip_drm_dma_init_device(struct drm_device *drm_dev,
|
|
struct device *dev);
|
|
int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout);
|
|
int rockchip_register_crtc_funcs(struct drm_crtc *crtc,
|
|
const struct rockchip_crtc_funcs *crtc_funcs);
|
|
void rockchip_unregister_crtc_funcs(struct drm_crtc *crtc);
|
|
void rockchip_drm_crtc_standby(struct drm_crtc *crtc, bool standby);
|
|
void rockchip_drm_crtc_output_post_enable(struct drm_crtc *crtc, int intf);
|
|
void rockchip_drm_crtc_output_pre_disable(struct drm_crtc *crtc, int intf);
|
|
|
|
void rockchip_drm_register_sub_dev(struct rockchip_drm_sub_dev *sub_dev);
|
|
void rockchip_drm_unregister_sub_dev(struct rockchip_drm_sub_dev *sub_dev);
|
|
struct rockchip_drm_sub_dev *rockchip_drm_get_sub_dev(struct device_node *node);
|
|
int rockchip_drm_add_modes_noedid(struct drm_connector *connector);
|
|
void rockchip_drm_te_handle(struct drm_crtc *crtc);
|
|
void drm_mode_convert_to_split_mode(struct drm_display_mode *mode);
|
|
void drm_mode_convert_to_origin_mode(struct drm_display_mode *mode);
|
|
const char *rockchip_drm_get_color_encoding_name(enum drm_color_encoding encoding);
|
|
const char *rockchip_drm_get_color_range_name(enum drm_color_range range);
|
|
#if IS_REACHABLE(CONFIG_DRM_ROCKCHIP)
|
|
int rockchip_drm_get_sub_dev_type(void);
|
|
u32 rockchip_drm_get_scan_line_time_ns(void);
|
|
#else
|
|
static inline int rockchip_drm_get_sub_dev_type(void)
|
|
{
|
|
return DRM_MODE_CONNECTOR_Unknown;
|
|
}
|
|
|
|
static inline u32 rockchip_drm_get_scan_line_time_ns(void)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int rockchip_drm_endpoint_is_subdriver(struct device_node *ep);
|
|
uint32_t rockchip_drm_of_find_possible_crtcs(struct drm_device *dev,
|
|
struct device_node *port);
|
|
uint32_t rockchip_drm_get_bpp(const struct drm_format_info *info);
|
|
uint32_t rockchip_drm_get_cycles_per_pixel(uint32_t bus_format);
|
|
int rockchip_drm_get_yuv422_format(struct drm_connector *connector,
|
|
const struct edid *edid);
|
|
int rockchip_drm_parse_cea_ext(struct rockchip_drm_dsc_cap *dsc_cap,
|
|
u8 *max_frl_rate_per_lane, u8 *max_lanes, u8 *add_func,
|
|
const struct edid *edid);
|
|
int rockchip_drm_parse_next_hdr(struct next_hdr_sink_data *sink_data,
|
|
const struct edid *edid);
|
|
int rockchip_drm_parse_colorimetry_data_block(u8 *colorimetry, const struct edid *edid);
|
|
struct dma_buf *rockchip_drm_gem_prime_export(struct drm_gem_object *obj, int flags);
|
|
long rockchip_drm_dclk_round_rate(u32 version, struct clk *dclk, unsigned long rate);
|
|
int rockchip_drm_dclk_set_rate(u32 version, struct clk *dclk, unsigned long rate);
|
|
bool rockchip_drm_is_afbc(struct drm_plane *plane, u64 modifier);
|
|
bool rockchip_drm_is_rfbc(struct drm_plane *plane, u64 modifier);
|
|
const char *rockchip_drm_modifier_to_string(uint64_t modifier);
|
|
void rockchip_drm_reset_iommu_fault_handler_rate_limit(void);
|
|
void rockchip_drm_send_error_event(struct rockchip_drm_private *priv,
|
|
enum rockchip_drm_error_event_type event);
|
|
|
|
__printf(3, 4)
|
|
void rockchip_drm_dbg(const struct device *dev,
|
|
enum rockchip_drm_debug_category category,
|
|
const char *format, ...);
|
|
__printf(3, 4)
|
|
void rockchip_drm_dbg_thread_info(const struct device *dev,
|
|
enum rockchip_drm_debug_category category,
|
|
const char *format, ...);
|
|
|
|
extern struct platform_driver cdn_dp_driver;
|
|
extern struct platform_driver dw_hdmi_rockchip_pltfm_driver;
|
|
extern struct platform_driver dw_mipi_dsi_rockchip_driver;
|
|
extern struct platform_driver dw_mipi_dsi2_rockchip_driver;
|
|
extern struct platform_driver inno_hdmi_driver;
|
|
extern struct platform_driver rockchip_dp_driver;
|
|
extern struct platform_driver rockchip_lvds_driver;
|
|
extern struct platform_driver vop_platform_driver;
|
|
extern struct platform_driver rk3066_hdmi_driver;
|
|
extern struct platform_driver vop2_platform_driver;
|
|
extern struct platform_driver rockchip_rgb_driver;
|
|
extern struct platform_driver rockchip_tve_driver;
|
|
extern struct platform_driver dw_dp_driver;
|
|
extern struct platform_driver vconn_platform_driver;
|
|
extern struct platform_driver vvop_platform_driver;
|
|
|
|
static inline struct rockchip_encoder *to_rockchip_encoder(struct drm_encoder *encoder)
|
|
{
|
|
return container_of(encoder, struct rockchip_encoder, encoder);
|
|
}
|
|
|
|
#endif /* _ROCKCHIP_DRM_DRV_H_ */
|