390 lines
10 KiB
C
390 lines
10 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018 Intel Corporation. All rights reserved.
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//
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// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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// Rander Wang <rander.wang@intel.com>
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// Keyon Jie <yang.jie@linux.intel.com>
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//
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/*
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* Hardware interface for generic Intel audio DSP HDA IP
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*/
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#include <sound/sof/ipc4/header.h>
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#include <trace/events/sof_intel.h>
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#include "../ops.h"
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#include "hda.h"
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static void hda_dsp_ipc_host_done(struct snd_sof_dev *sdev)
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{
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/*
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* tell DSP cmd is done - clear busy
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* interrupt and send reply msg to dsp
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*/
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snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCT,
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HDA_DSP_REG_HIPCT_BUSY,
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HDA_DSP_REG_HIPCT_BUSY);
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/* unmask BUSY interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCCTL,
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HDA_DSP_REG_HIPCCTL_BUSY,
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HDA_DSP_REG_HIPCCTL_BUSY);
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}
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static void hda_dsp_ipc_dsp_done(struct snd_sof_dev *sdev)
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{
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/*
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* set DONE bit - tell DSP we have received the reply msg
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* from DSP, and processed it, don't send more reply to host
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*/
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snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCIE,
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HDA_DSP_REG_HIPCIE_DONE,
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HDA_DSP_REG_HIPCIE_DONE);
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/* unmask Done interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCCTL,
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HDA_DSP_REG_HIPCCTL_DONE,
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HDA_DSP_REG_HIPCCTL_DONE);
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}
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int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
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{
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/* send IPC message to DSP */
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sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
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msg->msg_size);
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI,
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HDA_DSP_REG_HIPCI_BUSY);
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return 0;
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}
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int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
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{
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struct sof_ipc4_msg *msg_data = msg->msg_data;
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/* send the message via mailbox */
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if (msg_data->data_size)
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sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr,
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msg_data->data_size);
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE, msg_data->extension);
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI,
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msg_data->primary | HDA_DSP_REG_HIPCI_BUSY);
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return 0;
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}
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void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev)
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{
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struct snd_sof_ipc_msg *msg = sdev->msg;
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struct sof_ipc_reply reply;
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struct sof_ipc_cmd_hdr *hdr;
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/*
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* Sometimes, there is unexpected reply ipc arriving. The reply
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* ipc belongs to none of the ipcs sent from driver.
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* In this case, the driver must ignore the ipc.
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*/
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if (!msg) {
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dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
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return;
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}
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hdr = msg->msg_data;
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if (hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE) ||
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hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) {
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/*
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* memory windows are powered off before sending IPC reply,
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* so we can't read the mailbox for CTX_SAVE and PM_GATE
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* replies.
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*/
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reply.error = 0;
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reply.hdr.cmd = SOF_IPC_GLB_REPLY;
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reply.hdr.size = sizeof(reply);
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memcpy(msg->reply_data, &reply, sizeof(reply));
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msg->reply_error = 0;
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} else {
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snd_sof_ipc_get_reply(sdev);
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}
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}
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irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context)
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{
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struct sof_ipc4_msg notification_data = {{ 0 }};
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struct snd_sof_dev *sdev = context;
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bool ipc_irq = false;
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u32 hipcie, hipct;
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hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
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if (hipcie & HDA_DSP_REG_HIPCIE_DONE) {
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/* DSP received the message */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL,
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HDA_DSP_REG_HIPCCTL_DONE, 0);
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hda_dsp_ipc_dsp_done(sdev);
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ipc_irq = true;
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}
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hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
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if (hipct & HDA_DSP_REG_HIPCT_BUSY) {
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/* Message from DSP (reply or notification) */
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u32 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCTE);
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u32 primary = hipct & HDA_DSP_REG_HIPCT_MSG_MASK;
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u32 extension = hipcte & HDA_DSP_REG_HIPCTE_MSG_MASK;
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/* mask BUSY interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL,
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HDA_DSP_REG_HIPCCTL_BUSY, 0);
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if (primary & SOF_IPC4_MSG_DIR_MASK) {
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/* Reply received */
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if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
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struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data;
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data->primary = primary;
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data->extension = extension;
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spin_lock_irq(&sdev->ipc_lock);
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snd_sof_ipc_get_reply(sdev);
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snd_sof_ipc_reply(sdev, data->primary);
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spin_unlock_irq(&sdev->ipc_lock);
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} else {
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dev_dbg_ratelimited(sdev->dev,
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"IPC reply before FW_READY: %#x|%#x\n",
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primary, extension);
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}
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} else {
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/* Notification received */
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notification_data.primary = primary;
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notification_data.extension = extension;
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sdev->ipc->msg.rx_data = ¬ification_data;
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snd_sof_ipc_msgs_rx(sdev);
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sdev->ipc->msg.rx_data = NULL;
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}
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/* Let DSP know that we have finished processing the message */
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hda_dsp_ipc_host_done(sdev);
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ipc_irq = true;
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}
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if (!ipc_irq)
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/* This interrupt is not shared so no need to return IRQ_NONE. */
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dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
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return IRQ_HANDLED;
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}
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/* IPC handler thread */
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irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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u32 hipci;
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u32 hipcie;
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u32 hipct;
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u32 hipcte;
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u32 msg;
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u32 msg_ext;
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bool ipc_irq = false;
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/* read IPC status */
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hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCIE);
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hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
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hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI);
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hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE);
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/* is this a reply message from the DSP */
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if (hipcie & HDA_DSP_REG_HIPCIE_DONE) {
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msg = hipci & HDA_DSP_REG_HIPCI_MSG_MASK;
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msg_ext = hipcie & HDA_DSP_REG_HIPCIE_MSG_MASK;
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trace_sof_intel_ipc_firmware_response(sdev, msg, msg_ext);
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/* mask Done interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCCTL,
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HDA_DSP_REG_HIPCCTL_DONE, 0);
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/*
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* Make sure the interrupt thread cannot be preempted between
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* waking up the sender and re-enabling the interrupt. Also
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* protect against a theoretical race with sof_ipc_tx_message():
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* if the DSP is fast enough to receive an IPC message, reply to
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* it, and the host interrupt processing calls this function on
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* a different core from the one, where the sending is taking
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* place, the message might not yet be marked as expecting a
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* reply.
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*/
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if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
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spin_lock_irq(&sdev->ipc_lock);
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/* handle immediate reply from DSP core */
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hda_dsp_ipc_get_reply(sdev);
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snd_sof_ipc_reply(sdev, msg);
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/* set the done bit */
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hda_dsp_ipc_dsp_done(sdev);
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spin_unlock_irq(&sdev->ipc_lock);
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} else {
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dev_dbg_ratelimited(sdev->dev, "IPC reply before FW_READY: %#x\n",
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msg);
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}
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ipc_irq = true;
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}
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/* is this a new message from DSP */
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if (hipct & HDA_DSP_REG_HIPCT_BUSY) {
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msg = hipct & HDA_DSP_REG_HIPCT_MSG_MASK;
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msg_ext = hipcte & HDA_DSP_REG_HIPCTE_MSG_MASK;
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trace_sof_intel_ipc_firmware_initiated(sdev, msg, msg_ext);
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/* mask BUSY interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCCTL,
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HDA_DSP_REG_HIPCCTL_BUSY, 0);
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/* handle messages from DSP */
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if ((hipct & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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bool non_recoverable = true;
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/*
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* This is a PANIC message!
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*
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* If it is arriving during firmware boot and it is not
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* the last boot attempt then change the non_recoverable
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* to false as the DSP might be able to boot in the next
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* iteration(s)
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*/
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if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS &&
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hda->boot_iteration < HDA_FW_BOOT_ATTEMPTS)
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non_recoverable = false;
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snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext),
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non_recoverable);
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} else {
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/* normal message - process normally */
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snd_sof_ipc_msgs_rx(sdev);
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}
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hda_dsp_ipc_host_done(sdev);
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ipc_irq = true;
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}
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if (!ipc_irq) {
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/*
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* This interrupt is not shared so no need to return IRQ_NONE.
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*/
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dev_dbg_ratelimited(sdev->dev,
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"nothing to do in IPC IRQ thread\n");
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}
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return IRQ_HANDLED;
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}
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/* Check if an IPC IRQ occurred */
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bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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bool ret = false;
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u32 irq_status;
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/* store status */
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irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
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trace_sof_intel_hda_irq_ipc_check(sdev, irq_status);
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/* invalid message ? */
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if (irq_status == 0xffffffff)
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goto out;
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/* IPC message ? */
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if (irq_status & HDA_DSP_ADSPIS_IPC)
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ret = true;
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/* CLDMA message ? */
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if (irq_status & HDA_DSP_ADSPIS_CL_DMA) {
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hda->code_loading = 0;
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wake_up(&hda->waitq);
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ret = false;
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}
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out:
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return ret;
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}
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int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
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{
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return HDA_DSP_MBOX_UPLINK_OFFSET;
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}
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int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
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{
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return SRAM_WINDOW_OFFSET(id);
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}
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int hda_ipc_msg_data(struct snd_sof_dev *sdev,
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struct snd_pcm_substream *substream,
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void *p, size_t sz)
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{
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if (!substream || !sdev->stream_box.size) {
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sof_mailbox_read(sdev, sdev->dsp_box.offset, p, sz);
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} else {
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struct hdac_stream *hstream = substream->runtime->private_data;
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struct sof_intel_hda_stream *hda_stream;
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hda_stream = container_of(hstream,
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struct sof_intel_hda_stream,
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hext_stream.hstream);
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/* The stream might already be closed */
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if (!hstream)
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return -ESTRPIPE;
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sof_mailbox_read(sdev, hda_stream->sof_intel_stream.posn_offset, p, sz);
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}
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return 0;
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}
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int hda_set_stream_data_offset(struct snd_sof_dev *sdev,
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struct snd_pcm_substream *substream,
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size_t posn_offset)
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{
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struct hdac_stream *hstream = substream->runtime->private_data;
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struct sof_intel_hda_stream *hda_stream;
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hda_stream = container_of(hstream, struct sof_intel_hda_stream,
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hext_stream.hstream);
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/* check for unaligned offset or overflow */
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if (posn_offset > sdev->stream_box.size ||
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posn_offset % sizeof(struct sof_ipc_stream_posn) != 0)
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return -EINVAL;
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hda_stream->sof_intel_stream.posn_offset = sdev->stream_box.offset + posn_offset;
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dev_dbg(sdev->dev, "pcm: stream dir %d, posn mailbox offset is %zu",
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substream->stream, hda_stream->sof_intel_stream.posn_offset);
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return 0;
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}
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