704 lines
18 KiB
C
704 lines
18 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018 Intel Corporation. All rights reserved.
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//
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// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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//
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/*
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* Hardware interface for audio DSP on Broadwell
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*/
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#include <linux/module.h>
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#include <sound/sof.h>
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#include <sound/sof/xtensa.h>
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#include <sound/soc-acpi.h>
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#include <sound/soc-acpi-intel-match.h>
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#include <sound/intel-dsp-config.h>
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#include "../ops.h"
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#include "shim.h"
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#include "../sof-acpi-dev.h"
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#include "../sof-audio.h"
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/* BARs */
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#define BDW_DSP_BAR 0
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#define BDW_PCI_BAR 1
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/*
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* Debug
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*/
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/* DSP memories for BDW */
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#define IRAM_OFFSET 0xA0000
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#define BDW_IRAM_SIZE (10 * 32 * 1024)
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#define DRAM_OFFSET 0x00000
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#define BDW_DRAM_SIZE (20 * 32 * 1024)
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#define SHIM_OFFSET 0xFB000
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#define SHIM_SIZE 0x100
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#define MBOX_OFFSET 0x9E000
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#define MBOX_SIZE 0x1000
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#define MBOX_DUMP_SIZE 0x30
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#define EXCEPT_OFFSET 0x800
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#define EXCEPT_MAX_HDR_SIZE 0x400
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/* DSP peripherals */
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#define DMAC0_OFFSET 0xFE000
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#define DMAC1_OFFSET 0xFF000
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#define DMAC_SIZE 0x420
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#define SSP0_OFFSET 0xFC000
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#define SSP1_OFFSET 0xFD000
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#define SSP_SIZE 0x100
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#define BDW_STACK_DUMP_SIZE 32
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#define BDW_PANIC_OFFSET(x) ((x) & 0xFFFF)
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static const struct snd_sof_debugfs_map bdw_debugfs[] = {
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{"dmac0", BDW_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"dmac1", BDW_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"ssp0", BDW_DSP_BAR, SSP0_OFFSET, SSP_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"ssp1", BDW_DSP_BAR, SSP1_OFFSET, SSP_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"iram", BDW_DSP_BAR, IRAM_OFFSET, BDW_IRAM_SIZE,
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SOF_DEBUGFS_ACCESS_D0_ONLY},
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{"dram", BDW_DSP_BAR, DRAM_OFFSET, BDW_DRAM_SIZE,
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SOF_DEBUGFS_ACCESS_D0_ONLY},
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{"shim", BDW_DSP_BAR, SHIM_OFFSET, SHIM_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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};
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static void bdw_host_done(struct snd_sof_dev *sdev);
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static void bdw_dsp_done(struct snd_sof_dev *sdev);
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/*
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* DSP Control.
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*/
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static int bdw_run(struct snd_sof_dev *sdev)
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{
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/* set opportunistic mode on engine 0,1 for all channels */
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snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,
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SHIM_HMDC_HDDA_E0_ALLCH |
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SHIM_HMDC_HDDA_E1_ALLCH, 0);
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/* set DSP to RUN */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
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SHIM_CSR_STALL, 0x0);
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/* return init core mask */
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return 1;
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}
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static int bdw_reset(struct snd_sof_dev *sdev)
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{
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/* put DSP into reset and stall */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
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SHIM_CSR_RST | SHIM_CSR_STALL,
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SHIM_CSR_RST | SHIM_CSR_STALL);
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/* keep in reset for 10ms */
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mdelay(10);
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/* take DSP out of reset and keep stalled for FW loading */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
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SHIM_CSR_RST | SHIM_CSR_STALL,
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SHIM_CSR_STALL);
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return 0;
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}
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static int bdw_set_dsp_D0(struct snd_sof_dev *sdev)
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{
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int tries = 10;
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u32 reg;
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/* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
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PCI_VDRTCL2_DCLCGE |
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PCI_VDRTCL2_DTCGE, 0);
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/* Disable D3PG (VDRTCTL0.D3PGD = 1) */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,
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PCI_VDRTCL0_D3PGD, PCI_VDRTCL0_D3PGD);
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/* Set D0 state */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_PMCS,
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PCI_PMCS_PS_MASK, 0);
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/* check that ADSP shim is enabled */
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while (tries--) {
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reg = readl(sdev->bar[BDW_PCI_BAR] + PCI_PMCS)
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& PCI_PMCS_PS_MASK;
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if (reg == 0)
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goto finish;
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msleep(20);
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}
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return -ENODEV;
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finish:
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/*
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* select SSP1 19.2MHz base clock, SSP clock 0,
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* turn off Low Power Clock
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*/
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
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SHIM_CSR_S1IOCS | SHIM_CSR_SBCS1 |
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SHIM_CSR_LPCS, 0x0);
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/* stall DSP core, set clk to 192/96Mhz */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
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SHIM_CSR, SHIM_CSR_STALL |
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SHIM_CSR_DCS_MASK,
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SHIM_CSR_STALL |
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SHIM_CSR_DCS(4));
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/* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CLKCTL,
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SHIM_CLKCTL_MASK |
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SHIM_CLKCTL_DCPLCG |
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SHIM_CLKCTL_SCOE0,
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SHIM_CLKCTL_MASK |
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SHIM_CLKCTL_DCPLCG |
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SHIM_CLKCTL_SCOE0);
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/* Stall and reset core, set CSR */
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bdw_reset(sdev);
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/* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
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PCI_VDRTCL2_DCLCGE |
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PCI_VDRTCL2_DTCGE,
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PCI_VDRTCL2_DCLCGE |
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PCI_VDRTCL2_DTCGE);
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usleep_range(50, 55);
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/* switch on audio PLL */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
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PCI_VDRTCL2_APLLSE_MASK, 0);
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/*
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* set default power gating control, enable power gating control for
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* all blocks. that is, can't be accessed, please enable each block
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* before accessing.
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*/
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,
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0xfffffffC, 0x0);
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/* disable DMA finish function for SSP0 & SSP1 */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR2,
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SHIM_CSR2_SDFD_SSP1,
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SHIM_CSR2_SDFD_SSP1);
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/* set on-demond mode on engine 0,1 for all channels */
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snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,
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SHIM_HMDC_HDDA_E0_ALLCH |
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SHIM_HMDC_HDDA_E1_ALLCH,
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SHIM_HMDC_HDDA_E0_ALLCH |
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SHIM_HMDC_HDDA_E1_ALLCH);
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/* Enable Interrupt from both sides */
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snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRX,
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(SHIM_IMRX_BUSY | SHIM_IMRX_DONE), 0x0);
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snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRD,
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(SHIM_IMRD_DONE | SHIM_IMRD_BUSY |
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SHIM_IMRD_SSP0 | SHIM_IMRD_DMAC), 0x0);
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/* clear IPC registers */
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snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, 0x0);
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snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCD, 0x0);
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snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0x80, 0x6);
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snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0xe0, 0x300a);
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return 0;
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}
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static void bdw_get_registers(struct snd_sof_dev *sdev,
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struct sof_ipc_dsp_oops_xtensa *xoops,
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struct sof_ipc_panic_info *panic_info,
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u32 *stack, size_t stack_words)
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{
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u32 offset = sdev->dsp_oops_offset;
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/* first read registers */
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sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
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/* note: variable AR register array is not read */
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/* then get panic info */
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if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
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dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
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xoops->arch_hdr.totalsize);
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return;
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}
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offset += xoops->arch_hdr.totalsize;
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sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
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/* then get the stack */
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offset += sizeof(*panic_info);
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sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
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}
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static void bdw_dump(struct snd_sof_dev *sdev, u32 flags)
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{
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struct sof_ipc_dsp_oops_xtensa xoops;
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struct sof_ipc_panic_info panic_info;
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u32 stack[BDW_STACK_DUMP_SIZE];
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u32 status, panic, imrx, imrd;
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/* now try generic SOF status messages */
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status = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);
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panic = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);
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bdw_get_registers(sdev, &xoops, &panic_info, stack,
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BDW_STACK_DUMP_SIZE);
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sof_print_oops_and_stack(sdev, KERN_ERR, status, panic, &xoops,
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&panic_info, stack, BDW_STACK_DUMP_SIZE);
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/* provide some context for firmware debug */
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imrx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IMRX);
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imrd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IMRD);
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dev_err(sdev->dev,
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"error: ipc host -> DSP: pending %s complete %s raw 0x%8.8x\n",
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(panic & SHIM_IPCX_BUSY) ? "yes" : "no",
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(panic & SHIM_IPCX_DONE) ? "yes" : "no", panic);
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dev_err(sdev->dev,
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"error: mask host: pending %s complete %s raw 0x%8.8x\n",
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(imrx & SHIM_IMRX_BUSY) ? "yes" : "no",
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(imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx);
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dev_err(sdev->dev,
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"error: ipc DSP -> host: pending %s complete %s raw 0x%8.8x\n",
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(status & SHIM_IPCD_BUSY) ? "yes" : "no",
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(status & SHIM_IPCD_DONE) ? "yes" : "no", status);
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dev_err(sdev->dev,
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"error: mask DSP: pending %s complete %s raw 0x%8.8x\n",
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(imrd & SHIM_IMRD_BUSY) ? "yes" : "no",
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(imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd);
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}
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/*
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* IPC Doorbell IRQ handler and thread.
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*/
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static irqreturn_t bdw_irq_handler(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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u32 isr;
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int ret = IRQ_NONE;
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/* Interrupt arrived, check src */
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isr = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_ISRX);
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if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY))
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ret = IRQ_WAKE_THREAD;
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return ret;
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}
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static irqreturn_t bdw_irq_thread(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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u32 ipcx, ipcd, imrx;
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imrx = snd_sof_dsp_read64(sdev, BDW_DSP_BAR, SHIM_IMRX);
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ipcx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);
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/* reply message from DSP */
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if (ipcx & SHIM_IPCX_DONE &&
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!(imrx & SHIM_IMRX_DONE)) {
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/* Mask Done interrupt before return */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
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SHIM_IMRX, SHIM_IMRX_DONE,
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SHIM_IMRX_DONE);
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spin_lock_irq(&sdev->ipc_lock);
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/*
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* handle immediate reply from DSP core. If the msg is
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* found, set done bit in cmd_done which is called at the
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* end of message processing function, else set it here
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* because the done bit can't be set in cmd_done function
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* which is triggered by msg
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*/
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snd_sof_ipc_process_reply(sdev, ipcx);
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bdw_dsp_done(sdev);
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spin_unlock_irq(&sdev->ipc_lock);
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}
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ipcd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);
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/* new message from DSP */
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if (ipcd & SHIM_IPCD_BUSY &&
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!(imrx & SHIM_IMRX_BUSY)) {
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/* Mask Busy interrupt before return */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
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SHIM_IMRX, SHIM_IMRX_BUSY,
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SHIM_IMRX_BUSY);
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/* Handle messages from DSP Core */
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if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
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snd_sof_dsp_panic(sdev, BDW_PANIC_OFFSET(ipcx) + MBOX_OFFSET,
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true);
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} else {
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snd_sof_ipc_msgs_rx(sdev);
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}
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bdw_host_done(sdev);
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}
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return IRQ_HANDLED;
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}
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/*
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* IPC Mailbox IO
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*/
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static int bdw_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
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{
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/* send the message */
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sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
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msg->msg_size);
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snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, SHIM_IPCX_BUSY);
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return 0;
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}
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static int bdw_get_mailbox_offset(struct snd_sof_dev *sdev)
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{
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return MBOX_OFFSET;
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}
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static int bdw_get_window_offset(struct snd_sof_dev *sdev, u32 id)
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{
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return MBOX_OFFSET;
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}
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static void bdw_host_done(struct snd_sof_dev *sdev)
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{
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/* clear BUSY bit and set DONE bit - accept new messages */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCD,
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SHIM_IPCD_BUSY | SHIM_IPCD_DONE,
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SHIM_IPCD_DONE);
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/* unmask busy interrupt */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
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SHIM_IMRX_BUSY, 0);
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}
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static void bdw_dsp_done(struct snd_sof_dev *sdev)
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{
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/* clear DONE bit - tell DSP we have completed */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCX,
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SHIM_IPCX_DONE, 0);
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/* unmask Done interrupt */
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snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
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SHIM_IMRX_DONE, 0);
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}
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/*
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* Probe and remove.
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*/
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static int bdw_probe(struct snd_sof_dev *sdev)
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{
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struct snd_sof_pdata *pdata = sdev->pdata;
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const struct sof_dev_desc *desc = pdata->desc;
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struct platform_device *pdev =
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container_of(sdev->dev, struct platform_device, dev);
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const struct sof_intel_dsp_desc *chip;
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struct resource *mmio;
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u32 base, size;
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int ret;
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chip = get_chip_info(sdev->pdata);
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if (!chip) {
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dev_err(sdev->dev, "error: no such device supported\n");
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return -EIO;
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}
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sdev->num_cores = chip->cores_num;
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/* LPE base */
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mmio = platform_get_resource(pdev, IORESOURCE_MEM,
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desc->resindex_lpe_base);
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if (mmio) {
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base = mmio->start;
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size = resource_size(mmio);
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} else {
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dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
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desc->resindex_lpe_base);
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return -EINVAL;
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}
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dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
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sdev->bar[BDW_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
|
|
if (!sdev->bar[BDW_DSP_BAR]) {
|
|
dev_err(sdev->dev,
|
|
"error: failed to ioremap LPE base 0x%x size 0x%x\n",
|
|
base, size);
|
|
return -ENODEV;
|
|
}
|
|
dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BDW_DSP_BAR]);
|
|
|
|
/* TODO: add offsets */
|
|
sdev->mmio_bar = BDW_DSP_BAR;
|
|
sdev->mailbox_bar = BDW_DSP_BAR;
|
|
sdev->dsp_oops_offset = MBOX_OFFSET;
|
|
|
|
/* PCI base */
|
|
mmio = platform_get_resource(pdev, IORESOURCE_MEM,
|
|
desc->resindex_pcicfg_base);
|
|
if (mmio) {
|
|
base = mmio->start;
|
|
size = resource_size(mmio);
|
|
} else {
|
|
dev_err(sdev->dev, "error: failed to get PCI base at idx %d\n",
|
|
desc->resindex_pcicfg_base);
|
|
return -ENODEV;
|
|
}
|
|
|
|
dev_dbg(sdev->dev, "PCI base at 0x%x size 0x%x", base, size);
|
|
sdev->bar[BDW_PCI_BAR] = devm_ioremap(sdev->dev, base, size);
|
|
if (!sdev->bar[BDW_PCI_BAR]) {
|
|
dev_err(sdev->dev,
|
|
"error: failed to ioremap PCI base 0x%x size 0x%x\n",
|
|
base, size);
|
|
return -ENODEV;
|
|
}
|
|
dev_dbg(sdev->dev, "PCI VADDR %p\n", sdev->bar[BDW_PCI_BAR]);
|
|
|
|
/* register our IRQ */
|
|
sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
|
|
if (sdev->ipc_irq < 0)
|
|
return sdev->ipc_irq;
|
|
|
|
dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
|
|
ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
|
|
bdw_irq_handler, bdw_irq_thread,
|
|
IRQF_SHARED, "AudioDSP", sdev);
|
|
if (ret < 0) {
|
|
dev_err(sdev->dev, "error: failed to register IRQ %d\n",
|
|
sdev->ipc_irq);
|
|
return ret;
|
|
}
|
|
|
|
/* enable the DSP SHIM */
|
|
ret = bdw_set_dsp_D0(sdev);
|
|
if (ret < 0) {
|
|
dev_err(sdev->dev, "error: failed to set DSP D0\n");
|
|
return ret;
|
|
}
|
|
|
|
/* DSP DMA can only access low 31 bits of host memory */
|
|
ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
|
|
if (ret < 0) {
|
|
dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
/* set default mailbox offset for FW ready message */
|
|
sdev->dsp_box.offset = MBOX_OFFSET;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct snd_soc_acpi_mach *bdw_machine_select(struct snd_sof_dev *sdev)
|
|
{
|
|
struct snd_sof_pdata *sof_pdata = sdev->pdata;
|
|
const struct sof_dev_desc *desc = sof_pdata->desc;
|
|
struct snd_soc_acpi_mach *mach;
|
|
|
|
mach = snd_soc_acpi_find_machine(desc->machines);
|
|
if (!mach) {
|
|
dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n");
|
|
return NULL;
|
|
}
|
|
|
|
sof_pdata->tplg_filename = mach->sof_tplg_filename;
|
|
mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc;
|
|
|
|
return mach;
|
|
}
|
|
|
|
static void bdw_set_mach_params(struct snd_soc_acpi_mach *mach,
|
|
struct snd_sof_dev *sdev)
|
|
{
|
|
struct snd_sof_pdata *pdata = sdev->pdata;
|
|
const struct sof_dev_desc *desc = pdata->desc;
|
|
struct snd_soc_acpi_mach_params *mach_params;
|
|
|
|
mach_params = &mach->mach_params;
|
|
mach_params->platform = dev_name(sdev->dev);
|
|
mach_params->num_dai_drivers = desc->ops->num_drv;
|
|
mach_params->dai_drivers = desc->ops->drv;
|
|
}
|
|
|
|
/* Broadwell DAIs */
|
|
static struct snd_soc_dai_driver bdw_dai[] = {
|
|
{
|
|
.name = "ssp0-port",
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 8,
|
|
},
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 8,
|
|
},
|
|
},
|
|
{
|
|
.name = "ssp1-port",
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 8,
|
|
},
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 8,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* broadwell ops */
|
|
static struct snd_sof_dsp_ops sof_bdw_ops = {
|
|
/*Device init */
|
|
.probe = bdw_probe,
|
|
|
|
/* DSP Core Control */
|
|
.run = bdw_run,
|
|
.reset = bdw_reset,
|
|
|
|
/* Register IO */
|
|
.write = sof_io_write,
|
|
.read = sof_io_read,
|
|
.write64 = sof_io_write64,
|
|
.read64 = sof_io_read64,
|
|
|
|
/* Block IO */
|
|
.block_read = sof_block_read,
|
|
.block_write = sof_block_write,
|
|
|
|
/* Mailbox IO */
|
|
.mailbox_read = sof_mailbox_read,
|
|
.mailbox_write = sof_mailbox_write,
|
|
|
|
/* ipc */
|
|
.send_msg = bdw_send_msg,
|
|
.get_mailbox_offset = bdw_get_mailbox_offset,
|
|
.get_window_offset = bdw_get_window_offset,
|
|
|
|
.ipc_msg_data = sof_ipc_msg_data,
|
|
.set_stream_data_offset = sof_set_stream_data_offset,
|
|
|
|
/* machine driver */
|
|
.machine_select = bdw_machine_select,
|
|
.machine_register = sof_machine_register,
|
|
.machine_unregister = sof_machine_unregister,
|
|
.set_mach_params = bdw_set_mach_params,
|
|
|
|
/* debug */
|
|
.debug_map = bdw_debugfs,
|
|
.debug_map_count = ARRAY_SIZE(bdw_debugfs),
|
|
.dbg_dump = bdw_dump,
|
|
.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
|
|
|
|
/* stream callbacks */
|
|
.pcm_open = sof_stream_pcm_open,
|
|
.pcm_close = sof_stream_pcm_close,
|
|
|
|
/*Firmware loading */
|
|
.load_firmware = snd_sof_load_firmware_memcpy,
|
|
|
|
/* DAI drivers */
|
|
.drv = bdw_dai,
|
|
.num_drv = ARRAY_SIZE(bdw_dai),
|
|
|
|
/* ALSA HW info flags */
|
|
.hw_info = SNDRV_PCM_INFO_MMAP |
|
|
SNDRV_PCM_INFO_MMAP_VALID |
|
|
SNDRV_PCM_INFO_INTERLEAVED |
|
|
SNDRV_PCM_INFO_PAUSE |
|
|
SNDRV_PCM_INFO_BATCH,
|
|
|
|
.dsp_arch_ops = &sof_xtensa_arch_ops,
|
|
};
|
|
|
|
static const struct sof_intel_dsp_desc bdw_chip_info = {
|
|
.cores_num = 1,
|
|
.host_managed_cores_mask = 1,
|
|
.hw_ip_version = SOF_INTEL_BROADWELL,
|
|
};
|
|
|
|
static const struct sof_dev_desc sof_acpi_broadwell_desc = {
|
|
.machines = snd_soc_acpi_intel_broadwell_machines,
|
|
.resindex_lpe_base = 0,
|
|
.resindex_pcicfg_base = 1,
|
|
.resindex_imr_base = -1,
|
|
.irqindex_host_ipc = 0,
|
|
.chip_info = &bdw_chip_info,
|
|
.ipc_supported_mask = BIT(SOF_IPC),
|
|
.ipc_default = SOF_IPC,
|
|
.default_fw_path = {
|
|
[SOF_IPC] = "intel/sof",
|
|
},
|
|
.default_tplg_path = {
|
|
[SOF_IPC] = "intel/sof-tplg",
|
|
},
|
|
.default_fw_filename = {
|
|
[SOF_IPC] = "sof-bdw.ri",
|
|
},
|
|
.nocodec_tplg_filename = "sof-bdw-nocodec.tplg",
|
|
.ops = &sof_bdw_ops,
|
|
};
|
|
|
|
static const struct acpi_device_id sof_broadwell_match[] = {
|
|
{ "INT3438", (unsigned long)&sof_acpi_broadwell_desc },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, sof_broadwell_match);
|
|
|
|
static int sof_broadwell_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
const struct acpi_device_id *id;
|
|
const struct sof_dev_desc *desc;
|
|
int ret;
|
|
|
|
id = acpi_match_device(dev->driver->acpi_match_table, dev);
|
|
if (!id)
|
|
return -ENODEV;
|
|
|
|
ret = snd_intel_acpi_dsp_driver_probe(dev, id->id);
|
|
if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) {
|
|
dev_dbg(dev, "SOF ACPI driver not selected, aborting probe\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
desc = (const struct sof_dev_desc *)id->driver_data;
|
|
return sof_acpi_probe(pdev, desc);
|
|
}
|
|
|
|
/* acpi_driver definition */
|
|
static struct platform_driver snd_sof_acpi_intel_bdw_driver = {
|
|
.probe = sof_broadwell_probe,
|
|
.remove = sof_acpi_remove,
|
|
.driver = {
|
|
.name = "sof-audio-acpi-intel-bdw",
|
|
.pm = &sof_acpi_pm,
|
|
.acpi_match_table = sof_broadwell_match,
|
|
},
|
|
};
|
|
module_platform_driver(snd_sof_acpi_intel_bdw_driver);
|
|
|
|
MODULE_LICENSE("Dual BSD/GPL");
|
|
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
|
|
MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
|
|
MODULE_IMPORT_NS(SND_SOC_SOF_ACPI_DEV);
|