2009 lines
76 KiB
C
2009 lines
76 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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* aw882xx_pid_2032_reg.h
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*
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* Copyright (c) 2020 AWINIC Technology CO., LTD
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*
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* Author: Nick Li <liweilei@awinic.com.cn>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __AW882XX_PID_2032_REG_H__
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#define __AW882XX_PID_2032_REG_H__
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#define AW_PID_2032_MONITOR_FILE "aw882xx_pid_2032_monitor.bin"
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/* registers list */
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#define AW_PID_2032_ID_REG (0x00)
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#define AW_PID_2032_SYSST_REG (0x01)
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#define AW_PID_2032_SYSINT_REG (0x02)
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#define AW_PID_2032_SYSINTM_REG (0x03)
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#define AW_PID_2032_SYSCTRL_REG (0x04)
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#define AW_PID_2032_SYSCTRL2_REG (0x05)
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#define AW_PID_2032_I2SCTRL_REG (0x06)
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#define AW_PID_2032_I2SCFG1_REG (0x07)
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#define AW_PID_2032_I2SCFG2_REG (0x08)
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#define AW_PID_2032_HAGCCFG1_REG (0x09)
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#define AW_PID_2032_HAGCCFG2_REG (0x0A)
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#define AW_PID_2032_HAGCCFG3_REG (0x0B)
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#define AW_PID_2032_HAGCCFG4_REG (0x0C)
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#define AW_PID_2032_HAGCCFG5_REG (0x0D)
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#define AW_PID_2032_HAGCCFG6_REG (0x0E)
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#define AW_PID_2032_HAGCCFG7_REG (0x0F)
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#define AW_PID_2032_HAGCST_REG (0x10)
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#define AW_PID_2032_PRODID_REG (0x11)
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#define AW_PID_2032_VBAT_REG (0x12)
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#define AW_PID_2032_TEMP_REG (0x13)
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#define AW_PID_2032_PVDD_REG (0x14)
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#define AW_PID_2032_HAGCCFG8_REG (0x15)
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#define AW_PID_2032_DBGCTRL_REG (0x20)
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#define AW_PID_2032_I2SINT_REG (0x21)
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#define AW_PID_2032_I2SCAPCNT_REG (0x22)
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#define AW_PID_2032_ANASTA1_REG (0x23)
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#define AW_PID_2032_ANASTA2_REG (0x24)
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#define AW_PID_2032_ANASTA3_REG (0x25)
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#define AW_PID_2032_ANASTA4_REG (0x26)
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#define AW_PID_2032_DSMCFG1_REG (0x30)
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#define AW_PID_2032_DSMCFG2_REG (0x31)
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#define AW_PID_2032_DSMCFG3_REG (0x32)
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#define AW_PID_2032_DSMCFG4_REG (0x33)
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#define AW_PID_2032_DSMCFG5_REG (0x34)
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#define AW_PID_2032_DSMCFG6_REG (0x35)
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#define AW_PID_2032_DSMCFG7_REG (0x36)
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#define AW_PID_2032_DSMCFG8_REG (0x37)
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#define AW_PID_2032_TESTIN_REG (0x38)
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#define AW_PID_2032_TESTOUT_REG (0x39)
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#define AW_PID_2032_VSNCTRL1_REG (0x50)
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#define AW_PID_2032_ISNCTRL1_REG (0x52)
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#define AW_PID_2032_ISNCTRL2_REG (0x53)
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#define AW_PID_2032_VTMCTRL1_REG (0x54)
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#define AW_PID_2032_VTMCTRL2_REG (0x55)
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#define AW_PID_2032_VTMCTRL3_REG (0x56)
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#define AW_PID_2032_ISNDAT_REG (0x57)
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#define AW_PID_2032_VSNDAT_REG (0x58)
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#define AW_PID_2032_PWMCTRL_REG (0x59)
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#define AW_PID_2032_PWMCTRL2_REG (0x5A)
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#define AW_PID_2032_BSTCTRL1_REG (0x60)
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#define AW_PID_2032_BSTCTRL2_REG (0x61)
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#define AW_PID_2032_BSTCTRL3_REG (0x62)
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#define AW_PID_2032_BSTDBG1_REG (0x63)
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#define AW_PID_2032_BSTDBG2_REG (0x64)
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#define AW_PID_2032_BSTDBG3_REG (0x65)
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#define AW_PID_2032_PLLCTRL1_REG (0x66)
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#define AW_PID_2032_PLLCTRL2_REG (0x67)
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#define AW_PID_2032_PLLCTRL3_REG (0x68)
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#define AW_PID_2032_CDACTRL1_REG (0x69)
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#define AW_PID_2032_CDACTRL2_REG (0x6A)
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#define AW_PID_2032_SADCCTRL_REG (0x6B)
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#define AW_PID_2032_BSTCTRL8_REG (0x6C)
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#define AW_PID_2032_TESTCTRL1_REG (0x70)
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#define AW_PID_2032_TESTCTRL2_REG (0x71)
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#define AW_PID_2032_EFCTRL1_REG (0x72)
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#define AW_PID_2032_EFCTRL2_REG (0x73)
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#define AW_PID_2032_EFWH_REG (0x74)
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#define AW_PID_2032_EFWM2_REG (0x75)
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#define AW_PID_2032_EFWM1_REG (0x76)
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#define AW_PID_2032_EFWL_REG (0x77)
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#define AW_PID_2032_EFRH_REG (0x78)
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#define AW_PID_2032_EFRM2_REG (0x79)
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#define AW_PID_2032_EFRM1_REG (0x7A)
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#define AW_PID_2032_EFRL_REG (0x7B)
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#define AW_PID_2032_TESTDET_REG (0x7C)
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#define AW_PID_2032_TM_REG (0x7D)
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/********************************************
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* Register Access
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*******************************************/
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#define AW_PID_2032_REG_MAX (0x7E)
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#define AW_PID_2032_REG_NONE_ACCESS (0)
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#define AW_PID_2032_REG_RD_ACCESS (1 << 0)
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#define AW_PID_2032_REG_WR_ACCESS (1 << 1)
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const unsigned char aw_pid_2032_reg_access[AW_PID_2032_REG_MAX] = {
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[AW_PID_2032_ID_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_SYSST_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_SYSINT_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_SYSINTM_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_SYSCTRL_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_SYSCTRL2_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_I2SCTRL_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_I2SCFG1_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_I2SCFG2_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_HAGCCFG1_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_HAGCCFG2_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_HAGCCFG3_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_HAGCCFG4_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_HAGCCFG5_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_HAGCCFG6_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_HAGCCFG7_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_HAGCST_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_PRODID_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_VBAT_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_TEMP_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_PVDD_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_HAGCCFG8_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_DBGCTRL_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_I2SINT_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_I2SCAPCNT_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_ANASTA1_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_ANASTA2_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_ANASTA3_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_ANASTA4_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_DSMCFG1_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_DSMCFG2_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_DSMCFG3_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_DSMCFG4_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_DSMCFG5_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_DSMCFG6_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_DSMCFG7_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_DSMCFG8_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_TESTIN_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_TESTOUT_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_VSNCTRL1_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_ISNCTRL1_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_ISNCTRL2_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_VTMCTRL1_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_VTMCTRL2_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_VTMCTRL3_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_ISNDAT_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_VSNDAT_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_PWMCTRL_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_PWMCTRL2_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_BSTCTRL1_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_BSTCTRL2_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_BSTCTRL3_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_BSTDBG1_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_BSTDBG2_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_BSTDBG3_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_PLLCTRL1_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_PLLCTRL2_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_PLLCTRL3_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_CDACTRL1_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_CDACTRL2_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_SADCCTRL_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_BSTCTRL8_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_TESTCTRL1_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_TESTCTRL2_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_EFCTRL1_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_EFCTRL2_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_EFWH_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_EFWM2_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_EFWM1_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_EFWL_REG] = (AW_PID_2032_REG_RD_ACCESS | AW_PID_2032_REG_WR_ACCESS),
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[AW_PID_2032_EFRH_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_EFRM2_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_EFRM1_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_EFRL_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_TESTDET_REG] = (AW_PID_2032_REG_RD_ACCESS),
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[AW_PID_2032_TM_REG] = (AW_PID_2032_REG_NONE_ACCESS),
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};
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/* detail information of registers begin */
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/* ID (0x00) detail */
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/* IDCODE bit 15:0 (ID 0x00) */
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#define AW_PID_2032_IDCODE_START_BIT (0)
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#define AW_PID_2032_IDCODE_BITS_LEN (16)
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#define AW_PID_2032_IDCODE_MASK \
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(~(((1<<AW_PID_2032_IDCODE_BITS_LEN)-1) << AW_PID_2032_IDCODE_START_BIT))
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#define AW_PID_2032_IDCODE_DEFAULT_VALUE (0x2032)
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#define AW_PID_2032_IDCODE_DEFAULT \
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(AW_PID_2032_IDCODE_DEFAULT_VALUE << AW_PID_2032_IDCODE_START_BIT)
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/* default value of ID (0x00) */
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/* #define AW_PID_2032_ID_DEFAULT (0x2032) */
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/* SYSST (0x01) detail */
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/* OVP2S bit 15 (SYSST 0x01) */
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#define AW_PID_2032_OVP2S_START_BIT (15)
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#define AW_PID_2032_OVP2S_BITS_LEN (1)
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#define AW_PID_2032_OVP2S_MASK \
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(~(((1<<AW_PID_2032_OVP2S_BITS_LEN)-1) << AW_PID_2032_OVP2S_START_BIT))
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#define AW_PID_2032_OVP2S_NORMAL (0)
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#define AW_PID_2032_OVP2S_NORMAL_VALUE \
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(AW_PID_2032_OVP2S_NORMAL << AW_PID_2032_OVP2S_START_BIT)
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#define AW_PID_2032_OVP2S_OVP (1)
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#define AW_PID_2032_OVP2S_OVP_VALUE \
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(AW_PID_2032_OVP2S_OVP << AW_PID_2032_OVP2S_START_BIT)
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#define AW_PID_2032_OVP2S_DEFAULT_VALUE (0)
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#define AW_PID_2032_OVP2S_DEFAULT \
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(AW_PID_2032_OVP2S_DEFAULT_VALUE << AW_PID_2032_OVP2S_START_BIT)
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/* UVLS bit 14 (SYSST 0x01) */
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#define AW_PID_2032_UVLS_START_BIT (14)
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#define AW_PID_2032_UVLS_BITS_LEN (1)
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#define AW_PID_2032_UVLS_MASK \
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(~(((1<<AW_PID_2032_UVLS_BITS_LEN)-1) << AW_PID_2032_UVLS_START_BIT))
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#define AW_PID_2032_UVLS_VDD_ABOVE_2P8V (0)
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#define AW_PID_2032_UVLS_VDD_ABOVE_2P8V_VALUE \
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(AW_PID_2032_UVLS_VDD_ABOVE_2P8V << AW_PID_2032_UVLS_START_BIT)
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#define AW_PID_2032_UVLS_VDD_BELOW_2P8V (1)
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#define AW_PID_2032_UVLS_VDD_BELOW_2P8V_VALUE \
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(AW_PID_2032_UVLS_VDD_BELOW_2P8V << AW_PID_2032_UVLS_START_BIT)
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#define AW_PID_2032_UVLS_DEFAULT_VALUE (0)
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#define AW_PID_2032_UVLS_DEFAULT \
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(AW_PID_2032_UVLS_DEFAULT_VALUE << AW_PID_2032_UVLS_START_BIT)
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/* ADPS bit 13 (SYSST 0x01) */
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#define AW_PID_2032_ADPS_START_BIT (13)
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#define AW_PID_2032_ADPS_BITS_LEN (1)
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#define AW_PID_2032_ADPS_MASK \
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(~(((1<<AW_PID_2032_ADPS_BITS_LEN)-1) << AW_PID_2032_ADPS_START_BIT))
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#define AW_PID_2032_ADPS_TRANSPARENT (0)
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#define AW_PID_2032_ADPS_TRANSPARENT_VALUE \
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(AW_PID_2032_ADPS_TRANSPARENT << AW_PID_2032_ADPS_START_BIT)
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#define AW_PID_2032_ADPS_BOOST (1)
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#define AW_PID_2032_ADPS_BOOST_VALUE \
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(AW_PID_2032_ADPS_BOOST << AW_PID_2032_ADPS_START_BIT)
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#define AW_PID_2032_ADPS_DEFAULT_VALUE (0)
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#define AW_PID_2032_ADPS_DEFAULT \
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(AW_PID_2032_ADPS_DEFAULT_VALUE << AW_PID_2032_ADPS_START_BIT)
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/* BSTOCS bit 11 (SYSST 0x01) */
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#define AW_PID_2032_BSTOCS_START_BIT (11)
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#define AW_PID_2032_BSTOCS_BITS_LEN (1)
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#define AW_PID_2032_BSTOCS_MASK \
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(~(((1<<AW_PID_2032_BSTOCS_BITS_LEN)-1) << AW_PID_2032_BSTOCS_START_BIT))
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#define AW_PID_2032_BSTOCS_NORMAL (0)
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#define AW_PID_2032_BSTOCS_NORMAL_VALUE \
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(AW_PID_2032_BSTOCS_NORMAL << AW_PID_2032_BSTOCS_START_BIT)
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#define AW_PID_2032_BSTOCS_OVER_CURRENT (1)
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#define AW_PID_2032_BSTOCS_OVER_CURRENT_VALUE \
|
|
(AW_PID_2032_BSTOCS_OVER_CURRENT << AW_PID_2032_BSTOCS_START_BIT)
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|
|
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#define AW_PID_2032_BSTOCS_DEFAULT_VALUE (0)
|
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#define AW_PID_2032_BSTOCS_DEFAULT \
|
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(AW_PID_2032_BSTOCS_DEFAULT_VALUE << AW_PID_2032_BSTOCS_START_BIT)
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|
|
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/* OVPS bit 10 (SYSST 0x01) */
|
|
#define AW_PID_2032_OVPS_START_BIT (10)
|
|
#define AW_PID_2032_OVPS_BITS_LEN (1)
|
|
#define AW_PID_2032_OVPS_MASK \
|
|
(~(((1<<AW_PID_2032_OVPS_BITS_LEN)-1) << AW_PID_2032_OVPS_START_BIT))
|
|
|
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#define AW_PID_2032_OVPS_NORMAL (0)
|
|
#define AW_PID_2032_OVPS_NORMAL_VALUE \
|
|
(AW_PID_2032_OVPS_NORMAL << AW_PID_2032_OVPS_START_BIT)
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|
|
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#define AW_PID_2032_OVPS_OVP (1)
|
|
#define AW_PID_2032_OVPS_OVP_VALUE \
|
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(AW_PID_2032_OVPS_OVP << AW_PID_2032_OVPS_START_BIT)
|
|
|
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#define AW_PID_2032_OVPS_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_OVPS_DEFAULT \
|
|
(AW_PID_2032_OVPS_DEFAULT_VALUE << AW_PID_2032_OVPS_START_BIT)
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|
|
|
/* BSTS bit 9 (SYSST 0x01) */
|
|
#define AW_PID_2032_BSTS_START_BIT (9)
|
|
#define AW_PID_2032_BSTS_BITS_LEN (1)
|
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#define AW_PID_2032_BSTS_MASK \
|
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(~(((1<<AW_PID_2032_BSTS_BITS_LEN)-1) << AW_PID_2032_BSTS_START_BIT))
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|
|
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#define AW_PID_2032_BSTS_NOT_FINISHED (0)
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#define AW_PID_2032_BSTS_NOT_FINISHED_VALUE \
|
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(AW_PID_2032_BSTS_NOT_FINISHED << AW_PID_2032_BSTS_START_BIT)
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|
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#define AW_PID_2032_BSTS_FINISHED (1)
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#define AW_PID_2032_BSTS_FINISHED_VALUE \
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(AW_PID_2032_BSTS_FINISHED << AW_PID_2032_BSTS_START_BIT)
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|
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#define AW_PID_2032_BSTS_DEFAULT_VALUE (0)
|
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#define AW_PID_2032_BSTS_DEFAULT \
|
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(AW_PID_2032_BSTS_DEFAULT_VALUE << AW_PID_2032_BSTS_START_BIT)
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|
|
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/* SWS bit 8 (SYSST 0x01) */
|
|
#define AW_PID_2032_SWS_START_BIT (8)
|
|
#define AW_PID_2032_SWS_BITS_LEN (1)
|
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#define AW_PID_2032_SWS_MASK \
|
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(~(((1<<AW_PID_2032_SWS_BITS_LEN)-1) << AW_PID_2032_SWS_START_BIT))
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|
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#define AW_PID_2032_SWS_NOT_SWITCHING (0)
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#define AW_PID_2032_SWS_NOT_SWITCHING_VALUE \
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(AW_PID_2032_SWS_NOT_SWITCHING << AW_PID_2032_SWS_START_BIT)
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|
|
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#define AW_PID_2032_SWS_SWITCHING (1)
|
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#define AW_PID_2032_SWS_SWITCHING_VALUE \
|
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(AW_PID_2032_SWS_SWITCHING << AW_PID_2032_SWS_START_BIT)
|
|
|
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#define AW_PID_2032_SWS_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_SWS_DEFAULT \
|
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(AW_PID_2032_SWS_DEFAULT_VALUE << AW_PID_2032_SWS_START_BIT)
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|
|
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/* CLIPS bit 7 (SYSST 0x01) */
|
|
#define AW_PID_2032_CLIPS_START_BIT (7)
|
|
#define AW_PID_2032_CLIPS_BITS_LEN (1)
|
|
#define AW_PID_2032_CLIPS_MASK \
|
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(~(((1<<AW_PID_2032_CLIPS_BITS_LEN)-1) << AW_PID_2032_CLIPS_START_BIT))
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|
|
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#define AW_PID_2032_CLIPS_NOT_CLIPPING (0)
|
|
#define AW_PID_2032_CLIPS_NOT_CLIPPING_VALUE \
|
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(AW_PID_2032_CLIPS_NOT_CLIPPING << AW_PID_2032_CLIPS_START_BIT)
|
|
|
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#define AW_PID_2032_CLIPS_CLIPPING (1)
|
|
#define AW_PID_2032_CLIPS_CLIPPING_VALUE \
|
|
(AW_PID_2032_CLIPS_CLIPPING << AW_PID_2032_CLIPS_START_BIT)
|
|
|
|
#define AW_PID_2032_CLIPS_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_CLIPS_DEFAULT \
|
|
(AW_PID_2032_CLIPS_DEFAULT_VALUE << AW_PID_2032_CLIPS_START_BIT)
|
|
|
|
/* NOCLKS bit 5 (SYSST 0x01) */
|
|
#define AW_PID_2032_NOCLKS_START_BIT (5)
|
|
#define AW_PID_2032_NOCLKS_BITS_LEN (1)
|
|
#define AW_PID_2032_NOCLKS_MASK \
|
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(~(((1<<AW_PID_2032_NOCLKS_BITS_LEN)-1) << AW_PID_2032_NOCLKS_START_BIT))
|
|
|
|
#define AW_PID_2032_NOCLKS_CLOCK_OK (0)
|
|
#define AW_PID_2032_NOCLKS_CLOCK_OK_VALUE \
|
|
(AW_PID_2032_NOCLKS_CLOCK_OK << AW_PID_2032_NOCLKS_START_BIT)
|
|
|
|
#define AW_PID_2032_NOCLKS_NO_CLOCK (1)
|
|
#define AW_PID_2032_NOCLKS_NO_CLOCK_VALUE \
|
|
(AW_PID_2032_NOCLKS_NO_CLOCK << AW_PID_2032_NOCLKS_START_BIT)
|
|
|
|
#define AW_PID_2032_NOCLKS_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_NOCLKS_DEFAULT \
|
|
(AW_PID_2032_NOCLKS_DEFAULT_VALUE << AW_PID_2032_NOCLKS_START_BIT)
|
|
|
|
/* CLKS bit 4 (SYSST 0x01) */
|
|
#define AW_PID_2032_CLKS_START_BIT (4)
|
|
#define AW_PID_2032_CLKS_BITS_LEN (1)
|
|
#define AW_PID_2032_CLKS_MASK \
|
|
(~(((1<<AW_PID_2032_CLKS_BITS_LEN)-1) << AW_PID_2032_CLKS_START_BIT))
|
|
|
|
#define AW_PID_2032_CLKS_NOT_STABLE (0)
|
|
#define AW_PID_2032_CLKS_NOT_STABLE_VALUE \
|
|
(AW_PID_2032_CLKS_NOT_STABLE << AW_PID_2032_CLKS_START_BIT)
|
|
|
|
#define AW_PID_2032_CLKS_STABLE (1)
|
|
#define AW_PID_2032_CLKS_STABLE_VALUE \
|
|
(AW_PID_2032_CLKS_STABLE << AW_PID_2032_CLKS_START_BIT)
|
|
|
|
#define AW_PID_2032_CLKS_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_CLKS_DEFAULT \
|
|
(AW_PID_2032_CLKS_DEFAULT_VALUE << AW_PID_2032_CLKS_START_BIT)
|
|
|
|
/* OCDS bit 3 (SYSST 0x01) */
|
|
#define AW_PID_2032_OCDS_START_BIT (3)
|
|
#define AW_PID_2032_OCDS_BITS_LEN (1)
|
|
#define AW_PID_2032_OCDS_MASK \
|
|
(~(((1<<AW_PID_2032_OCDS_BITS_LEN)-1) << AW_PID_2032_OCDS_START_BIT))
|
|
|
|
#define AW_PID_2032_OCDS_NORAML (0)
|
|
#define AW_PID_2032_OCDS_NORAML_VALUE \
|
|
(AW_PID_2032_OCDS_NORAML << AW_PID_2032_OCDS_START_BIT)
|
|
|
|
#define AW_PID_2032_OCDS_OC (1)
|
|
#define AW_PID_2032_OCDS_OC_VALUE \
|
|
(AW_PID_2032_OCDS_OC << AW_PID_2032_OCDS_START_BIT)
|
|
|
|
#define AW_PID_2032_OCDS_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_OCDS_DEFAULT \
|
|
(AW_PID_2032_OCDS_DEFAULT_VALUE << AW_PID_2032_OCDS_START_BIT)
|
|
|
|
/* CLIP_PRES bit 2 (SYSST 0x01) */
|
|
#define AW_PID_2032_CLIP_PRES_START_BIT (2)
|
|
#define AW_PID_2032_CLIP_PRES_BITS_LEN (1)
|
|
#define AW_PID_2032_CLIP_PRES_MASK \
|
|
(~(((1<<AW_PID_2032_CLIP_PRES_BITS_LEN)-1) << AW_PID_2032_CLIP_PRES_START_BIT))
|
|
|
|
#define AW_PID_2032_CLIP_PRES_NOT_CLIPPING (0)
|
|
#define AW_PID_2032_CLIP_PRES_NOT_CLIPPING_VALUE \
|
|
(AW_PID_2032_CLIP_PRES_NOT_CLIPPING << AW_PID_2032_CLIP_PRES_START_BIT)
|
|
|
|
#define AW_PID_2032_CLIP_PRES_CLIPPING (1)
|
|
#define AW_PID_2032_CLIP_PRES_CLIPPING_VALUE \
|
|
(AW_PID_2032_CLIP_PRES_CLIPPING << AW_PID_2032_CLIP_PRES_START_BIT)
|
|
|
|
#define AW_PID_2032_CLIP_PRES_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_CLIP_PRES_DEFAULT \
|
|
(AW_PID_2032_CLIP_PRES_DEFAULT_VALUE << AW_PID_2032_CLIP_PRES_START_BIT)
|
|
|
|
/* OTHS bit 1 (SYSST 0x01) */
|
|
#define AW_PID_2032_OTHS_START_BIT (1)
|
|
#define AW_PID_2032_OTHS_BITS_LEN (1)
|
|
#define AW_PID_2032_OTHS_MASK \
|
|
(~(((1<<AW_PID_2032_OTHS_BITS_LEN)-1) << AW_PID_2032_OTHS_START_BIT))
|
|
|
|
#define AW_PID_2032_OTHS_NORMAL (0)
|
|
#define AW_PID_2032_OTHS_NORMAL_VALUE \
|
|
(AW_PID_2032_OTHS_NORMAL << AW_PID_2032_OTHS_START_BIT)
|
|
|
|
#define AW_PID_2032_OTHS_OT (1)
|
|
#define AW_PID_2032_OTHS_OT_VALUE \
|
|
(AW_PID_2032_OTHS_OT << AW_PID_2032_OTHS_START_BIT)
|
|
|
|
#define AW_PID_2032_OTHS_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_OTHS_DEFAULT \
|
|
(AW_PID_2032_OTHS_DEFAULT_VALUE << AW_PID_2032_OTHS_START_BIT)
|
|
|
|
/* PLLS bit 0 (SYSST 0x01) */
|
|
#define AW_PID_2032_PLLS_START_BIT (0)
|
|
#define AW_PID_2032_PLLS_BITS_LEN (1)
|
|
#define AW_PID_2032_PLLS_MASK \
|
|
(~(((1<<AW_PID_2032_PLLS_BITS_LEN)-1) << AW_PID_2032_PLLS_START_BIT))
|
|
|
|
#define AW_PID_2032_PLLS_UNLOCKED (0)
|
|
#define AW_PID_2032_PLLS_UNLOCKED_VALUE \
|
|
(AW_PID_2032_PLLS_UNLOCKED << AW_PID_2032_PLLS_START_BIT)
|
|
|
|
#define AW_PID_2032_PLLS_LOCKED (1)
|
|
#define AW_PID_2032_PLLS_LOCKED_VALUE \
|
|
(AW_PID_2032_PLLS_LOCKED << AW_PID_2032_PLLS_START_BIT)
|
|
|
|
#define AW_PID_2032_PLLS_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_PLLS_DEFAULT \
|
|
(AW_PID_2032_PLLS_DEFAULT_VALUE << AW_PID_2032_PLLS_START_BIT)
|
|
|
|
|
|
#define AW_PID_2032_SYSST_CHECK_MASK \
|
|
(~(AW_PID_2032_UVLS_VDD_BELOW_2P8V_VALUE | \
|
|
AW_PID_2032_BSTOCS_OVER_CURRENT_VALUE | \
|
|
AW_PID_2032_BSTS_FINISHED_VALUE | \
|
|
AW_PID_2032_SWS_SWITCHING_VALUE | \
|
|
AW_PID_2032_NOCLKS_NO_CLOCK_VALUE | \
|
|
AW_PID_2032_CLKS_STABLE_VALUE | \
|
|
AW_PID_2032_OCDS_OC_VALUE | \
|
|
AW_PID_2032_OTHS_OT_VALUE | \
|
|
AW_PID_2032_PLLS_LOCKED_VALUE))
|
|
|
|
#define AW_PID_2032_SYSST_CHECK \
|
|
(AW_PID_2032_BSTS_FINISHED_VALUE | \
|
|
AW_PID_2032_SWS_SWITCHING_VALUE | \
|
|
AW_PID_2032_CLKS_STABLE_VALUE | \
|
|
AW_PID_2032_PLLS_LOCKED_VALUE)
|
|
|
|
#define AW882XX_IIS_CHECK_MASK \
|
|
(~(AW_PID_2032_UVLS_VDD_BELOW_2P8V_VALUE | \
|
|
AW_PID_2032_NOCLKS_NO_CLOCK_VALUE | \
|
|
AW_PID_2032_CLKS_STABLE_VALUE | \
|
|
AW_PID_2032_OCDS_OC_VALUE | \
|
|
AW_PID_2032_OTHS_OT_VALUE | \
|
|
AW_PID_2032_PLLS_LOCKED_VALUE))
|
|
|
|
#define AW_PID_2032_IIS_CHECK \
|
|
(AW_PID_2032_CLKS_STABLE_VALUE | \
|
|
AW_PID_2032_PLLS_LOCKED_VALUE)
|
|
|
|
/* default value of SYSST (0x01) */
|
|
/* #define AW_PID_2032_SYSST_DEFAULT (0x0000) */
|
|
|
|
/* SYSINT (0x02) detail */
|
|
/* OVP2I bit 15 (SYSINT 0x02) */
|
|
#define AW_PID_2032_OVP2I_START_BIT (15)
|
|
#define AW_PID_2032_OVP2I_BITS_LEN (1)
|
|
#define AW_PID_2032_OVP2I_MASK \
|
|
(~(((1<<AW_PID_2032_OVP2I_BITS_LEN)-1) << AW_PID_2032_OVP2I_START_BIT))
|
|
|
|
#define AW_PID_2032_OVP2I_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_OVP2I_DEFAULT \
|
|
(AW_PID_2032_OVP2I_DEFAULT_VALUE << AW_PID_2032_OVP2I_START_BIT)
|
|
|
|
/* UVLI bit 14 (SYSINT 0x02) */
|
|
#define AW_PID_2032_UVLI_START_BIT (14)
|
|
#define AW_PID_2032_UVLI_BITS_LEN (1)
|
|
#define AW_PID_2032_UVLI_MASK \
|
|
(~(((1<<AW_PID_2032_UVLI_BITS_LEN)-1) << AW_PID_2032_UVLI_START_BIT))
|
|
|
|
#define AW_PID_2032_UVLI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_UVLI_DEFAULT \
|
|
(AW_PID_2032_UVLI_DEFAULT_VALUE << AW_PID_2032_UVLI_START_BIT)
|
|
|
|
/* ADPI bit 13 (SYSINT 0x02) */
|
|
#define AW_PID_2032_ADPI_START_BIT (13)
|
|
#define AW_PID_2032_ADPI_BITS_LEN (1)
|
|
#define AW_PID_2032_ADPI_MASK \
|
|
(~(((1<<AW_PID_2032_ADPI_BITS_LEN)-1) << AW_PID_2032_ADPI_START_BIT))
|
|
|
|
#define AW_PID_2032_ADPI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_ADPI_DEFAULT \
|
|
(AW_PID_2032_ADPI_DEFAULT_VALUE << AW_PID_2032_ADPI_START_BIT)
|
|
|
|
/* BSTOCI bit 11 (SYSINT 0x02) */
|
|
#define AW_PID_2032_BSTOCI_START_BIT (11)
|
|
#define AW_PID_2032_BSTOCI_BITS_LEN (1)
|
|
#define AW_PID_2032_BSTOCI_MASK \
|
|
(~(((1<<AW_PID_2032_BSTOCI_BITS_LEN)-1) << AW_PID_2032_BSTOCI_START_BIT))
|
|
|
|
#define AW_PID_2032_BSTOCI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_BSTOCI_DEFAULT \
|
|
(AW_PID_2032_BSTOCI_DEFAULT_VALUE << AW_PID_2032_BSTOCI_START_BIT)
|
|
|
|
/* OVPI bit 10 (SYSINT 0x02) */
|
|
#define AW_PID_2032_OVPI_START_BIT (10)
|
|
#define AW_PID_2032_OVPI_BITS_LEN (1)
|
|
#define AW_PID_2032_OVPI_MASK \
|
|
(~(((1<<AW_PID_2032_OVPI_BITS_LEN)-1) << AW_PID_2032_OVPI_START_BIT))
|
|
|
|
#define AW_PID_2032_OVPI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_OVPI_DEFAULT \
|
|
(AW_PID_2032_OVPI_DEFAULT_VALUE << AW_PID_2032_OVPI_START_BIT)
|
|
|
|
/* BSTI bit 9 (SYSINT 0x02) */
|
|
#define AW_PID_2032_BSTI_START_BIT (9)
|
|
#define AW_PID_2032_BSTI_BITS_LEN (1)
|
|
#define AW_PID_2032_BSTI_MASK \
|
|
(~(((1<<AW_PID_2032_BSTI_BITS_LEN)-1) << AW_PID_2032_BSTI_START_BIT))
|
|
|
|
#define AW_PID_2032_BSTI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_BSTI_DEFAULT \
|
|
(AW_PID_2032_BSTI_DEFAULT_VALUE << AW_PID_2032_BSTI_START_BIT)
|
|
|
|
/* SWI bit 8 (SYSINT 0x02) */
|
|
#define AW_PID_2032_SWI_START_BIT (8)
|
|
#define AW_PID_2032_SWI_BITS_LEN (1)
|
|
#define AW_PID_2032_SWI_MASK \
|
|
(~(((1<<AW_PID_2032_SWI_BITS_LEN)-1) << AW_PID_2032_SWI_START_BIT))
|
|
|
|
#define AW_PID_2032_SWI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_SWI_DEFAULT \
|
|
(AW_PID_2032_SWI_DEFAULT_VALUE << AW_PID_2032_SWI_START_BIT)
|
|
|
|
/* CLIPI bit 7 (SYSINT 0x02) */
|
|
#define AW_PID_2032_CLIPI_START_BIT (7)
|
|
#define AW_PID_2032_CLIPI_BITS_LEN (1)
|
|
#define AW_PID_2032_CLIPI_MASK \
|
|
(~(((1<<AW_PID_2032_CLIPI_BITS_LEN)-1) << AW_PID_2032_CLIPI_START_BIT))
|
|
|
|
#define AW_PID_2032_CLIPI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_CLIPI_DEFAULT \
|
|
(AW_PID_2032_CLIPI_DEFAULT_VALUE << AW_PID_2032_CLIPI_START_BIT)
|
|
|
|
/* NOCLKI bit 5 (SYSINT 0x02) */
|
|
#define AW_PID_2032_NOCLKI_START_BIT (5)
|
|
#define AW_PID_2032_NOCLKI_BITS_LEN (1)
|
|
#define AW_PID_2032_NOCLKI_MASK \
|
|
(~(((1<<AW_PID_2032_NOCLKI_BITS_LEN)-1) << AW_PID_2032_NOCLKI_START_BIT))
|
|
|
|
#define AW_PID_2032_NOCLKI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_NOCLKI_DEFAULT \
|
|
(AW_PID_2032_NOCLKI_DEFAULT_VALUE << AW_PID_2032_NOCLKI_START_BIT)
|
|
|
|
/* CLKI bit 4 (SYSINT 0x02) */
|
|
#define AW_PID_2032_CLKI_START_BIT (4)
|
|
#define AW_PID_2032_CLKI_BITS_LEN (1)
|
|
#define AW_PID_2032_CLKI_MASK \
|
|
(~(((1<<AW_PID_2032_CLKI_BITS_LEN)-1) << AW_PID_2032_CLKI_START_BIT))
|
|
|
|
#define AW_PID_2032_CLKI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_CLKI_DEFAULT \
|
|
(AW_PID_2032_CLKI_DEFAULT_VALUE << AW_PID_2032_CLKI_START_BIT)
|
|
|
|
/* OCDI bit 3 (SYSINT 0x02) */
|
|
#define AW_PID_2032_OCDI_START_BIT (3)
|
|
#define AW_PID_2032_OCDI_BITS_LEN (1)
|
|
#define AW_PID_2032_OCDI_MASK \
|
|
(~(((1<<AW_PID_2032_OCDI_BITS_LEN)-1) << AW_PID_2032_OCDI_START_BIT))
|
|
|
|
#define AW_PID_2032_OCDI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_OCDI_DEFAULT \
|
|
(AW_PID_2032_OCDI_DEFAULT_VALUE << AW_PID_2032_OCDI_START_BIT)
|
|
|
|
/* CLIP_PREI bit 2 (SYSINT 0x02) */
|
|
#define AW_PID_2032_CLIP_PREI_START_BIT (2)
|
|
#define AW_PID_2032_CLIP_PREI_BITS_LEN (1)
|
|
#define AW_PID_2032_CLIP_PREI_MASK \
|
|
(~(((1<<AW_PID_2032_CLIP_PREI_BITS_LEN)-1) << AW_PID_2032_CLIP_PREI_START_BIT))
|
|
|
|
#define AW_PID_2032_CLIP_PREI_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_CLIP_PREI_DEFAULT \
|
|
(AW_PID_2032_CLIP_PREI_DEFAULT_VALUE << AW_PID_2032_CLIP_PREI_START_BIT)
|
|
|
|
/* OTHI bit 1 (SYSINT 0x02) */
|
|
#define AW_PID_2032_OTHI_START_BIT (1)
|
|
#define AW_PID_2032_OTHI_BITS_LEN (1)
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#define AW_PID_2032_OTHI_MASK \
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(~(((1<<AW_PID_2032_OTHI_BITS_LEN)-1) << AW_PID_2032_OTHI_START_BIT))
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#define AW_PID_2032_OTHI_DEFAULT_VALUE (0)
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#define AW_PID_2032_OTHI_DEFAULT \
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(AW_PID_2032_OTHI_DEFAULT_VALUE << AW_PID_2032_OTHI_START_BIT)
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|
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/* PLLI bit 0 (SYSINT 0x02) */
|
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#define AW_PID_2032_PLLI_START_BIT (0)
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#define AW_PID_2032_PLLI_BITS_LEN (1)
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#define AW_PID_2032_PLLI_MASK \
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(~(((1<<AW_PID_2032_PLLI_BITS_LEN)-1) << AW_PID_2032_PLLI_START_BIT))
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#define AW_PID_2032_PLLI_DEFAULT_VALUE (0)
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#define AW_PID_2032_PLLI_DEFAULT \
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(AW_PID_2032_PLLI_DEFAULT_VALUE << AW_PID_2032_PLLI_START_BIT)
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/* default value of SYSINT (0x02) */
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/* #define AW_PID_2032_SYSINT_DEFAULT (0x0000) */
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/* SYSINTM (0x03) detail */
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/* OVP2M bit 15 (SYSINTM 0x03) */
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#define AW_PID_2032_OVP2M_START_BIT (15)
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#define AW_PID_2032_OVP2M_BITS_LEN (1)
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#define AW_PID_2032_OVP2M_MASK \
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(~(((1<<AW_PID_2032_OVP2M_BITS_LEN)-1) << AW_PID_2032_OVP2M_START_BIT))
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#define AW_PID_2032_OVP2M_DEFAULT_VALUE (1)
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#define AW_PID_2032_OVP2M_DEFAULT \
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(AW_PID_2032_OVP2M_DEFAULT_VALUE << AW_PID_2032_OVP2M_START_BIT)
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/* UVLM bit 14 (SYSINTM 0x03) */
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#define AW_PID_2032_UVLM_START_BIT (14)
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#define AW_PID_2032_UVLM_BITS_LEN (1)
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#define AW_PID_2032_UVLM_MASK \
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(~(((1<<AW_PID_2032_UVLM_BITS_LEN)-1) << AW_PID_2032_UVLM_START_BIT))
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#define AW_PID_2032_UVLM_DEFAULT_VALUE (1)
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#define AW_PID_2032_UVLM_DEFAULT \
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(AW_PID_2032_UVLM_DEFAULT_VALUE << AW_PID_2032_UVLM_START_BIT)
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/* ADPM bit 13 (SYSINTM 0x03) */
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#define AW_PID_2032_ADPM_START_BIT (13)
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#define AW_PID_2032_ADPM_BITS_LEN (1)
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#define AW_PID_2032_ADPM_MASK \
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(~(((1<<AW_PID_2032_ADPM_BITS_LEN)-1) << AW_PID_2032_ADPM_START_BIT))
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#define AW_PID_2032_ADPM_DEFAULT_VALUE (1)
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#define AW_PID_2032_ADPM_DEFAULT \
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(AW_PID_2032_ADPM_DEFAULT_VALUE << AW_PID_2032_ADPM_START_BIT)
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/* BSTOCM bit 11 (SYSINTM 0x03) */
|
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#define AW_PID_2032_BSTOCM_START_BIT (11)
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#define AW_PID_2032_BSTOCM_BITS_LEN (1)
|
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#define AW_PID_2032_BSTOCM_MASK \
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(~(((1<<AW_PID_2032_BSTOCM_BITS_LEN)-1) << AW_PID_2032_BSTOCM_START_BIT))
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|
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#define AW_PID_2032_BSTOCM_DEFAULT_VALUE (1)
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#define AW_PID_2032_BSTOCM_DEFAULT \
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(AW_PID_2032_BSTOCM_DEFAULT_VALUE << AW_PID_2032_BSTOCM_START_BIT)
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|
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/* OVPM bit 10 (SYSINTM 0x03) */
|
|
#define AW_PID_2032_OVPM_START_BIT (10)
|
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#define AW_PID_2032_OVPM_BITS_LEN (1)
|
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#define AW_PID_2032_OVPM_MASK \
|
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(~(((1<<AW_PID_2032_OVPM_BITS_LEN)-1) << AW_PID_2032_OVPM_START_BIT))
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|
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#define AW_PID_2032_OVPM_DEFAULT_VALUE (1)
|
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#define AW_PID_2032_OVPM_DEFAULT \
|
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(AW_PID_2032_OVPM_DEFAULT_VALUE << AW_PID_2032_OVPM_START_BIT)
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|
|
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/* BSTM bit 9 (SYSINTM 0x03) */
|
|
#define AW_PID_2032_BSTM_START_BIT (9)
|
|
#define AW_PID_2032_BSTM_BITS_LEN (1)
|
|
#define AW_PID_2032_BSTM_MASK \
|
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(~(((1<<AW_PID_2032_BSTM_BITS_LEN)-1) << AW_PID_2032_BSTM_START_BIT))
|
|
|
|
#define AW_PID_2032_BSTM_DEFAULT_VALUE (1)
|
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#define AW_PID_2032_BSTM_DEFAULT \
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(AW_PID_2032_BSTM_DEFAULT_VALUE << AW_PID_2032_BSTM_START_BIT)
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|
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/* SWM bit 8 (SYSINTM 0x03) */
|
|
#define AW_PID_2032_SWM_START_BIT (8)
|
|
#define AW_PID_2032_SWM_BITS_LEN (1)
|
|
#define AW_PID_2032_SWM_MASK \
|
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(~(((1<<AW_PID_2032_SWM_BITS_LEN)-1) << AW_PID_2032_SWM_START_BIT))
|
|
|
|
#define AW_PID_2032_SWM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_SWM_DEFAULT \
|
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(AW_PID_2032_SWM_DEFAULT_VALUE << AW_PID_2032_SWM_START_BIT)
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|
|
|
/* CLIPM bit 7 (SYSINTM 0x03) */
|
|
#define AW_PID_2032_CLIPM_START_BIT (7)
|
|
#define AW_PID_2032_CLIPM_BITS_LEN (1)
|
|
#define AW_PID_2032_CLIPM_MASK \
|
|
(~(((1<<AW_PID_2032_CLIPM_BITS_LEN)-1) << AW_PID_2032_CLIPM_START_BIT))
|
|
|
|
#define AW_PID_2032_CLIPM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_CLIPM_DEFAULT \
|
|
(AW_PID_2032_CLIPM_DEFAULT_VALUE << AW_PID_2032_CLIPM_START_BIT)
|
|
|
|
/* NOCLKM bit 5 (SYSINTM 0x03) */
|
|
#define AW_PID_2032_NOCLKM_START_BIT (5)
|
|
#define AW_PID_2032_NOCLKM_BITS_LEN (1)
|
|
#define AW_PID_2032_NOCLKM_MASK \
|
|
(~(((1<<AW_PID_2032_NOCLKM_BITS_LEN)-1) << AW_PID_2032_NOCLKM_START_BIT))
|
|
|
|
#define AW_PID_2032_NOCLKM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_NOCLKM_DEFAULT \
|
|
(AW_PID_2032_NOCLKM_DEFAULT_VALUE << AW_PID_2032_NOCLKM_START_BIT)
|
|
|
|
/* CLKM bit 4 (SYSINTM 0x03) */
|
|
#define AW_PID_2032_CLKM_START_BIT (4)
|
|
#define AW_PID_2032_CLKM_BITS_LEN (1)
|
|
#define AW_PID_2032_CLKM_MASK \
|
|
(~(((1<<AW_PID_2032_CLKM_BITS_LEN)-1) << AW_PID_2032_CLKM_START_BIT))
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|
|
|
#define AW_PID_2032_CLKM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_CLKM_DEFAULT \
|
|
(AW_PID_2032_CLKM_DEFAULT_VALUE << AW_PID_2032_CLKM_START_BIT)
|
|
|
|
/* OCDM bit 3 (SYSINTM 0x03) */
|
|
#define AW_PID_2032_OCDM_START_BIT (3)
|
|
#define AW_PID_2032_OCDM_BITS_LEN (1)
|
|
#define AW_PID_2032_OCDM_MASK \
|
|
(~(((1<<AW_PID_2032_OCDM_BITS_LEN)-1) << AW_PID_2032_OCDM_START_BIT))
|
|
|
|
#define AW_PID_2032_OCDM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_OCDM_DEFAULT \
|
|
(AW_PID_2032_OCDM_DEFAULT_VALUE << AW_PID_2032_OCDM_START_BIT)
|
|
|
|
/* CLIP_PREM bit 2 (SYSINTM 0x03) */
|
|
#define AW_PID_2032_CLIP_PREM_START_BIT (2)
|
|
#define AW_PID_2032_CLIP_PREM_BITS_LEN (1)
|
|
#define AW_PID_2032_CLIP_PREM_MASK \
|
|
(~(((1<<AW_PID_2032_CLIP_PREM_BITS_LEN)-1) << AW_PID_2032_CLIP_PREM_START_BIT))
|
|
|
|
#define AW_PID_2032_CLIP_PREM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_CLIP_PREM_DEFAULT \
|
|
(AW_PID_2032_CLIP_PREM_DEFAULT_VALUE << AW_PID_2032_CLIP_PREM_START_BIT)
|
|
|
|
/* OTHM bit 1 (SYSINTM 0x03) */
|
|
#define AW_PID_2032_OTHM_START_BIT (1)
|
|
#define AW_PID_2032_OTHM_BITS_LEN (1)
|
|
#define AW_PID_2032_OTHM_MASK \
|
|
(~(((1<<AW_PID_2032_OTHM_BITS_LEN)-1) << AW_PID_2032_OTHM_START_BIT))
|
|
|
|
#define AW_PID_2032_OTHM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_OTHM_DEFAULT \
|
|
(AW_PID_2032_OTHM_DEFAULT_VALUE << AW_PID_2032_OTHM_START_BIT)
|
|
|
|
/* PLLM bit 0 (SYSINTM 0x03) */
|
|
#define AW_PID_2032_PLLM_START_BIT (0)
|
|
#define AW_PID_2032_PLLM_BITS_LEN (1)
|
|
#define AW_PID_2032_PLLM_MASK \
|
|
(~(((1<<AW_PID_2032_PLLM_BITS_LEN)-1) << AW_PID_2032_PLLM_START_BIT))
|
|
|
|
#define AW_PID_2032_PLLM_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_PLLM_DEFAULT \
|
|
(AW_PID_2032_PLLM_DEFAULT_VALUE << AW_PID_2032_PLLM_START_BIT)
|
|
|
|
/* default value of SYSINTM (0x03) */
|
|
/* #define AW_PID_2032_SYSINTM_DEFAULT (0xEFBF) */
|
|
|
|
/* SYSCTRL (0x04) detail */
|
|
/* ULS_MODE bit 15 (SYSCTRL 0x04) */
|
|
#define AW_PID_2032_ULS_MODE_START_BIT (15)
|
|
#define AW_PID_2032_ULS_MODE_BITS_LEN (1)
|
|
#define AW_PID_2032_ULS_MODE_MASK \
|
|
(~(((1<<AW_PID_2032_ULS_MODE_BITS_LEN)-1) << AW_PID_2032_ULS_MODE_START_BIT))
|
|
|
|
#define AW_PID_2032_ULS_MODE_LEGACY (0)
|
|
#define AW_PID_2032_ULS_MODE_LEGACY_VALUE \
|
|
(AW_PID_2032_ULS_MODE_LEGACY << AW_PID_2032_ULS_MODE_START_BIT)
|
|
|
|
#define AW_PID_2032_ULS_MODE_TDM (1)
|
|
#define AW_PID_2032_ULS_MODE_TDM_VALUE \
|
|
(AW_PID_2032_ULS_MODE_TDM << AW_PID_2032_ULS_MODE_START_BIT)
|
|
|
|
#define AW_PID_2032_ULS_MODE_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_ULS_MODE_DEFAULT \
|
|
(AW_PID_2032_ULS_MODE_DEFAULT_VALUE << AW_PID_2032_ULS_MODE_START_BIT)
|
|
|
|
/* SPK_GAIN bit 14:12 (SYSCTRL 0x04) */
|
|
#define AW_PID_2032_SPK_GAIN_START_BIT (12)
|
|
#define AW_PID_2032_SPK_GAIN_BITS_LEN (3)
|
|
#define AW_PID_2032_SPK_GAIN_MASK \
|
|
(~(((1<<AW_PID_2032_SPK_GAIN_BITS_LEN)-1) << AW_PID_2032_SPK_GAIN_START_BIT))
|
|
|
|
#define AW_PID_2032_SPK_GAIN_7 (0)
|
|
#define AW_PID_2032_SPK_GAIN_7_VALUE \
|
|
(AW_PID_2032_SPK_GAIN_7 << AW_PID_2032_SPK_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2032_SPK_GAIN_8 (1)
|
|
#define AW_PID_2032_SPK_GAIN_8_VALUE \
|
|
(AW_PID_2032_SPK_GAIN_8 << AW_PID_2032_SPK_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2032_SPK_GAIN_10 (2)
|
|
#define AW_PID_2032_SPK_GAIN_10_VALUE \
|
|
(AW_PID_2032_SPK_GAIN_10 << AW_PID_2032_SPK_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2032_SPK_GAIN_14 (3)
|
|
#define AW_PID_2032_SPK_GAIN_14_VALUE \
|
|
(AW_PID_2032_SPK_GAIN_14 << AW_PID_2032_SPK_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2032_SPK_GAIN_16 (4)
|
|
#define AW_PID_2032_SPK_GAIN_16_VALUE \
|
|
(AW_PID_2032_SPK_GAIN_16 << AW_PID_2032_SPK_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2032_SPK_GAIN_20 (5)
|
|
#define AW_PID_2032_SPK_GAIN_20_VALUE \
|
|
(AW_PID_2032_SPK_GAIN_20 << AW_PID_2032_SPK_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2032_SPK_GAIN_DEFAULT_VALUE (0x4)
|
|
#define AW_PID_2032_SPK_GAIN_DEFAULT \
|
|
(AW_PID_2032_SPK_GAIN_DEFAULT_VALUE << AW_PID_2032_SPK_GAIN_START_BIT)
|
|
|
|
/* RCV_GAIN bit 11:10 (SYSCTRL 0x04) */
|
|
#define AW_PID_2032_RCV_GAIN_START_BIT (10)
|
|
#define AW_PID_2032_RCV_GAIN_BITS_LEN (2)
|
|
#define AW_PID_2032_RCV_GAIN_MASK \
|
|
(~(((1<<AW_PID_2032_RCV_GAIN_BITS_LEN)-1) << AW_PID_2032_RCV_GAIN_START_BIT))
|
|
|
|
#define AW_PID_2032_RCV_GAIN_4P5 (0)
|
|
#define AW_PID_2032_RCV_GAIN_4P5_VALUE \
|
|
(AW_PID_2032_RCV_GAIN_4P5 << AW_PID_2032_RCV_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2032_RCV_GAIN_5P0 (1)
|
|
#define AW_PID_2032_RCV_GAIN_5P0_VALUE \
|
|
(AW_PID_2032_RCV_GAIN_5P0 << AW_PID_2032_RCV_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2032_RCV_GAIN_5P5 (2)
|
|
#define AW_PID_2032_RCV_GAIN_5P5_VALUE \
|
|
(AW_PID_2032_RCV_GAIN_5P5 << AW_PID_2032_RCV_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2032_RCV_GAIN_7P5 (3)
|
|
#define AW_PID_2032_RCV_GAIN_7P5_VALUE \
|
|
(AW_PID_2032_RCV_GAIN_7P5 << AW_PID_2032_RCV_GAIN_START_BIT)
|
|
|
|
#define AW_PID_2032_RCV_GAIN_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_RCV_GAIN_DEFAULT \
|
|
(AW_PID_2032_RCV_GAIN_DEFAULT_VALUE << AW_PID_2032_RCV_GAIN_START_BIT)
|
|
|
|
/* INTMODE bit 9 (SYSCTRL 0x04) */
|
|
#define AW_PID_2032_INTMODE_START_BIT (9)
|
|
#define AW_PID_2032_INTMODE_BITS_LEN (1)
|
|
#define AW_PID_2032_INTMODE_MASK \
|
|
(~(((1<<AW_PID_2032_INTMODE_BITS_LEN)-1) << AW_PID_2032_INTMODE_START_BIT))
|
|
|
|
#define AW_PID_2032_INTMODE_OPENMINUS_DRAIN (0)
|
|
#define AW_PID_2032_INTMODE_OPENMINUS_DRAIN_VALUE \
|
|
(AW_PID_2032_INTMODE_OPENMINUS_DRAIN << AW_PID_2032_INTMODE_START_BIT)
|
|
|
|
#define AW_PID_2032_INTMODE_PUSHPULL (1)
|
|
#define AW_PID_2032_INTMODE_PUSHPULL_VALUE \
|
|
(AW_PID_2032_INTMODE_PUSHPULL << AW_PID_2032_INTMODE_START_BIT)
|
|
|
|
#define AW_PID_2032_INTMODE_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_INTMODE_DEFAULT \
|
|
(AW_PID_2032_INTMODE_DEFAULT_VALUE << AW_PID_2032_INTMODE_START_BIT)
|
|
|
|
/* default value of SYSINTM (0x03) */
|
|
#define AW_PID_2032_SYSINTM_DEFAULT (0xEFBF)
|
|
|
|
/* INTN bit 8 (SYSCTRL 0x04) */
|
|
#define AW_PID_2032_INTN_START_BIT (8)
|
|
#define AW_PID_2032_INTN_BITS_LEN (1)
|
|
#define AW_PID_2032_INTN_MASK \
|
|
(~(((1<<AW_PID_2032_INTN_BITS_LEN)-1) << AW_PID_2032_INTN_START_BIT))
|
|
|
|
#define AW_PID_2032_INTN_SYSINT (0)
|
|
#define AW_PID_2032_INTN_SYSINT_VALUE \
|
|
(AW_PID_2032_INTN_SYSINT << AW_PID_2032_INTN_START_BIT)
|
|
|
|
#define AW_PID_2032_INTN_SYSST (1)
|
|
#define AW_PID_2032_INTN_SYSST_VALUE \
|
|
(AW_PID_2032_INTN_SYSST << AW_PID_2032_INTN_START_BIT)
|
|
|
|
#define AW_PID_2032_INTN_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_INTN_DEFAULT \
|
|
(AW_PID_2032_INTN_DEFAULT_VALUE << AW_PID_2032_INTN_START_BIT)
|
|
|
|
/* RCV_MODE bit 7 (SYSCTRL 0x04) */
|
|
#define AW_PID_2032_RCV_MODE_START_BIT (7)
|
|
#define AW_PID_2032_RCV_MODE_BITS_LEN (1)
|
|
#define AW_PID_2032_RCV_MODE_MASK \
|
|
(~(((1<<AW_PID_2032_RCV_MODE_BITS_LEN)-1) << AW_PID_2032_RCV_MODE_START_BIT))
|
|
|
|
#define AW_PID_2032_RCV_MODE_SPEAKER (0)
|
|
#define AW_PID_2032_RCV_MODE_SPEAKER_VALUE \
|
|
(AW_PID_2032_RCV_MODE_SPEAKER << AW_PID_2032_RCV_MODE_START_BIT)
|
|
|
|
#define AW_PID_2032_RCV_MODE_RECEIVER (1)
|
|
#define AW_PID_2032_RCV_MODE_RECEIVER_VALUE \
|
|
(AW_PID_2032_RCV_MODE_RECEIVER << AW_PID_2032_RCV_MODE_START_BIT)
|
|
|
|
#define AW_PID_2032_RCV_MODE_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_RCV_MODE_DEFAULT \
|
|
(AW_PID_2032_RCV_MODE_DEFAULT_VALUE << AW_PID_2032_RCV_MODE_START_BIT)
|
|
|
|
/* I2SEN bit 6 (SYSCTRL 0x04) */
|
|
#define AW_PID_2032_I2SEN_START_BIT (6)
|
|
#define AW_PID_2032_I2SEN_BITS_LEN (1)
|
|
#define AW_PID_2032_I2SEN_MASK \
|
|
(~(((1<<AW_PID_2032_I2SEN_BITS_LEN)-1) << AW_PID_2032_I2SEN_START_BIT))
|
|
|
|
#define AW_PID_2032_I2SEN_DISABLE (0)
|
|
#define AW_PID_2032_I2SEN_DISABLE_VALUE \
|
|
(AW_PID_2032_I2SEN_DISABLE << AW_PID_2032_I2SEN_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SEN_ENABLE (1)
|
|
#define AW_PID_2032_I2SEN_ENABLE_VALUE \
|
|
(AW_PID_2032_I2SEN_ENABLE << AW_PID_2032_I2SEN_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SEN_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_I2SEN_DEFAULT \
|
|
(AW_PID_2032_I2SEN_DEFAULT_VALUE << AW_PID_2032_I2SEN_START_BIT)
|
|
|
|
/* WSINV bit 5 (SYSCTRL 0x04) */
|
|
#define AW_PID_2032_WSINV_START_BIT (5)
|
|
#define AW_PID_2032_WSINV_BITS_LEN (1)
|
|
#define AW_PID_2032_WSINV_MASK \
|
|
(~(((1<<AW_PID_2032_WSINV_BITS_LEN)-1) << AW_PID_2032_WSINV_START_BIT))
|
|
|
|
#define AW_PID_2032_WSINV_NOT_SWITCH (0)
|
|
#define AW_PID_2032_WSINV_NOT_SWITCH_VALUE \
|
|
(AW_PID_2032_WSINV_NOT_SWITCH << AW_PID_2032_WSINV_START_BIT)
|
|
|
|
#define AW_PID_2032_WSINV_SWITCH (1)
|
|
#define AW_PID_2032_WSINV_SWITCH_VALUE \
|
|
(AW_PID_2032_WSINV_SWITCH << AW_PID_2032_WSINV_START_BIT)
|
|
|
|
#define AW_PID_2032_WSINV_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_WSINV_DEFAULT \
|
|
(AW_PID_2032_WSINV_DEFAULT_VALUE << AW_PID_2032_WSINV_START_BIT)
|
|
|
|
/* BCKINV bit 4 (SYSCTRL 0x04) */
|
|
#define AW_PID_2032_BCKINV_START_BIT (4)
|
|
#define AW_PID_2032_BCKINV_BITS_LEN (1)
|
|
#define AW_PID_2032_BCKINV_MASK \
|
|
(~(((1<<AW_PID_2032_BCKINV_BITS_LEN)-1) << AW_PID_2032_BCKINV_START_BIT))
|
|
|
|
#define AW_PID_2032_BCKINV_NOT_INVERT (0)
|
|
#define AW_PID_2032_BCKINV_NOT_INVERT_VALUE \
|
|
(AW_PID_2032_BCKINV_NOT_INVERT << AW_PID_2032_BCKINV_START_BIT)
|
|
|
|
#define AW_PID_2032_BCKINV_INVERTED (1)
|
|
#define AW_PID_2032_BCKINV_INVERTED_VALUE \
|
|
(AW_PID_2032_BCKINV_INVERTED << AW_PID_2032_BCKINV_START_BIT)
|
|
|
|
#define AW_PID_2032_BCKINV_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_BCKINV_DEFAULT \
|
|
(AW_PID_2032_BCKINV_DEFAULT_VALUE << AW_PID_2032_BCKINV_START_BIT)
|
|
|
|
/* IPLL bit 3 (SYSCTRL 0x04) */
|
|
#define AW_PID_2032_IPLL_START_BIT (3)
|
|
#define AW_PID_2032_IPLL_BITS_LEN (1)
|
|
#define AW_PID_2032_IPLL_MASK \
|
|
(~(((1<<AW_PID_2032_IPLL_BITS_LEN)-1) << AW_PID_2032_IPLL_START_BIT))
|
|
|
|
#define AW_PID_2032_IPLL_BCK (0)
|
|
#define AW_PID_2032_IPLL_BCK_VALUE \
|
|
(AW_PID_2032_IPLL_BCK << AW_PID_2032_IPLL_START_BIT)
|
|
|
|
#define AW_PID_2032_IPLL_WCK (1)
|
|
#define AW_PID_2032_IPLL_WCK_VALUE \
|
|
(AW_PID_2032_IPLL_WCK << AW_PID_2032_IPLL_START_BIT)
|
|
|
|
#define AW_PID_2032_IPLL_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_IPLL_DEFAULT \
|
|
(AW_PID_2032_IPLL_DEFAULT_VALUE << AW_PID_2032_IPLL_START_BIT)
|
|
|
|
/* AMPPD bit 1 (SYSCTRL 0x04) */
|
|
#define AW_PID_2032_AMPPD_START_BIT (1)
|
|
#define AW_PID_2032_AMPPD_BITS_LEN (1)
|
|
#define AW_PID_2032_AMPPD_MASK \
|
|
(~(((1<<AW_PID_2032_AMPPD_BITS_LEN)-1) << AW_PID_2032_AMPPD_START_BIT))
|
|
|
|
#define AW_PID_2032_AMPPD_WORKING (0)
|
|
#define AW_PID_2032_AMPPD_WORKING_VALUE \
|
|
(AW_PID_2032_AMPPD_WORKING << AW_PID_2032_AMPPD_START_BIT)
|
|
|
|
#define AW_PID_2032_AMPPD_POWER_DOWN (1)
|
|
#define AW_PID_2032_AMPPD_POWER_DOWN_VALUE \
|
|
(AW_PID_2032_AMPPD_POWER_DOWN << AW_PID_2032_AMPPD_START_BIT)
|
|
|
|
#define AW_PID_2032_AMPPD_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_AMPPD_DEFAULT \
|
|
(AW_PID_2032_AMPPD_DEFAULT_VALUE << AW_PID_2032_AMPPD_START_BIT)
|
|
|
|
/* PWDN bit 0 (SYSCTRL 0x04) */
|
|
#define AW_PID_2032_PWDN_START_BIT (0)
|
|
#define AW_PID_2032_PWDN_BITS_LEN (1)
|
|
#define AW_PID_2032_PWDN_MASK \
|
|
(~(((1<<AW_PID_2032_PWDN_BITS_LEN)-1) << AW_PID_2032_PWDN_START_BIT))
|
|
|
|
#define AW_PID_2032_PWDN_WORKING (0)
|
|
#define AW_PID_2032_PWDN_WORKING_VALUE \
|
|
(AW_PID_2032_PWDN_WORKING << AW_PID_2032_PWDN_START_BIT)
|
|
|
|
#define AW_PID_2032_PWDN_POWER_DOWN (1)
|
|
#define AW_PID_2032_PWDN_POWER_DOWN_VALUE \
|
|
(AW_PID_2032_PWDN_POWER_DOWN << AW_PID_2032_PWDN_START_BIT)
|
|
|
|
#define AW_PID_2032_PWDN_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_PWDN_DEFAULT \
|
|
(AW_PID_2032_PWDN_DEFAULT_VALUE << AW_PID_2032_PWDN_START_BIT)
|
|
|
|
/* default value of SYSCTRL (0x04) */
|
|
/* #define AW_PID_2032_SYSCTRL_DEFAULT (0x4003) */
|
|
|
|
/* SYSCTRL2 (0x05) detail */
|
|
/* VOL bit 15:6 (SYSCTRL2 0x05) */
|
|
#define AW_PID_2032_VOL_START_BIT (6)
|
|
#define AW_PID_2032_VOL_BITS_LEN (10)
|
|
#define AW_PID_2032_VOL_MASK \
|
|
(~(((1<<AW_PID_2032_VOL_BITS_LEN)-1) << AW_PID_2032_VOL_START_BIT))
|
|
|
|
#define AW_PID_2032_VOL_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_VOL_DEFAULT \
|
|
(AW_PID_2032_VOL_DEFAULT_VALUE << AW_PID_2032_VOL_START_BIT)
|
|
|
|
/* HDCCE bit 5 (SYSCTRL2 0x05) */
|
|
#define AW_PID_2032_HDCCE_START_BIT (5)
|
|
#define AW_PID_2032_HDCCE_BITS_LEN (1)
|
|
#define AW_PID_2032_HDCCE_MASK \
|
|
(~(((1<<AW_PID_2032_HDCCE_BITS_LEN)-1) << AW_PID_2032_HDCCE_START_BIT))
|
|
|
|
#define AW_PID_2032_HDCCE_DISABLE (0)
|
|
#define AW_PID_2032_HDCCE_DISABLE_VALUE \
|
|
(AW_PID_2032_HDCCE_DISABLE << AW_PID_2032_HDCCE_START_BIT)
|
|
|
|
#define AW_PID_2032_HDCCE_ENABLE (1)
|
|
#define AW_PID_2032_HDCCE_ENABLE_VALUE \
|
|
(AW_PID_2032_HDCCE_ENABLE << AW_PID_2032_HDCCE_START_BIT)
|
|
|
|
#define AW_PID_2032_HDCCE_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_HDCCE_DEFAULT \
|
|
(AW_PID_2032_HDCCE_DEFAULT_VALUE << AW_PID_2032_HDCCE_START_BIT)
|
|
|
|
/* HMUTE bit 4 (SYSCTRL2 0x05) */
|
|
#define AW_PID_2032_HMUTE_START_BIT (4)
|
|
#define AW_PID_2032_HMUTE_BITS_LEN (1)
|
|
#define AW_PID_2032_HMUTE_MASK \
|
|
(~(((1<<AW_PID_2032_HMUTE_BITS_LEN)-1) << AW_PID_2032_HMUTE_START_BIT))
|
|
|
|
#define AW_PID_2032_HMUTE_DISABLE (0)
|
|
#define AW_PID_2032_HMUTE_DISABLE_VALUE \
|
|
(AW_PID_2032_HMUTE_DISABLE << AW_PID_2032_HMUTE_START_BIT)
|
|
|
|
#define AW_PID_2032_HMUTE_ENABLE (1)
|
|
#define AW_PID_2032_HMUTE_ENABLE_VALUE \
|
|
(AW_PID_2032_HMUTE_ENABLE << AW_PID_2032_HMUTE_START_BIT)
|
|
|
|
#define AW_PID_2032_HMUTE_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_HMUTE_DEFAULT \
|
|
(AW_PID_2032_HMUTE_DEFAULT_VALUE << AW_PID_2032_HMUTE_START_BIT)
|
|
|
|
/* BST_IPEAK bit 3:0 (SYSCTRL2 0x05) */
|
|
#define AW_PID_2032_BST_IPEAK_START_BIT (0)
|
|
#define AW_PID_2032_BST_IPEAK_BITS_LEN (4)
|
|
#define AW_PID_2032_BST_IPEAK_MASK \
|
|
(~(((1<<AW_PID_2032_BST_IPEAK_BITS_LEN)-1) << AW_PID_2032_BST_IPEAK_START_BIT))
|
|
|
|
#define AW_PID_2032_BST_IPEAK_1P50A (0)
|
|
#define AW_PID_2032_BST_IPEAK_1P50A_VALUE \
|
|
(AW_PID_2032_BST_IPEAK_1P50A << AW_PID_2032_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_IPEAK_1P75A (1)
|
|
#define AW_PID_2032_BST_IPEAK_1P75A_VALUE \
|
|
(AW_PID_2032_BST_IPEAK_1P75A << AW_PID_2032_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_IPEAK_2P00A (2)
|
|
#define AW_PID_2032_BST_IPEAK_2P00A_VALUE \
|
|
(AW_PID_2032_BST_IPEAK_2P00A << AW_PID_2032_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_IPEAK_2P25A (3)
|
|
#define AW_PID_2032_BST_IPEAK_2P25A_VALUE \
|
|
(AW_PID_2032_BST_IPEAK_2P25A << AW_PID_2032_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_IPEAK_2P50A (4)
|
|
#define AW_PID_2032_BST_IPEAK_2P50A_VALUE \
|
|
(AW_PID_2032_BST_IPEAK_2P50A << AW_PID_2032_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_IPEAK_2P75A (5)
|
|
#define AW_PID_2032_BST_IPEAK_2P75A_VALUE \
|
|
(AW_PID_2032_BST_IPEAK_2P75A << AW_PID_2032_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_IPEAK_3P00A (6)
|
|
#define AW_PID_2032_BST_IPEAK_3P00A_VALUE \
|
|
(AW_PID_2032_BST_IPEAK_3P00A << AW_PID_2032_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_IPEAK_3P25A (7)
|
|
#define AW_PID_2032_BST_IPEAK_3P25A_VALUE \
|
|
(AW_PID_2032_BST_IPEAK_3P25A << AW_PID_2032_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_IPEAK_3P50A (8)
|
|
#define AW_PID_2032_BST_IPEAK_3P50A_VALUE \
|
|
(AW_PID_2032_BST_IPEAK_3P50A << AW_PID_2032_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_IPEAK_3P75A (9)
|
|
#define AW_PID_2032_BST_IPEAK_3P75A_VALUE \
|
|
(AW_PID_2032_BST_IPEAK_3P75A << AW_PID_2032_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_IPEAK_4P00A (10)
|
|
#define AW_PID_2032_BST_IPEAK_4P00A_VALUE \
|
|
(AW_PID_2032_BST_IPEAK_4P00A << AW_PID_2032_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_IPEAK_4P25A (11)
|
|
#define AW_PID_2032_BST_IPEAK_4P25A_VALUE \
|
|
(AW_PID_2032_BST_IPEAK_4P25A << AW_PID_2032_BST_IPEAK_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_IPEAK_DEFAULT_VALUE (8)
|
|
#define AW_PID_2032_BST_IPEAK_DEFAULT \
|
|
(AW_PID_2032_BST_IPEAK_DEFAULT_VALUE << AW_PID_2032_BST_IPEAK_START_BIT)
|
|
|
|
/* default value of SYSCTRL2 (0x05) */
|
|
/* #define AW_PID_2032_SYSCTRL2_DEFAULT (0x0038) */
|
|
|
|
#define AW_PID_2032_MUTE_VOL (90 * 8)
|
|
#define AW_PID_2032_VOL_STEP_DB (6 * 8)
|
|
|
|
/* I2SCTRL (0x06) detail */
|
|
/* RX_THRS bit 15:14 (I2SCTRL 0x06) */
|
|
#define AW_PID_2032_RX_THRS_START_BIT (14)
|
|
#define AW_PID_2032_RX_THRS_BITS_LEN (2)
|
|
#define AW_PID_2032_RX_THRS_MASK \
|
|
(~(((1<<AW_PID_2032_RX_THRS_BITS_LEN)-1) << AW_PID_2032_RX_THRS_START_BIT))
|
|
|
|
#define AW_PID_2032_RX_THRS_DEFAULT_VALUE (2)
|
|
#define AW_PID_2032_RX_THRS_DEFAULT \
|
|
(AW_PID_2032_RX_THRS_DEFAULT_VALUE << AW_PID_2032_RX_THRS_START_BIT)
|
|
|
|
/* INPLEV bit 13 (I2SCTRL 0x06) */
|
|
#define AW_PID_2032_INPLEV_START_BIT (13)
|
|
#define AW_PID_2032_INPLEV_BITS_LEN (1)
|
|
#define AW_PID_2032_INPLEV_MASK \
|
|
(~(((1<<AW_PID_2032_INPLEV_BITS_LEN)-1) << AW_PID_2032_INPLEV_START_BIT))
|
|
|
|
#define AW_PID_2032_INPLEV_NOT_ATTENUATED (0)
|
|
#define AW_PID_2032_INPLEV_NOT_ATTENUATED_VALUE \
|
|
(AW_PID_2032_INPLEV_NOT_ATTENUATED << AW_PID_2032_INPLEV_START_BIT)
|
|
|
|
#define AW_PID_2032_INPLEV_ATTENUATED (1)
|
|
#define AW_PID_2032_INPLEV_ATTENUATED_VALUE \
|
|
(AW_PID_2032_INPLEV_ATTENUATED << AW_PID_2032_INPLEV_START_BIT)
|
|
|
|
#define AW_PID_2032_INPLEV_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_INPLEV_DEFAULT \
|
|
(AW_PID_2032_INPLEV_DEFAULT_VALUE << AW_PID_2032_INPLEV_START_BIT)
|
|
|
|
/* I2SRXEN bit 12 (I2SCTRL 0x06) */
|
|
#define AW_PID_2032_I2SRXEN_START_BIT (12)
|
|
#define AW_PID_2032_I2SRXEN_BITS_LEN (1)
|
|
#define AW_PID_2032_I2SRXEN_MASK \
|
|
(~(((1<<AW_PID_2032_I2SRXEN_BITS_LEN)-1) << AW_PID_2032_I2SRXEN_START_BIT))
|
|
|
|
#define AW_PID_2032_I2SRXEN_DISABLE (0)
|
|
#define AW_PID_2032_I2SRXEN_DISABLE_VALUE \
|
|
(AW_PID_2032_I2SRXEN_DISABLE << AW_PID_2032_I2SRXEN_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SRXEN_ENABLE (1)
|
|
#define AW_PID_2032_I2SRXEN_ENABLE_VALUE \
|
|
(AW_PID_2032_I2SRXEN_ENABLE << AW_PID_2032_I2SRXEN_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SRXEN_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_I2SRXEN_DEFAULT \
|
|
(AW_PID_2032_I2SRXEN_DEFAULT_VALUE << AW_PID_2032_I2SRXEN_START_BIT)
|
|
|
|
/* CHSEL bit 11:10 (I2SCTRL 0x06) */
|
|
#define AW_PID_2032_CHSEL_START_BIT (10)
|
|
#define AW_PID_2032_CHSEL_BITS_LEN (2)
|
|
#define AW_PID_2032_CHSEL_MASK \
|
|
(~(((1<<AW_PID_2032_CHSEL_BITS_LEN)-1) << AW_PID_2032_CHSEL_START_BIT))
|
|
|
|
#define AW_PID_2032_CHSEL_RESERVED (0)
|
|
#define AW_PID_2032_CHSEL_RESERVED_VALUE \
|
|
(AW_PID_2032_CHSEL_RESERVED << AW_PID_2032_CHSEL_START_BIT)
|
|
|
|
#define AW_PID_2032_CHSEL_LEFT (1)
|
|
#define AW_PID_2032_CHSEL_LEFT_VALUE \
|
|
(AW_PID_2032_CHSEL_LEFT << AW_PID_2032_CHSEL_START_BIT)
|
|
|
|
#define AW_PID_2032_CHSEL_RIGHT (2)
|
|
#define AW_PID_2032_CHSEL_RIGHT_VALUE \
|
|
(AW_PID_2032_CHSEL_RIGHT << AW_PID_2032_CHSEL_START_BIT)
|
|
|
|
#define AW_PID_2032_CHSEL_MONO (3)
|
|
#define AW_PID_2032_CHSEL_MONO_VALUE \
|
|
(AW_PID_2032_CHSEL_MONO << AW_PID_2032_CHSEL_START_BIT)
|
|
|
|
#define AW_PID_2032_CHSEL_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_CHSEL_DEFAULT \
|
|
(AW_PID_2032_CHSEL_DEFAULT_VALUE << AW_PID_2032_CHSEL_START_BIT)
|
|
|
|
/* I2SMD bit 9:8 (I2SCTRL 0x06) */
|
|
#define AW_PID_2032_I2SMD_START_BIT (8)
|
|
#define AW_PID_2032_I2SMD_BITS_LEN (2)
|
|
#define AW_PID_2032_I2SMD_MASK \
|
|
(~(((1<<AW_PID_2032_I2SMD_BITS_LEN)-1) << AW_PID_2032_I2SMD_START_BIT))
|
|
|
|
#define AW_PID_2032_I2SMD_PHILIP_STANDARD (0)
|
|
#define AW_PID_2032_I2SMD_PHILIP_STANDARD_VALUE \
|
|
(AW_PID_2032_I2SMD_PHILIP_STANDARD << AW_PID_2032_I2SMD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SMD_MSB_JUSTIFIED (1)
|
|
#define AW_PID_2032_I2SMD_MSB_JUSTIFIED_VALUE \
|
|
(AW_PID_2032_I2SMD_MSB_JUSTIFIED << AW_PID_2032_I2SMD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SMD_LSB_JUSTIFIED (2)
|
|
#define AW_PID_2032_I2SMD_LSB_JUSTIFIED_VALUE \
|
|
(AW_PID_2032_I2SMD_LSB_JUSTIFIED << AW_PID_2032_I2SMD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SMD_RESERVED (3)
|
|
#define AW_PID_2032_I2SMD_RESERVED_VALUE \
|
|
(AW_PID_2032_I2SMD_RESERVED << AW_PID_2032_I2SMD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SMD_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_I2SMD_DEFAULT \
|
|
(AW_PID_2032_I2SMD_DEFAULT_VALUE << AW_PID_2032_I2SMD_START_BIT)
|
|
|
|
/* I2SFS bit 7:6 (I2SCTRL 0x06) */
|
|
#define AW_PID_2032_I2SFS_START_BIT (6)
|
|
#define AW_PID_2032_I2SFS_BITS_LEN (2)
|
|
#define AW_PID_2032_I2SFS_MASK \
|
|
(~(((1<<AW_PID_2032_I2SFS_BITS_LEN)-1) << AW_PID_2032_I2SFS_START_BIT))
|
|
|
|
#define AW_PID_2032_I2SFS_16_BITS (0)
|
|
#define AW_PID_2032_I2SFS_16_BITS_VALUE \
|
|
(AW_PID_2032_I2SFS_16_BITS << AW_PID_2032_I2SFS_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SFS_20_BITS (1)
|
|
#define AW_PID_2032_I2SFS_20_BITS_VALUE \
|
|
(AW_PID_2032_I2SFS_20_BITS << AW_PID_2032_I2SFS_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SFS_24_BITS (2)
|
|
#define AW_PID_2032_I2SFS_24_BITS_VALUE \
|
|
(AW_PID_2032_I2SFS_24_BITS << AW_PID_2032_I2SFS_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SFS_32_BITS (3)
|
|
#define AW_PID_2032_I2SFS_32_BITS_VALUE \
|
|
(AW_PID_2032_I2SFS_32_BITS << AW_PID_2032_I2SFS_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SFS_DEFAULT_VALUE (3)
|
|
#define AW_PID_2032_I2SFS_DEFAULT \
|
|
(AW_PID_2032_I2SFS_DEFAULT_VALUE << AW_PID_2032_I2SFS_START_BIT)
|
|
|
|
/* I2SBCK bit 5:4 (I2SCTRL 0x06) */
|
|
#define AW_PID_2032_I2SBCK_START_BIT (4)
|
|
#define AW_PID_2032_I2SBCK_BITS_LEN (2)
|
|
#define AW_PID_2032_I2SBCK_MASK \
|
|
(~(((1<<AW_PID_2032_I2SBCK_BITS_LEN)-1) << AW_PID_2032_I2SBCK_START_BIT))
|
|
|
|
#define AW_PID_2032_I2SBCK_32FS (0)
|
|
#define AW_PID_2032_I2SBCK_32FS_VALUE \
|
|
(AW_PID_2032_I2SBCK_32FS << AW_PID_2032_I2SBCK_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SBCK_48FS (1)
|
|
#define AW_PID_2032_I2SBCK_48FS_VALUE \
|
|
(AW_PID_2032_I2SBCK_48FS << AW_PID_2032_I2SBCK_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SBCK_64FS (2)
|
|
#define AW_PID_2032_I2SBCK_64FS_VALUE \
|
|
(AW_PID_2032_I2SBCK_64FS << AW_PID_2032_I2SBCK_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SBCK_RESERVED (3)
|
|
#define AW_PID_2032_I2SBCK_RESERVED_VALUE \
|
|
(AW_PID_2032_I2SBCK_RESERVED << AW_PID_2032_I2SBCK_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SBCK_DEFAULT_VALUE (2)
|
|
#define AW_PID_2032_I2SBCK_DEFAULT \
|
|
(AW_PID_2032_I2SBCK_DEFAULT_VALUE << AW_PID_2032_I2SBCK_START_BIT)
|
|
|
|
/* I2SSR bit 3:0 (I2SCTRL 0x06) */
|
|
#define AW_PID_2032_I2SSR_START_BIT (0)
|
|
#define AW_PID_2032_I2SSR_BITS_LEN (4)
|
|
#define AW_PID_2032_I2SSR_MASK \
|
|
(~(((1<<AW_PID_2032_I2SSR_BITS_LEN)-1) << AW_PID_2032_I2SSR_START_BIT))
|
|
|
|
#define AW_PID_2032_I2SSR_8_KHZ (0)
|
|
#define AW_PID_2032_I2SSR_8_KHZ_VALUE \
|
|
(AW_PID_2032_I2SSR_8_KHZ << AW_PID_2032_I2SSR_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SSR_11_KHZ (1)
|
|
#define AW_PID_2032_I2SSR_11_KHZ_VALUE \
|
|
(AW_PID_2032_I2SSR_11_KHZ << AW_PID_2032_I2SSR_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SSR_12_KHZ (2)
|
|
#define AW_PID_2032_I2SSR_12_KHZ_VALUE \
|
|
(AW_PID_2032_I2SSR_12_KHZ << AW_PID_2032_I2SSR_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SSR_16_KHZ (3)
|
|
#define AW_PID_2032_I2SSR_16_KHZ_VALUE \
|
|
(AW_PID_2032_I2SSR_16_KHZ << AW_PID_2032_I2SSR_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SSR_22_KHZ (4)
|
|
#define AW_PID_2032_I2SSR_22_KHZ_VALUE \
|
|
(AW_PID_2032_I2SSR_22_KHZ << AW_PID_2032_I2SSR_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SSR_24_KHZ (5)
|
|
#define AW_PID_2032_I2SSR_24_KHZ_VALUE \
|
|
(AW_PID_2032_I2SSR_24_KHZ << AW_PID_2032_I2SSR_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SSR_32_KHZ (6)
|
|
#define AW_PID_2032_I2SSR_32_KHZ_VALUE \
|
|
(AW_PID_2032_I2SSR_32_KHZ << AW_PID_2032_I2SSR_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SSR_44_KHZ (7)
|
|
#define AW_PID_2032_I2SSR_44_KHZ_VALUE \
|
|
(AW_PID_2032_I2SSR_44_KHZ << AW_PID_2032_I2SSR_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SSR_48_KHZ (8)
|
|
#define AW_PID_2032_I2SSR_48_KHZ_VALUE \
|
|
(AW_PID_2032_I2SSR_48_KHZ << AW_PID_2032_I2SSR_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SSR_96_KHZ (9)
|
|
#define AW_PID_2032_I2SSR_96_KHZ_VALUE \
|
|
(AW_PID_2032_I2SSR_96_KHZ << AW_PID_2032_I2SSR_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SSR_DEFAULT_VALUE (8)
|
|
#define AW_PID_2032_I2SSR_DEFAULT \
|
|
(AW_PID_2032_I2SSR_DEFAULT_VALUE << AW_PID_2032_I2SSR_START_BIT)
|
|
|
|
/* default value of I2SCTRL (0x06) */
|
|
/* #define AW_PID_2032_I2SCTRL_DEFAULT (0x94E8) */
|
|
|
|
/* I2SCFG1 (0x07) detail */
|
|
/* I2S_TX_SLOTVLD bit 15:12 (I2SCFG1 0x07) */
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_START_BIT (12)
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_BITS_LEN (4)
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_MASK \
|
|
(~(((1<<AW_PID_2032_I2S_TX_SLOTVLD_BITS_LEN)-1) << AW_PID_2032_I2S_TX_SLOTVLD_START_BIT))
|
|
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_0 (0)
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_0_VALUE \
|
|
(AW_PID_2032_I2S_TX_SLOTVLD_SLOT_0 << AW_PID_2032_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_1 (1)
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_1_VALUE \
|
|
(AW_PID_2032_I2S_TX_SLOTVLD_SLOT_1 << AW_PID_2032_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_2 (2)
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_2_VALUE \
|
|
(AW_PID_2032_I2S_TX_SLOTVLD_SLOT_2 << AW_PID_2032_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_3 (3)
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_3_VALUE \
|
|
(AW_PID_2032_I2S_TX_SLOTVLD_SLOT_3 << AW_PID_2032_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_4 (4)
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_4_VALUE \
|
|
(AW_PID_2032_I2S_TX_SLOTVLD_SLOT_4 << AW_PID_2032_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_5 (5)
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_5_VALUE \
|
|
(AW_PID_2032_I2S_TX_SLOTVLD_SLOT_5 << AW_PID_2032_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_6 (6)
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_6_VALUE \
|
|
(AW_PID_2032_I2S_TX_SLOTVLD_SLOT_6 << AW_PID_2032_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_7 (7)
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_SLOT_7_VALUE \
|
|
(AW_PID_2032_I2S_TX_SLOTVLD_SLOT_7 << AW_PID_2032_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_I2S_TX_SLOTVLD_DEFAULT \
|
|
(AW_PID_2032_I2S_TX_SLOTVLD_DEFAULT_VALUE << AW_PID_2032_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
/* I2S_RXL_SLOTVLD bit 11:8 (I2SCFG1 0x07) */
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_START_BIT (8)
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_BITS_LEN (4)
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_MASK \
|
|
(~(((1<<AW_PID_2032_I2S_RXL_SLOTVLD_BITS_LEN)-1) << AW_PID_2032_I2S_RXL_SLOTVLD_START_BIT))
|
|
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_0 (0)
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_0_VALUE \
|
|
(AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_0 << AW_PID_2032_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_1 (1)
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_1_VALUE \
|
|
(AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_1 << AW_PID_2032_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_2 (2)
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_2_VALUE \
|
|
(AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_2 << AW_PID_2032_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_3 (3)
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_3_VALUE \
|
|
(AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_3 << AW_PID_2032_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_4 (4)
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_4_VALUE \
|
|
(AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_4 << AW_PID_2032_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_5 (5)
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_5_VALUE \
|
|
(AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_5 << AW_PID_2032_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_6 (6)
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_6_VALUE \
|
|
(AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_6 << AW_PID_2032_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_7 (7)
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_7_VALUE \
|
|
(AW_PID_2032_I2S_RXL_SLOTVLD_SLOT_7 << AW_PID_2032_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_I2S_RXL_SLOTVLD_DEFAULT \
|
|
(AW_PID_2032_I2S_RXL_SLOTVLD_DEFAULT_VALUE << AW_PID_2032_I2S_RXL_SLOTVLD_START_BIT)
|
|
|
|
/* CFSEL bit 7:6 (I2SCFG1 0x07) */
|
|
#define AW_PID_2032_CFSEL_START_BIT (6)
|
|
#define AW_PID_2032_CFSEL_BITS_LEN (2)
|
|
#define AW_PID_2032_CFSEL_MASK \
|
|
(~(((1<<AW_PID_2032_CFSEL_BITS_LEN)-1) << AW_PID_2032_CFSEL_START_BIT))
|
|
|
|
#define AW_PID_2032_CFSEL_HAGC (0)
|
|
#define AW_PID_2032_CFSEL_HAGC_VALUE \
|
|
(AW_PID_2032_CFSEL_HAGC << AW_PID_2032_CFSEL_START_BIT)
|
|
|
|
#define AW_PID_2032_CFSEL_IV_TXDOUT (1)
|
|
#define AW_PID_2032_CFSEL_IV_TXDOUT_VALUE \
|
|
(AW_PID_2032_CFSEL_IV_TXDOUT << AW_PID_2032_CFSEL_START_BIT)
|
|
|
|
#define AW_PID_2032_CFSEL_IVBT_TXDOUT (2)
|
|
#define AW_PID_2032_CFSEL_IVBT_TXDOUT_VALUE \
|
|
(AW_PID_2032_CFSEL_IVBT_TXDOUT << AW_PID_2032_CFSEL_START_BIT)
|
|
|
|
#define AW_PID_2032_CFSEL_RESERVED_FOR_IV_TXDOUT (3)
|
|
#define AW_PID_2032_CFSEL_RESERVED_FOR_IV_TXDOUT_VALUE \
|
|
(AW_PID_2032_CFSEL_RESERVED_FOR_IV_TXDOUT << AW_PID_2032_CFSEL_START_BIT)
|
|
|
|
#define AW_PID_2032_CFSEL_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_CFSEL_DEFAULT \
|
|
(AW_PID_2032_CFSEL_DEFAULT_VALUE << AW_PID_2032_CFSEL_START_BIT)
|
|
|
|
/* DRVSTREN bit 5 (I2SCFG1 0x07) */
|
|
#define AW_PID_2032_DRVSTREN_START_BIT (5)
|
|
#define AW_PID_2032_DRVSTREN_BITS_LEN (1)
|
|
#define AW_PID_2032_DRVSTREN_MASK \
|
|
(~(((1<<AW_PID_2032_DRVSTREN_BITS_LEN)-1) << AW_PID_2032_DRVSTREN_START_BIT))
|
|
|
|
#define AW_PID_2032_DRVSTREN_2MA (0)
|
|
#define AW_PID_2032_DRVSTREN_2MA_VALUE \
|
|
(AW_PID_2032_DRVSTREN_2MA << AW_PID_2032_DRVSTREN_START_BIT)
|
|
|
|
#define AW_PID_2032_DRVSTREN_8MA (1)
|
|
#define AW_PID_2032_DRVSTREN_8MA_VALUE \
|
|
(AW_PID_2032_DRVSTREN_8MA << AW_PID_2032_DRVSTREN_START_BIT)
|
|
|
|
#define AW_PID_2032_DRVSTREN_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_DRVSTREN_DEFAULT \
|
|
(AW_PID_2032_DRVSTREN_DEFAULT_VALUE << AW_PID_2032_DRVSTREN_START_BIT)
|
|
|
|
/* DOHZ bit 4 (I2SCFG1 0x07) */
|
|
#define AW_PID_2032_DOHZ_START_BIT (4)
|
|
#define AW_PID_2032_DOHZ_BITS_LEN (1)
|
|
#define AW_PID_2032_DOHZ_MASK \
|
|
(~(((1<<AW_PID_2032_DOHZ_BITS_LEN)-1) << AW_PID_2032_DOHZ_START_BIT))
|
|
|
|
#define AW_PID_2032_DOHZ_ALL (0)
|
|
#define AW_PID_2032_DOHZ_ALL_VALUE \
|
|
(AW_PID_2032_DOHZ_ALL << AW_PID_2032_DOHZ_START_BIT)
|
|
|
|
#define AW_PID_2032_DOHZ_HIZ (1)
|
|
#define AW_PID_2032_DOHZ_HIZ_VALUE \
|
|
(AW_PID_2032_DOHZ_HIZ << AW_PID_2032_DOHZ_START_BIT)
|
|
|
|
#define AW_PID_2032_DOHZ_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_DOHZ_DEFAULT \
|
|
(AW_PID_2032_DOHZ_DEFAULT_VALUE << AW_PID_2032_DOHZ_START_BIT)
|
|
|
|
/* FSYNC_TYPE bit 3 (I2SCFG1 0x07) */
|
|
#define AW_PID_2032_FSYNC_TYPE_START_BIT (3)
|
|
#define AW_PID_2032_FSYNC_TYPE_BITS_LEN (1)
|
|
#define AW_PID_2032_FSYNC_TYPE_MASK \
|
|
(~(((1<<AW_PID_2032_FSYNC_TYPE_BITS_LEN)-1) << AW_PID_2032_FSYNC_TYPE_START_BIT))
|
|
|
|
#define AW_PID_2032_FSYNC_TYPE_ONEMINUS_SLOT (0)
|
|
#define AW_PID_2032_FSYNC_TYPE_ONEMINUS_SLOT_VALUE \
|
|
(AW_PID_2032_FSYNC_TYPE_ONEMINUS_SLOT << AW_PID_2032_FSYNC_TYPE_START_BIT)
|
|
|
|
#define AW_PID_2032_FSYNC_TYPE_ONEMINUS_BCK (1)
|
|
#define AW_PID_2032_FSYNC_TYPE_ONEMINUS_BCK_VALUE \
|
|
(AW_PID_2032_FSYNC_TYPE_ONEMINUS_BCK << AW_PID_2032_FSYNC_TYPE_START_BIT)
|
|
|
|
#define AW_PID_2032_FSYNC_TYPE_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_FSYNC_TYPE_DEFAULT \
|
|
(AW_PID_2032_FSYNC_TYPE_DEFAULT_VALUE << AW_PID_2032_FSYNC_TYPE_START_BIT)
|
|
|
|
/* I2SDOSEL bit 2 (I2SCFG1 0x07) */
|
|
#define AW_PID_2032_I2SDOSEL_START_BIT (2)
|
|
#define AW_PID_2032_I2SDOSEL_BITS_LEN (1)
|
|
#define AW_PID_2032_I2SDOSEL_MASK \
|
|
(~(((1<<AW_PID_2032_I2SDOSEL_BITS_LEN)-1) << AW_PID_2032_I2SDOSEL_START_BIT))
|
|
|
|
#define AW_PID_2032_I2SDOSEL_0 (0)
|
|
#define AW_PID_2032_I2SDOSEL_0_VALUE \
|
|
(AW_PID_2032_I2SDOSEL_0 << AW_PID_2032_I2SDOSEL_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SDOSEL_NORMAL_DATA (1)
|
|
#define AW_PID_2032_I2SDOSEL_NORMAL_DATA_VALUE \
|
|
(AW_PID_2032_I2SDOSEL_NORMAL_DATA << AW_PID_2032_I2SDOSEL_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SDOSEL_DEFAULT_VALUE (1)
|
|
#define AW_PID_2032_I2SDOSEL_DEFAULT \
|
|
(AW_PID_2032_I2SDOSEL_DEFAULT_VALUE << AW_PID_2032_I2SDOSEL_START_BIT)
|
|
|
|
/* I2SCHS bit 1 (I2SCFG1 0x07) */
|
|
#define AW_PID_2032_I2SCHS_START_BIT (1)
|
|
#define AW_PID_2032_I2SCHS_BITS_LEN (1)
|
|
#define AW_PID_2032_I2SCHS_MASK \
|
|
(~(((1<<AW_PID_2032_I2SCHS_BITS_LEN)-1) << AW_PID_2032_I2SCHS_START_BIT))
|
|
|
|
#define AW_PID_2032_I2SCHS_LEFT (0)
|
|
#define AW_PID_2032_I2SCHS_LEFT_VALUE \
|
|
(AW_PID_2032_I2SCHS_LEFT << AW_PID_2032_I2SCHS_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SCHS_RIGHT (1)
|
|
#define AW_PID_2032_I2SCHS_RIGHT_VALUE \
|
|
(AW_PID_2032_I2SCHS_RIGHT << AW_PID_2032_I2SCHS_START_BIT)
|
|
|
|
#define AW_PID_2032_I2SCHS_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_I2SCHS_DEFAULT \
|
|
(AW_PID_2032_I2SCHS_DEFAULT_VALUE << AW_PID_2032_I2SCHS_START_BIT)
|
|
|
|
/* I2STXEN bit 0 (I2SCFG1 0x07) */
|
|
#define AW_PID_2032_I2STXEN_START_BIT (0)
|
|
#define AW_PID_2032_I2STXEN_BITS_LEN (1)
|
|
#define AW_PID_2032_I2STXEN_MASK \
|
|
(~(((1<<AW_PID_2032_I2STXEN_BITS_LEN)-1) << AW_PID_2032_I2STXEN_START_BIT))
|
|
|
|
#define AW_PID_2032_I2STXEN_DISABLE (0)
|
|
#define AW_PID_2032_I2STXEN_DISABLE_VALUE \
|
|
(AW_PID_2032_I2STXEN_DISABLE << AW_PID_2032_I2STXEN_START_BIT)
|
|
|
|
#define AW_PID_2032_I2STXEN_ENABLE (1)
|
|
#define AW_PID_2032_I2STXEN_ENABLE_VALUE \
|
|
(AW_PID_2032_I2STXEN_ENABLE << AW_PID_2032_I2STXEN_START_BIT)
|
|
|
|
#define AW_PID_2032_I2STXEN_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_I2STXEN_DEFAULT \
|
|
(AW_PID_2032_I2STXEN_DEFAULT_VALUE << AW_PID_2032_I2STXEN_START_BIT)
|
|
|
|
/* default value of I2SCFG1 (0x07) */
|
|
/* #define AW_PID_2032_I2SCFG1_DEFAULT (0x0034) */
|
|
|
|
/* HAGCCFG1 (0x09) detail */
|
|
/* RVTH bit 15:8 (HAGCCFG1 0x09) */
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#define AW_PID_2032_RVTH_START_BIT (8)
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#define AW_PID_2032_RVTH_BITS_LEN (8)
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#define AW_PID_2032_RVTH_MASK \
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(~(((1<<AW_PID_2032_RVTH_BITS_LEN)-1) << AW_PID_2032_RVTH_START_BIT))
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#define AW_PID_2032_RVTH_DEFAULT_VALUE (0x39)
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#define AW_PID_2032_RVTH_DEFAULT \
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(AW_PID_2032_RVTH_DEFAULT_VALUE << AW_PID_2032_RVTH_START_BIT)
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/* AVTH bit 7:0 (HAGCCFG1 0x09) */
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#define AW_PID_2032_AVTH_START_BIT (0)
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#define AW_PID_2032_AVTH_BITS_LEN (8)
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#define AW_PID_2032_AVTH_MASK \
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(~(((1<<AW_PID_2032_AVTH_BITS_LEN)-1) << AW_PID_2032_AVTH_START_BIT))
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#define AW_PID_2032_AVTH_DEFAULT_VALUE (0x40)
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#define AW_PID_2032_AVTH_DEFAULT \
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(AW_PID_2032_AVTH_DEFAULT_VALUE << AW_PID_2032_AVTH_START_BIT)
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/* default value of HAGCCFG1 (0x09) */
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/* #define AW_PID_2032_HAGCCFG1_DEFAULT (0x3940) */
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/* HAGCCFG2 (0x0A) detail */
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/* ATTH bit 15:0 (HAGCCFG2 0x0A) */
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#define AW_PID_2032_ATTH_START_BIT (0)
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#define AW_PID_2032_ATTH_BITS_LEN (16)
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#define AW_PID_2032_ATTH_MASK \
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(~(((1<<AW_PID_2032_ATTH_BITS_LEN)-1) << AW_PID_2032_ATTH_START_BIT))
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#define AW_PID_2032_ATTH_RESERVED (0)
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#define AW_PID_2032_ATTH_RESERVED_VALUE \
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(AW_PID_2032_ATTH_RESERVED << AW_PID_2032_ATTH_START_BIT)
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#define AW_PID_2032_ATTH_DEFAULT_VALUE (0x0030)
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#define AW_PID_2032_ATTH_DEFAULT \
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(AW_PID_2032_ATTH_DEFAULT_VALUE << AW_PID_2032_ATTH_START_BIT)
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/* default value of HAGCCFG2 (0x0A) */
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/* #define AW_PID_2032_HAGCCFG2_DEFAULT (0x0030) */
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/* HAGCCFG3 (0x0B) detail */
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/* RTTH bit 15:0 (HAGCCFG3 0x0B) */
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#define AW_PID_2032_RTTH_START_BIT (0)
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#define AW_PID_2032_RTTH_BITS_LEN (16)
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#define AW_PID_2032_RTTH_MASK \
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(~(((1<<AW_PID_2032_RTTH_BITS_LEN)-1) << AW_PID_2032_RTTH_START_BIT))
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#define AW_PID_2032_RTTH_RESERVED (0)
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#define AW_PID_2032_RTTH_RESERVED_VALUE \
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(AW_PID_2032_RTTH_RESERVED << AW_PID_2032_RTTH_START_BIT)
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#define AW_PID_2032_RTTH_DEFAULT_VALUE (0x01E0)
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#define AW_PID_2032_RTTH_DEFAULT \
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(AW_PID_2032_RTTH_DEFAULT_VALUE << AW_PID_2032_RTTH_START_BIT)
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/* default value of HAGCCFG3 (0x0B) */
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/* #define AW_PID_2032_HAGCCFG3_DEFAULT (0x01E0) */
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/* HAGCCFG4 (0x0C) detail */
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/* HOLDTH bit 7:0 (HAGCCFG4 0x0C) */
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#define AW_PID_2032_HOLDTH_START_BIT (0)
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#define AW_PID_2032_HOLDTH_BITS_LEN (8)
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#define AW_PID_2032_HOLDTH_MASK \
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(~(((1<<AW_PID_2032_HOLDTH_BITS_LEN)-1) << AW_PID_2032_HOLDTH_START_BIT))
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#define AW_PID_2032_HOLDTH_RESERVED (0)
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#define AW_PID_2032_HOLDTH_RESERVED_VALUE \
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(AW_PID_2032_HOLDTH_RESERVED << AW_PID_2032_HOLDTH_START_BIT)
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#define AW_PID_2032_HOLDTH_DEFAULT_VALUE (0x64)
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#define AW_PID_2032_HOLDTH_DEFAULT \
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(AW_PID_2032_HOLDTH_DEFAULT_VALUE << AW_PID_2032_HOLDTH_START_BIT)
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/* default value of HAGCCFG4 (0x0C) */
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/* #define AW_PID_2032_HAGCCFG4_DEFAULT (0x0064) */
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/* HAGCST (0x10) detail */
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/* SPK_GAIN_ST bit 10:8 (HAGCST 0x10) */
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#define AW_PID_2032_SPK_GAIN_ST_START_BIT (8)
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#define AW_PID_2032_SPK_GAIN_ST_BITS_LEN (3)
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#define AW_PID_2032_SPK_GAIN_ST_MASK \
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(~(((1<<AW_PID_2032_SPK_GAIN_ST_BITS_LEN)-1) << AW_PID_2032_SPK_GAIN_ST_START_BIT))
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#define AW_PID_2032_SPK_GAIN_ST_7 (0)
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#define AW_PID_2032_SPK_GAIN_ST_7_VALUE \
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(AW_PID_2032_SPK_GAIN_ST_7 << AW_PID_2032_SPK_GAIN_ST_START_BIT)
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#define AW_PID_2032_SPK_GAIN_ST_8 (1)
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#define AW_PID_2032_SPK_GAIN_ST_8_VALUE \
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(AW_PID_2032_SPK_GAIN_ST_8 << AW_PID_2032_SPK_GAIN_ST_START_BIT)
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#define AW_PID_2032_SPK_GAIN_ST_10 (2)
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#define AW_PID_2032_SPK_GAIN_ST_10_VALUE \
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(AW_PID_2032_SPK_GAIN_ST_10 << AW_PID_2032_SPK_GAIN_ST_START_BIT)
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#define AW_PID_2032_SPK_GAIN_ST_14 (3)
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#define AW_PID_2032_SPK_GAIN_ST_14_VALUE \
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(AW_PID_2032_SPK_GAIN_ST_14 << AW_PID_2032_SPK_GAIN_ST_START_BIT)
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#define AW_PID_2032_SPK_GAIN_ST_16 (4)
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#define AW_PID_2032_SPK_GAIN_ST_16_VALUE \
|
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(AW_PID_2032_SPK_GAIN_ST_16 << AW_PID_2032_SPK_GAIN_ST_START_BIT)
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#define AW_PID_2032_SPK_GAIN_ST_20 (5)
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#define AW_PID_2032_SPK_GAIN_ST_20_VALUE \
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(AW_PID_2032_SPK_GAIN_ST_20 << AW_PID_2032_SPK_GAIN_ST_START_BIT)
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#define AW_PID_2032_SPK_GAIN_ST_DEFAULT_VALUE (0x4)
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#define AW_PID_2032_SPK_GAIN_ST_DEFAULT \
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(AW_PID_2032_SPK_GAIN_ST_DEFAULT_VALUE << AW_PID_2032_SPK_GAIN_ST_START_BIT)
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/* BSTVOUT_ST bit 5:0 (HAGCST 0x10) */
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#define AW_PID_2032_BSTVOUT_ST_START_BIT (0)
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#define AW_PID_2032_BSTVOUT_ST_BITS_LEN (6)
|
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#define AW_PID_2032_BSTVOUT_ST_MASK \
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(~(((1<<AW_PID_2032_BSTVOUT_ST_BITS_LEN)-1) << AW_PID_2032_BSTVOUT_ST_START_BIT))
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#define AW_PID_2032_BSTVOUT_ST_5P0V (15)
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#define AW_PID_2032_BSTVOUT_ST_5P0V_VALUE \
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(AW_PID_2032_BSTVOUT_ST_5P0V << AW_PID_2032_BSTVOUT_ST_START_BIT)
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#define AW_PID_2032_BSTVOUT_ST_10P25V (57)
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#define AW_PID_2032_BSTVOUT_ST_10P25V_VALUE \
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(AW_PID_2032_BSTVOUT_ST_10P25V << AW_PID_2032_BSTVOUT_ST_START_BIT)
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#define AW_PID_2032_BSTVOUT_ST_DEFAULT_VALUE (0)
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#define AW_PID_2032_BSTVOUT_ST_DEFAULT \
|
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(AW_PID_2032_BSTVOUT_ST_DEFAULT_VALUE << AW_PID_2032_BSTVOUT_ST_START_BIT)
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|
|
|
/* default value of HAGCST (0x10) */
|
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/* #define AW_PID_2032_HAGCST_DEFAULT (0x0400) */
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|
|
|
/* VBAT (0x12) detail */
|
|
/* VBAT_DET bit 9:0 (VBAT 0x12) */
|
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#define AW_PID_2032_VBAT_DET_START_BIT (0)
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#define AW_PID_2032_VBAT_DET_BITS_LEN (10)
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#define AW_PID_2032_VBAT_DET_MASK \
|
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(~(((1<<AW_PID_2032_VBAT_DET_BITS_LEN)-1) << AW_PID_2032_VBAT_DET_START_BIT))
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|
|
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#define AW_PID_2032_VBAT_DET_DEFAULT_VALUE (0x263)
|
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#define AW_PID_2032_VBAT_DET_DEFAULT \
|
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(AW_PID_2032_VBAT_DET_DEFAULT_VALUE << AW_PID_2032_VBAT_DET_START_BIT)
|
|
|
|
/* default value of VBAT (0x12) */
|
|
/* #define AW_PID_2032_VBAT_DEFAULT (0x0263) */
|
|
|
|
/* TEMP (0x13) detail */
|
|
/* TEMP_DET bit 9:0 (TEMP 0x13) */
|
|
#define AW_PID_2032_TEMP_DET_START_BIT (0)
|
|
#define AW_PID_2032_TEMP_DET_BITS_LEN (10)
|
|
#define AW_PID_2032_TEMP_DET_MASK \
|
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(~(((1<<AW_PID_2032_TEMP_DET_BITS_LEN)-1) << AW_PID_2032_TEMP_DET_START_BIT))
|
|
|
|
#define AW_PID_2032_TEMP_DET_MINUS_40_DEGREE (0x3D8)
|
|
#define AW_PID_2032_TEMP_DET_MINUS_40_DEGREE_VALUE \
|
|
(AW_PID_2032_TEMP_DET_MINUS_40_DEGREE << AW_PID_2032_TEMP_DET_START_BIT)
|
|
|
|
#define AW_PID_2032_TEMP_DET_0_DEGREE (0x00)
|
|
#define AW_PID_2032_TEMP_DET_0_DEGREE_VALUE \
|
|
(AW_PID_2032_TEMP_DET_0_DEGREE << AW_PID_2032_TEMP_DET_START_BIT)
|
|
|
|
#define AW_PID_2032_TEMP_DET_1_DEGREE (0x01)
|
|
#define AW_PID_2032_TEMP_DET_1_DEGREE_VALUE \
|
|
(AW_PID_2032_TEMP_DET_1_DEGREE << AW_PID_2032_TEMP_DET_START_BIT)
|
|
|
|
#define AW_PID_2032_TEMP_DET_25_DEGREE (0x19)
|
|
#define AW_PID_2032_TEMP_DET_25_DEGREE_VALUE \
|
|
(AW_PID_2032_TEMP_DET_25_DEGREE << AW_PID_2032_TEMP_DET_START_BIT)
|
|
|
|
#define AW_PID_2032_TEMP_DET_55_DEGREE (0x37)
|
|
#define AW_PID_2032_TEMP_DET_55_DEGREE_VALUE \
|
|
(AW_PID_2032_TEMP_DET_55_DEGREE << AW_PID_2032_TEMP_DET_START_BIT)
|
|
|
|
#define AW_PID_2032_TEMP_DET_DEFAULT_VALUE (0x019)
|
|
#define AW_PID_2032_TEMP_DET_DEFAULT \
|
|
(AW_PID_2032_TEMP_DET_DEFAULT_VALUE << AW_PID_2032_TEMP_DET_START_BIT)
|
|
|
|
/* default value of TEMP (0x13) */
|
|
/* #define AW_PID_2032_TEMP_DEFAULT (0x0019) */
|
|
|
|
/* PVDD (0x14) detail */
|
|
/* PVDD_DET bit 9:0 (PVDD 0x14) */
|
|
#define AW_PID_2032_PVDD_DET_START_BIT (0)
|
|
#define AW_PID_2032_PVDD_DET_BITS_LEN (10)
|
|
#define AW_PID_2032_PVDD_DET_MASK \
|
|
(~(((1<<AW_PID_2032_PVDD_DET_BITS_LEN)-1) << AW_PID_2032_PVDD_DET_START_BIT))
|
|
|
|
#define AW_PID_2032_PVDD_DET_DEFAULT_VALUE (0x263)
|
|
#define AW_PID_2032_PVDD_DET_DEFAULT \
|
|
(AW_PID_2032_PVDD_DET_DEFAULT_VALUE << AW_PID_2032_PVDD_DET_START_BIT)
|
|
|
|
/* default value of PVDD (0x14) */
|
|
/* #define AW_PID_2032_PVDD_DEFAULT (0x0263) */
|
|
|
|
/* BSTCTRL1 (0x60) detail */
|
|
/* BST_RTH bit 13:8 (BSTCTRL1 0x60) */
|
|
#define AW_PID_2032_BST_RTH_START_BIT (8)
|
|
#define AW_PID_2032_BST_RTH_BITS_LEN (6)
|
|
#define AW_PID_2032_BST_RTH_MASK \
|
|
(~(((1<<AW_PID_2032_BST_RTH_BITS_LEN)-1) << AW_PID_2032_BST_RTH_START_BIT))
|
|
|
|
#define AW_PID_2032_BST_RTH_DEFAULT_VALUE (4)
|
|
#define AW_PID_2032_BST_RTH_DEFAULT \
|
|
(AW_PID_2032_BST_RTH_DEFAULT_VALUE << AW_PID_2032_BST_RTH_START_BIT)
|
|
|
|
/* BST_ATH bit 5:0 (BSTCTRL1 0x60) */
|
|
#define AW_PID_2032_BST_ATH_START_BIT (0)
|
|
#define AW_PID_2032_BST_ATH_BITS_LEN (6)
|
|
#define AW_PID_2032_BST_ATH_MASK \
|
|
(~(((1<<AW_PID_2032_BST_ATH_BITS_LEN)-1) << AW_PID_2032_BST_ATH_START_BIT))
|
|
|
|
#define AW_PID_2032_BST_ATH_DEFAULT_VALUE (2)
|
|
#define AW_PID_2032_BST_ATH_DEFAULT \
|
|
(AW_PID_2032_BST_ATH_DEFAULT_VALUE << AW_PID_2032_BST_ATH_START_BIT)
|
|
|
|
/* default value of BSTCTRL1 (0x60) */
|
|
/* #define AW_PID_2032_BSTCTRL1_DEFAULT (0x0402) */
|
|
|
|
/* BSTCTRL2 (0x61) detail */
|
|
/* VOUT_CTMD bit 15 (BSTCTRL2 0x61) */
|
|
#define AW_PID_2032_VOUT_CTMD_START_BIT (15)
|
|
#define AW_PID_2032_VOUT_CTMD_BITS_LEN (1)
|
|
#define AW_PID_2032_VOUT_CTMD_MASK \
|
|
(~(((1<<AW_PID_2032_VOUT_CTMD_BITS_LEN)-1) << AW_PID_2032_VOUT_CTMD_START_BIT))
|
|
|
|
#define AW_PID_2032_VOUT_CTMD_VREF (0)
|
|
#define AW_PID_2032_VOUT_CTMD_VREF_VALUE \
|
|
(AW_PID_2032_VOUT_CTMD_VREF << AW_PID_2032_VOUT_CTMD_START_BIT)
|
|
|
|
#define AW_PID_2032_VOUT_CTMD_VFB (1)
|
|
#define AW_PID_2032_VOUT_CTMD_VFB_VALUE \
|
|
(AW_PID_2032_VOUT_CTMD_VFB << AW_PID_2032_VOUT_CTMD_START_BIT)
|
|
|
|
#define AW_PID_2032_VOUT_CTMD_DEFAULT_VALUE (0)
|
|
#define AW_PID_2032_VOUT_CTMD_DEFAULT \
|
|
(AW_PID_2032_VOUT_CTMD_DEFAULT_VALUE << AW_PID_2032_VOUT_CTMD_START_BIT)
|
|
|
|
/* BST_MODE bit 14:13 (BSTCTRL2 0x61) */
|
|
#define AW_PID_2032_BST_MODE_START_BIT (13)
|
|
#define AW_PID_2032_BST_MODE_BITS_LEN (2)
|
|
#define AW_PID_2032_BST_MODE_MASK \
|
|
(~(((1<<AW_PID_2032_BST_MODE_BITS_LEN)-1) << AW_PID_2032_BST_MODE_START_BIT))
|
|
|
|
#define AW_PID_2032_BST_MODE_TRANSPARENT (0)
|
|
#define AW_PID_2032_BST_MODE_TRANSPARENT_VALUE \
|
|
(AW_PID_2032_BST_MODE_TRANSPARENT << AW_PID_2032_BST_MODE_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_MODE_FORCE_BOOST (1)
|
|
#define AW_PID_2032_BST_MODE_FORCE_BOOST_VALUE \
|
|
(AW_PID_2032_BST_MODE_FORCE_BOOST << AW_PID_2032_BST_MODE_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_MODE_SMART_BOOST1 (2)
|
|
#define AW_PID_2032_BST_MODE_SMART_BOOST1_VALUE \
|
|
(AW_PID_2032_BST_MODE_SMART_BOOST1 << AW_PID_2032_BST_MODE_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_MODE_SMART_BOOST2 (3)
|
|
#define AW_PID_2032_BST_MODE_SMART_BOOST2_VALUE \
|
|
(AW_PID_2032_BST_MODE_SMART_BOOST2 << AW_PID_2032_BST_MODE_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_MODE_DEFAULT_VALUE (0x3)
|
|
#define AW_PID_2032_BST_MODE_DEFAULT \
|
|
(AW_PID_2032_BST_MODE_DEFAULT_VALUE << AW_PID_2032_BST_MODE_START_BIT)
|
|
|
|
/* BST_TDEG bit 11:8 (BSTCTRL2 0x61) */
|
|
#define AW_PID_2032_BST_TDEG_START_BIT (8)
|
|
#define AW_PID_2032_BST_TDEG_BITS_LEN (4)
|
|
#define AW_PID_2032_BST_TDEG_MASK \
|
|
(~(((1<<AW_PID_2032_BST_TDEG_BITS_LEN)-1) << AW_PID_2032_BST_TDEG_START_BIT))
|
|
|
|
#define AW_PID_2032_BST_TDEG_0P50_MS (0)
|
|
#define AW_PID_2032_BST_TDEG_0P50_MS_VALUE \
|
|
(AW_PID_2032_BST_TDEG_0P50_MS << AW_PID_2032_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_TDEG_1P00_MS (1)
|
|
#define AW_PID_2032_BST_TDEG_1P00_MS_VALUE \
|
|
(AW_PID_2032_BST_TDEG_1P00_MS << AW_PID_2032_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_TDEG_2P00_MS (2)
|
|
#define AW_PID_2032_BST_TDEG_2P00_MS_VALUE \
|
|
(AW_PID_2032_BST_TDEG_2P00_MS << AW_PID_2032_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_TDEG_4P00_MS (3)
|
|
#define AW_PID_2032_BST_TDEG_4P00_MS_VALUE \
|
|
(AW_PID_2032_BST_TDEG_4P00_MS << AW_PID_2032_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_TDEG_8P00_MS (4)
|
|
#define AW_PID_2032_BST_TDEG_8P00_MS_VALUE \
|
|
(AW_PID_2032_BST_TDEG_8P00_MS << AW_PID_2032_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_TDEG_10P7_MS (5)
|
|
#define AW_PID_2032_BST_TDEG_10P7_MS_VALUE \
|
|
(AW_PID_2032_BST_TDEG_10P7_MS << AW_PID_2032_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_TDEG_13P3_MS (6)
|
|
#define AW_PID_2032_BST_TDEG_13P3_MS_VALUE \
|
|
(AW_PID_2032_BST_TDEG_13P3_MS << AW_PID_2032_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_TDEG_16P0_MS (7)
|
|
#define AW_PID_2032_BST_TDEG_16P0_MS_VALUE \
|
|
(AW_PID_2032_BST_TDEG_16P0_MS << AW_PID_2032_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_TDEG_18P6_MS (8)
|
|
#define AW_PID_2032_BST_TDEG_18P6_MS_VALUE \
|
|
(AW_PID_2032_BST_TDEG_18P6_MS << AW_PID_2032_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_TDEG_21P3_MS (9)
|
|
#define AW_PID_2032_BST_TDEG_21P3_MS_VALUE \
|
|
(AW_PID_2032_BST_TDEG_21P3_MS << AW_PID_2032_BST_TDEG_START_BIT)
|
|
|
|
#define AW_PID_2032_BST_TDEG_24P0_MS (10)
|
|
#define AW_PID_2032_BST_TDEG_24P0_MS_VALUE \
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(AW_PID_2032_BST_TDEG_24P0_MS << AW_PID_2032_BST_TDEG_START_BIT)
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#define AW_PID_2032_BST_TDEG_32P0_MS (11)
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#define AW_PID_2032_BST_TDEG_32P0_MS_VALUE \
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(AW_PID_2032_BST_TDEG_32P0_MS << AW_PID_2032_BST_TDEG_START_BIT)
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#define AW_PID_2032_BST_TDEG_64P0_MS (12)
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#define AW_PID_2032_BST_TDEG_64P0_MS_VALUE \
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(AW_PID_2032_BST_TDEG_64P0_MS << AW_PID_2032_BST_TDEG_START_BIT)
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#define AW_PID_2032_BST_TDEG_128_MS (13)
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#define AW_PID_2032_BST_TDEG_128_MS_VALUE \
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(AW_PID_2032_BST_TDEG_128_MS << AW_PID_2032_BST_TDEG_START_BIT)
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#define AW_PID_2032_BST_TDEG_256_MS (14)
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#define AW_PID_2032_BST_TDEG_256_MS_VALUE \
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(AW_PID_2032_BST_TDEG_256_MS << AW_PID_2032_BST_TDEG_START_BIT)
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#define AW_PID_2032_BST_TDEG_1200_MS (15)
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#define AW_PID_2032_BST_TDEG_1200_MS_VALUE \
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(AW_PID_2032_BST_TDEG_1200_MS << AW_PID_2032_BST_TDEG_START_BIT)
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#define AW_PID_2032_BST_TDEG_DEFAULT_VALUE (11)
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#define AW_PID_2032_BST_TDEG_DEFAULT \
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(AW_PID_2032_BST_TDEG_DEFAULT_VALUE << AW_PID_2032_BST_TDEG_START_BIT)
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/* VOUT_VFBSET bit 7:6 (BSTCTRL2 0x61) */
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#define AW_PID_2032_VOUT_VFBSET_START_BIT (6)
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#define AW_PID_2032_VOUT_VFBSET_BITS_LEN (2)
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#define AW_PID_2032_VOUT_VFBSET_MASK \
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(~(((1<<AW_PID_2032_VOUT_VFBSET_BITS_LEN)-1) << AW_PID_2032_VOUT_VFBSET_START_BIT))
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#define AW_PID_2032_VOUT_VFBSET_8P5V (0)
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#define AW_PID_2032_VOUT_VFBSET_8P5V_VALUE \
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(AW_PID_2032_VOUT_VFBSET_8P5V << AW_PID_2032_VOUT_VFBSET_START_BIT)
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#define AW_PID_2032_VOUT_VFBSET_9P5V (1)
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#define AW_PID_2032_VOUT_VFBSET_9P5V_VALUE \
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(AW_PID_2032_VOUT_VFBSET_9P5V << AW_PID_2032_VOUT_VFBSET_START_BIT)
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#define AW_PID_2032_VOUT_VFBSET_10P5V (2)
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#define AW_PID_2032_VOUT_VFBSET_10P5V_VALUE \
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(AW_PID_2032_VOUT_VFBSET_10P5V << AW_PID_2032_VOUT_VFBSET_START_BIT)
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#define AW_PID_2032_VOUT_VFBSET_DEFAULT_VALUE (1)
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#define AW_PID_2032_VOUT_VFBSET_DEFAULT \
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(AW_PID_2032_VOUT_VFBSET_DEFAULT_VALUE << AW_PID_2032_VOUT_VFBSET_START_BIT)
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/* VOUT_VREFSET bit 5:0 (BSTCTRL2 0x61) */
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#define AW_PID_2032_VOUT_VREFSET_START_BIT (0)
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#define AW_PID_2032_VOUT_VREFSET_BITS_LEN (6)
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#define AW_PID_2032_VOUT_VREFSET_MASK \
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(~(((1<<AW_PID_2032_VOUT_VREFSET_BITS_LEN)-1) << AW_PID_2032_VOUT_VREFSET_START_BIT))
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#define AW_PID_2032_VOUT_VREFSET_5P0V (15)
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#define AW_PID_2032_VOUT_VREFSET_5P0V_VALUE \
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(AW_PID_2032_VOUT_VREFSET_5P0V << AW_PID_2032_VOUT_VREFSET_START_BIT)
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#define AW_PID_2032_VOUT_VREFSET_10P25V (57)
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#define AW_PID_2032_VOUT_VREFSET_10P25V_VALUE \
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(AW_PID_2032_VOUT_VREFSET_10P25V << AW_PID_2032_VOUT_VREFSET_START_BIT)
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#define AW_PID_2032_VOUT_VREFSET_DEFAULT_VALUE (0x33)
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#define AW_PID_2032_VOUT_VREFSET_DEFAULT \
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(AW_PID_2032_VOUT_VREFSET_DEFAULT_VALUE << AW_PID_2032_VOUT_VREFSET_START_BIT)
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/* EFRH (0x78) detail */
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/* EF_VSN_GESLP bit 9:0 (EFRH 0x78) */
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#define AW_PID_2032_EF_VSN_GESLP_START_BIT (0)
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#define AW_PID_2032_EF_VSN_GESLP_BITS_LEN (10)
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#define AW_PID_2032_EF_VSN_GESLP_MASK \
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(~(((1<<AW_PID_2032_EF_VSN_GESLP_BITS_LEN)-1) << AW_PID_2032_EF_VSN_GESLP_START_BIT))
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/* EF_ISN_GESLP bit 9:0 (EFRM1 0x7A) */
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#define AW_PID_2032_EF_ISN_GESLP_START_BIT (0)
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#define AW_PID_2032_EF_ISN_GESLP_BITS_LEN (10)
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#define AW_PID_2032_EF_ISN_GESLP_MASK \
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(~(((1<<AW_PID_2032_EF_ISN_GESLP_BITS_LEN)-1) << AW_PID_2032_EF_ISN_GESLP_START_BIT))
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/* default value of BSTCTRL2 (0x61) */
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/* #define AW_PID_2032_BSTCTRL2_DEFAULT (0x6B73) */
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/* CCO_MUX bit 14 (PLLCTRL1 0x66) */
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#define AW_PID_2032_CCO_MUX_START_BIT (14)
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#define AW_PID_2032_CCO_MUX_BITS_LEN (1)
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#define AW_PID_2032_CCO_MUX_MASK \
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(~(((1<<AW_PID_2032_CCO_MUX_BITS_LEN)-1) << AW_PID_2032_CCO_MUX_START_BIT))
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#define AW_PID_2032_CCO_MUX_DIVIDED (0)
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#define AW_PID_2032_CCO_MUX_DIVIDED_VALUE \
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(AW_PID_2032_CCO_MUX_DIVIDED << AW_PID_2032_CCO_MUX_START_BIT)
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#define AW_PID_2032_CCO_MUX_BYPASS (1)
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#define AW_PID_2032_CCO_MUX_BYPASS_VALUE \
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(AW_PID_2032_CCO_MUX_BYPASS << AW_PID_2032_CCO_MUX_START_BIT)
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/* detail information of registers end */
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/********************************************
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* Volume Coefficient
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*******************************************/
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#define AW_PID_2032_VOL_STEP (6 * 8)
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/********************************************
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* Vcalb
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*******************************************/
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#define AW_PID_2032_EF_VSN_GESLP_SIGN_MASK (~0x0200)
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#define AW_PID_2032_EF_VSN_GESLP_NEG (~0xfc00)
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#define AW_PID_2032_EF_ISN_GESLP_SIGN_MASK (~0x0200)
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#define AW_PID_2032_EF_ISN_GESLP_NEG (~0xfc00)
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#define AW_PID_2032_CABL_BASE_VALUE (1000)
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#define AW_PID_2032_ICABLK_FACTOR (1)
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#define AW_PID_2032_VCABLK_FACTOR (1)
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#define AW_PID_2032_VCAL_FACTOR (1<<13)
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#define AW_PID_2032_MONITOR_VBAT_RANGE (6025)
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#define AW_PID_2032_MONITOR_INT_10BIT (1023)
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#define AW_PID_2032_MONITOR_TEMP_SIGN_MASK (~(1<<9))
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#define AW_PID_2032_MONITOR_TEMP_NEG_MASK (0XFC00)
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/********************************************
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* Dither
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*******************************************/
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#define AW_PID_2032_DITHER_START_BIT (13)
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#define AW_PID_2032_DITHER_BITS_LEN (1)
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#define AW_PID_2032_DITHER_MASK \
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(~(((1<<AW_PID_2032_DITHER_BITS_LEN)-1) << AW_PID_2032_DITHER_START_BIT))
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#define AW_PID_2032_DITHER_DISABLE (0)
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#define AW_PID_2032_DITHER_DISABLE_VALUE \
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(AW_PID_2032_DITHER_DISABLE << AW_PID_2032_DITHER_START_BIT)
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#define AW_PID_2032_DITHER_ENABLE (1)
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#define AW_PID_2032_DITHER_ENABLE_VALUE \
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(AW_PID_2032_DITHER_ENABLE << AW_PID_2032_DITHER_START_BIT)
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#endif /* #ifndef __AW_PID_2032_REG_H__ */
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