225 lines
6.1 KiB
C
225 lines
6.1 KiB
C
// SPDX-License-Identifier: ISC
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#include "mt7603.h"
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struct beacon_bc_data {
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struct mt7603_dev *dev;
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struct sk_buff_head q;
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struct sk_buff *tail[MT7603_MAX_INTERFACES];
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int count[MT7603_MAX_INTERFACES];
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};
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static void
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mt7603_mac_stuck_beacon_recovery(struct mt7603_dev *dev)
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{
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if (dev->beacon_check % 5 != 4)
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return;
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mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_EN);
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mt76_set(dev, MT_SCH_4, MT_SCH_4_RESET);
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mt76_clear(dev, MT_SCH_4, MT_SCH_4_RESET);
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mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_EN);
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mt76_set(dev, MT_WF_CFG_OFF_WOCCR, MT_WF_CFG_OFF_WOCCR_TMAC_GC_DIS);
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mt76_set(dev, MT_ARB_SCR, MT_ARB_SCR_TX_DISABLE);
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mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_TX_DISABLE);
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mt76_clear(dev, MT_WF_CFG_OFF_WOCCR, MT_WF_CFG_OFF_WOCCR_TMAC_GC_DIS);
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}
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static void
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mt7603_update_beacon_iter(void *priv, u8 *mac, struct ieee80211_vif *vif)
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{
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struct mt7603_dev *dev = (struct mt7603_dev *)priv;
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struct mt76_dev *mdev = &dev->mt76;
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struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
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struct sk_buff *skb = NULL;
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u32 om_idx = mvif->idx;
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u32 val;
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if (!(mdev->beacon_mask & BIT(mvif->idx)))
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return;
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skb = ieee80211_beacon_get(mt76_hw(dev), vif, 0);
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if (!skb)
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return;
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if (om_idx)
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om_idx |= 0x10;
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val = MT_DMA_FQCR0_BUSY | MT_DMA_FQCR0_MODE |
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FIELD_PREP(MT_DMA_FQCR0_TARGET_BSS, om_idx) |
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FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, 3) |
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FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, 8);
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spin_lock_bh(&dev->ps_lock);
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mt76_wr(dev, MT_DMA_FQCR0, val |
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FIELD_PREP(MT_DMA_FQCR0_TARGET_QID, MT_TX_HW_QUEUE_BCN));
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if (!mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 5000)) {
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dev->beacon_check = MT7603_WATCHDOG_TIMEOUT;
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goto out;
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}
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mt76_wr(dev, MT_DMA_FQCR0, val |
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FIELD_PREP(MT_DMA_FQCR0_TARGET_QID, MT_TX_HW_QUEUE_BMC));
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if (!mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 5000)) {
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dev->beacon_check = MT7603_WATCHDOG_TIMEOUT;
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goto out;
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}
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mt76_tx_queue_skb(dev, dev->mphy.q_tx[MT_TXQ_BEACON],
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MT_TXQ_BEACON, skb, &mvif->sta.wcid, NULL);
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out:
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spin_unlock_bh(&dev->ps_lock);
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}
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static void
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mt7603_add_buffered_bc(void *priv, u8 *mac, struct ieee80211_vif *vif)
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{
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struct beacon_bc_data *data = priv;
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struct mt7603_dev *dev = data->dev;
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struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
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struct ieee80211_tx_info *info;
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struct sk_buff *skb;
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if (!(dev->mt76.beacon_mask & BIT(mvif->idx)))
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return;
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skb = ieee80211_get_buffered_bc(mt76_hw(dev), vif);
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if (!skb)
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return;
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info = IEEE80211_SKB_CB(skb);
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info->control.vif = vif;
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info->flags |= IEEE80211_TX_CTL_ASSIGN_SEQ;
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mt76_skb_set_moredata(skb, true);
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__skb_queue_tail(&data->q, skb);
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data->tail[mvif->idx] = skb;
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data->count[mvif->idx]++;
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}
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void mt7603_pre_tbtt_tasklet(struct tasklet_struct *t)
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{
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struct mt7603_dev *dev = from_tasklet(dev, t, mt76.pre_tbtt_tasklet);
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struct mt76_dev *mdev = &dev->mt76;
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struct mt76_queue *q;
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struct beacon_bc_data data = {};
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struct sk_buff *skb;
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int i, nframes;
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if (mt76_hw(dev)->conf.flags & IEEE80211_CONF_OFFCHANNEL)
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return;
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data.dev = dev;
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__skb_queue_head_init(&data.q);
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/* Flush all previous CAB queue packets and beacons */
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mt76_wr(dev, MT_WF_ARB_CAB_FLUSH, GENMASK(30, 16) | BIT(0));
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mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_CAB], false);
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mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BEACON], false);
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if (dev->mphy.q_tx[MT_TXQ_BEACON]->queued > 0)
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dev->beacon_check++;
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else
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dev->beacon_check = 0;
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mt7603_mac_stuck_beacon_recovery(dev);
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q = dev->mphy.q_tx[MT_TXQ_BEACON];
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spin_lock(&q->lock);
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ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev),
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IEEE80211_IFACE_ITER_RESUME_ALL,
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mt7603_update_beacon_iter, dev);
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mt76_queue_kick(dev, q);
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spin_unlock(&q->lock);
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mt76_csa_check(mdev);
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if (mdev->csa_complete)
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return;
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q = dev->mphy.q_tx[MT_TXQ_CAB];
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do {
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nframes = skb_queue_len(&data.q);
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ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev),
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IEEE80211_IFACE_ITER_RESUME_ALL,
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mt7603_add_buffered_bc, &data);
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} while (nframes != skb_queue_len(&data.q) &&
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skb_queue_len(&data.q) < 8);
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if (skb_queue_empty(&data.q))
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return;
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for (i = 0; i < ARRAY_SIZE(data.tail); i++) {
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if (!data.tail[i])
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continue;
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mt76_skb_set_moredata(data.tail[i], false);
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}
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spin_lock(&q->lock);
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while ((skb = __skb_dequeue(&data.q)) != NULL) {
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
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struct ieee80211_vif *vif = info->control.vif;
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struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
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mt76_tx_queue_skb(dev, q, MT_TXQ_CAB, skb, &mvif->sta.wcid, NULL);
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}
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mt76_queue_kick(dev, q);
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spin_unlock(&q->lock);
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for (i = 0; i < ARRAY_SIZE(data.count); i++)
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mt76_wr(dev, MT_WF_ARB_CAB_COUNT_B0_REG(i),
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data.count[i] << MT_WF_ARB_CAB_COUNT_B0_SHIFT(i));
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mt76_wr(dev, MT_WF_ARB_CAB_START,
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MT_WF_ARB_CAB_START_BSSn(0) |
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(MT_WF_ARB_CAB_START_BSS0n(1) *
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((1 << (MT7603_MAX_INTERFACES - 1)) - 1)));
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}
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void mt7603_beacon_set_timer(struct mt7603_dev *dev, int idx, int intval)
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{
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u32 pre_tbtt = MT7603_PRE_TBTT_TIME / 64;
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if (idx >= 0) {
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if (intval)
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dev->mt76.beacon_mask |= BIT(idx);
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else
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dev->mt76.beacon_mask &= ~BIT(idx);
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}
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if (!dev->mt76.beacon_mask || (!intval && idx < 0)) {
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mt7603_irq_disable(dev, MT_INT_MAC_IRQ3);
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mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_BCNQ_OPMODE_MASK);
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mt76_wr(dev, MT_HW_INT_MASK(3), 0);
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return;
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}
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dev->mt76.beacon_int = intval;
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mt76_wr(dev, MT_TBTT,
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FIELD_PREP(MT_TBTT_PERIOD, intval) | MT_TBTT_CAL_ENABLE);
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mt76_wr(dev, MT_TBTT_TIMER_CFG, 0x99); /* start timer */
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mt76_rmw_field(dev, MT_ARB_SCR, MT_ARB_SCR_BCNQ_OPMODE_MASK,
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MT_BCNQ_OPMODE_AP);
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mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_TBTT_BCN_PRIO);
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mt76_set(dev, MT_ARB_SCR, MT_ARB_SCR_TBTT_BCAST_PRIO);
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mt76_wr(dev, MT_PRE_TBTT, pre_tbtt);
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mt76_set(dev, MT_HW_INT_MASK(3),
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MT_HW_INT3_PRE_TBTT0 | MT_HW_INT3_TBTT0);
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mt76_set(dev, MT_WF_ARB_BCN_START,
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MT_WF_ARB_BCN_START_BSSn(0) |
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((dev->mt76.beacon_mask >> 1) *
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MT_WF_ARB_BCN_START_BSS0n(1)));
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mt7603_irq_enable(dev, MT_INT_MAC_IRQ3);
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if (dev->mt76.beacon_mask & ~BIT(0))
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mt76_set(dev, MT_LPON_SBTOR(0), MT_LPON_SBTOR_SUB_BSS_EN);
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else
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mt76_clear(dev, MT_LPON_SBTOR(0), MT_LPON_SBTOR_SUB_BSS_EN);
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}
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