350 lines
8.8 KiB
C
350 lines
8.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* TI Camera Access Layer (CAL)
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*
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* Copyright (c) 2015-2020 Texas Instruments Inc.
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*
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* Authors:
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* Benoit Parrot <bparrot@ti.com>
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* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*/
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#ifndef __TI_CAL_H__
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#define __TI_CAL_H__
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#include <linux/bitfield.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/spinlock.h>
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#include <linux/videodev2.h>
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#include <linux/wait.h>
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#include <media/media-device.h>
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#include <media/v4l2-async.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-dev.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-fwnode.h>
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#include <media/v4l2-subdev.h>
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#include <media/videobuf2-v4l2.h>
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#define CAL_MODULE_NAME "cal"
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#define CAL_MAX_NUM_CONTEXT 8
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#define CAL_NUM_CSI2_PORTS 2
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/*
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* The width is limited by the size of the CAL_WR_DMA_XSIZE_j.XSIZE field,
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* expressed in multiples of 64 bits. The height is limited by the size of the
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* CAL_CSI2_CTXi_j.CTXi_LINES and CAL_WR_DMA_CTRL_j.YSIZE fields, expressed in
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* lines.
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*/
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#define CAL_MIN_WIDTH_BYTES 16
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#define CAL_MAX_WIDTH_BYTES (8192 * 8)
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#define CAL_MIN_HEIGHT_LINES 1
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#define CAL_MAX_HEIGHT_LINES 16383
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#define CAL_CAMERARX_PAD_SINK 0
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#define CAL_CAMERARX_PAD_FIRST_SOURCE 1
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#define CAL_CAMERARX_NUM_SOURCE_PADS 1
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#define CAL_CAMERARX_NUM_PADS (1 + CAL_CAMERARX_NUM_SOURCE_PADS)
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static inline bool cal_rx_pad_is_sink(u32 pad)
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{
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/* Camera RX has 1 sink pad, and N source pads */
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return pad == 0;
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}
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static inline bool cal_rx_pad_is_source(u32 pad)
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{
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/* Camera RX has 1 sink pad, and N source pads */
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return pad >= CAL_CAMERARX_PAD_FIRST_SOURCE &&
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pad <= CAL_CAMERARX_NUM_SOURCE_PADS;
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}
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struct device;
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struct device_node;
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struct resource;
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struct regmap;
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struct regmap_fied;
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/* CTRL_CORE_CAMERRX_CONTROL register field id */
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enum cal_camerarx_field {
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F_CTRLCLKEN,
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F_CAMMODE,
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F_LANEENABLE,
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F_CSI_MODE,
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F_MAX_FIELDS,
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};
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enum cal_dma_state {
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CAL_DMA_RUNNING,
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CAL_DMA_STOP_REQUESTED,
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CAL_DMA_STOP_PENDING,
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CAL_DMA_STOPPED,
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};
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struct cal_format_info {
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u32 fourcc;
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u32 code;
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/* Bits per pixel */
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u8 bpp;
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bool meta;
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};
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/* buffer for one video frame */
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struct cal_buffer {
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/* common v4l buffer stuff -- must be first */
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struct vb2_v4l2_buffer vb;
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struct list_head list;
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};
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/**
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* struct cal_dmaqueue - Queue of DMA buffers
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*/
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struct cal_dmaqueue {
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/**
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* @lock: Protects all fields in the cal_dmaqueue.
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*/
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spinlock_t lock;
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/**
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* @queue: Buffers queued to the driver and waiting for DMA processing.
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* Buffers are added to the list by the vb2 .buffer_queue() operation,
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* and move to @pending when they are scheduled for the next frame.
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*/
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struct list_head queue;
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/**
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* @pending: Buffer provided to the hardware to DMA the next frame.
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* Will move to @active at the end of the current frame.
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*/
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struct cal_buffer *pending;
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/**
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* @active: Buffer being DMA'ed to for the current frame. Will be
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* retired and given back to vb2 at the end of the current frame if
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* a @pending buffer has been scheduled to replace it.
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*/
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struct cal_buffer *active;
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/** @state: State of the DMA engine. */
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enum cal_dma_state state;
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/** @wait: Wait queue to signal a @state transition to CAL_DMA_STOPPED. */
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struct wait_queue_head wait;
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};
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struct cal_camerarx_data {
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struct {
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unsigned int lsb;
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unsigned int msb;
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} fields[F_MAX_FIELDS];
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unsigned int num_lanes;
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};
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struct cal_data {
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const struct cal_camerarx_data *camerarx;
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unsigned int num_csi2_phy;
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unsigned int flags;
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};
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/*
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* The Camera Adaptation Layer (CAL) module is paired with one or more complex
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* I/O PHYs (CAMERARX). It contains multiple instances of CSI-2, processing and
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* DMA contexts.
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*
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* The cal_dev structure represents the whole subsystem, including the CAL and
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* the CAMERARX instances. Instances of struct cal_dev are named cal through the
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* driver.
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*
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* The cal_camerarx structure represents one CAMERARX instance. Instances of
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* cal_camerarx are named phy through the driver.
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*
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* The cal_ctx structure represents the combination of one CSI-2 context, one
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* processing context and one DMA context. Instance of struct cal_ctx are named
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* ctx through the driver.
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*/
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struct cal_camerarx {
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void __iomem *base;
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struct resource *res;
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struct regmap_field *fields[F_MAX_FIELDS];
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struct cal_dev *cal;
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unsigned int instance;
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struct v4l2_fwnode_endpoint endpoint;
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struct device_node *source_ep_node;
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struct device_node *source_node;
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struct v4l2_subdev *source;
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struct v4l2_subdev subdev;
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struct media_pad pads[CAL_CAMERARX_NUM_PADS];
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struct v4l2_mbus_framefmt formats[CAL_CAMERARX_NUM_PADS];
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/* protects the vc_* fields below */
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spinlock_t vc_lock;
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u8 vc_enable_count[4];
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u16 vc_frame_number[4];
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u32 vc_sequence[4];
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/*
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* Lock for camerarx ops. Protects:
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* - formats
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* - enable_count
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*/
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struct mutex mutex;
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unsigned int enable_count;
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};
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struct cal_dev {
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struct clk *fclk;
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int irq;
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void __iomem *base;
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struct resource *res;
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struct device *dev;
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const struct cal_data *data;
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u32 revision;
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/* Control Module handle */
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struct regmap *syscon_camerrx;
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u32 syscon_camerrx_offset;
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/* Camera Core Module handle */
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struct cal_camerarx *phy[CAL_NUM_CSI2_PORTS];
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u32 num_contexts;
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struct cal_ctx *ctx[CAL_MAX_NUM_CONTEXT];
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struct media_device mdev;
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struct v4l2_device v4l2_dev;
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struct v4l2_async_notifier notifier;
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unsigned long reserved_pix_proc_mask;
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};
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/*
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* There is one cal_ctx structure for each camera core context.
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*/
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struct cal_ctx {
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struct v4l2_ctrl_handler ctrl_handler;
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struct video_device vdev;
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struct media_pad pad;
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struct cal_dev *cal;
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struct cal_camerarx *phy;
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/* v4l2_ioctl mutex */
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struct mutex mutex;
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struct cal_dmaqueue dma;
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/* video capture */
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const struct cal_format_info *fmtinfo;
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/* Used to store current pixel format */
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struct v4l2_format v_fmt;
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/* Current subdev enumerated format (legacy) */
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const struct cal_format_info **active_fmt;
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unsigned int num_active_fmt;
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struct vb2_queue vb_vidq;
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u8 dma_ctx;
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u8 cport;
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u8 csi2_ctx;
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u8 pix_proc;
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u8 vc;
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u8 datatype;
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bool use_pix_proc;
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};
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extern unsigned int cal_debug;
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extern int cal_video_nr;
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extern bool cal_mc_api;
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#define cal_dbg(level, cal, fmt, arg...) \
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do { \
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if (cal_debug >= (level)) \
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dev_printk(KERN_DEBUG, (cal)->dev, fmt, ##arg); \
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} while (0)
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#define cal_info(cal, fmt, arg...) \
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dev_info((cal)->dev, fmt, ##arg)
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#define cal_err(cal, fmt, arg...) \
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dev_err((cal)->dev, fmt, ##arg)
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#define ctx_dbg(level, ctx, fmt, arg...) \
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cal_dbg(level, (ctx)->cal, "ctx%u: " fmt, (ctx)->dma_ctx, ##arg)
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#define ctx_info(ctx, fmt, arg...) \
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cal_info((ctx)->cal, "ctx%u: " fmt, (ctx)->dma_ctx, ##arg)
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#define ctx_err(ctx, fmt, arg...) \
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cal_err((ctx)->cal, "ctx%u: " fmt, (ctx)->dma_ctx, ##arg)
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#define phy_dbg(level, phy, fmt, arg...) \
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cal_dbg(level, (phy)->cal, "phy%u: " fmt, (phy)->instance, ##arg)
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#define phy_info(phy, fmt, arg...) \
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cal_info((phy)->cal, "phy%u: " fmt, (phy)->instance, ##arg)
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#define phy_err(phy, fmt, arg...) \
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cal_err((phy)->cal, "phy%u: " fmt, (phy)->instance, ##arg)
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static inline u32 cal_read(struct cal_dev *cal, u32 offset)
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{
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return ioread32(cal->base + offset);
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}
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static inline void cal_write(struct cal_dev *cal, u32 offset, u32 val)
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{
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iowrite32(val, cal->base + offset);
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}
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static __always_inline u32 cal_read_field(struct cal_dev *cal, u32 offset, u32 mask)
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{
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return FIELD_GET(mask, cal_read(cal, offset));
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}
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static inline void cal_write_field(struct cal_dev *cal, u32 offset, u32 value,
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u32 mask)
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{
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u32 val = cal_read(cal, offset);
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val &= ~mask;
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val |= (value << __ffs(mask)) & mask;
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cal_write(cal, offset, val);
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}
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static inline void cal_set_field(u32 *valp, u32 field, u32 mask)
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{
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u32 val = *valp;
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val &= ~mask;
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val |= (field << __ffs(mask)) & mask;
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*valp = val;
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}
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extern const struct cal_format_info cal_formats[];
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extern const unsigned int cal_num_formats;
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const struct cal_format_info *cal_format_by_fourcc(u32 fourcc);
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const struct cal_format_info *cal_format_by_code(u32 code);
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void cal_quickdump_regs(struct cal_dev *cal);
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int cal_camerarx_get_remote_frame_desc(struct cal_camerarx *phy,
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struct v4l2_mbus_frame_desc *desc);
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void cal_camerarx_disable(struct cal_camerarx *phy);
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void cal_camerarx_i913_errata(struct cal_camerarx *phy);
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struct cal_camerarx *cal_camerarx_create(struct cal_dev *cal,
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unsigned int instance);
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void cal_camerarx_destroy(struct cal_camerarx *phy);
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int cal_ctx_prepare(struct cal_ctx *ctx);
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void cal_ctx_unprepare(struct cal_ctx *ctx);
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void cal_ctx_set_dma_addr(struct cal_ctx *ctx, dma_addr_t addr);
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void cal_ctx_start(struct cal_ctx *ctx);
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void cal_ctx_stop(struct cal_ctx *ctx);
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int cal_ctx_v4l2_register(struct cal_ctx *ctx);
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void cal_ctx_v4l2_unregister(struct cal_ctx *ctx);
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int cal_ctx_v4l2_init(struct cal_ctx *ctx);
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void cal_ctx_v4l2_cleanup(struct cal_ctx *ctx);
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#endif /* __TI_CAL_H__ */
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