231 lines
5.8 KiB
C
231 lines
5.8 KiB
C
/*
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* Driver for Rockchip TSP Controller
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*
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* Copyright (C) 2012-2016 Rockchip Electronics Co., Ltd.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _RK_TSP_H
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#define _RK_TSP_H
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#include <linux/types.h>
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#define _SBF(s, v) ((v) << (s))
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#define TSP_GCFG 0x0000
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#define TSOUT_ON BIT(3)
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#define PVR_ON BIT(2)
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#define PTI1_ON BIT(1)
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#define PTI0_ON BIT(0)
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#define PVR_CTRL 0x0004
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#define PVR_BURST_INCR4 _SBF(4, 0x00)
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#define PVR_BURST_INCR8 _SBF(4, 0x01)
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#define PVR_BURST_INCR16 _SBF(4, 0x02)
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#define PVR_SOURCE_NO_PID_FILTER_PTI0 _SBF(2, 0x00)
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#define PVR_SOURCE_PID_FILTER_PTI0 _SBF(2, 0x01)
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#define PVR_SOURCE_NO_PID_FILTER_PTI1 _SBF(2, 0x02)
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#define PVR_SOURCE_PID_FILTER_PTI1 _SBF(2, 0x03)
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#define PVR_STOP BIT(1)
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#define PVR_START BIT(0)
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#define PVR_LEN 0x0008
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#define PVR_ADDR 0x000c
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#define PVR_INT_STS 0x0010
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#define PVR_INT_ENA 0x0014
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#define TSOUT_CTRL 0x0018
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#define PVR_TOP_ADDR 0x001c
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#define PVR_WRITE_ADDR 0x0020
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#define PTI0_CTRL 0x0100
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#define TS_ERROR_NOT_OUTPUT _SBF(19, 0x00)
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#define TS_ERROR_SET_INDICATOR _SBF(19, 0x01)
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#define TS_ERROR_NOT_CARE _SBF(19, 0x02)
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#define TS_CLK_PHASE_SEL BIT(18)
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#define DEMUX_BURST_INCR4 _SBF(16, 0x00)
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#define DEMUX_BURST_INCR8 _SBF(16, 0x01)
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#define DEMUX_BURST_INCR16 _SBF(16, 0x02)
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#define SYNC_BYPASS BIT(15)
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#define CW_BYTEORDER BIT(14)
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#define CM_ON BIT(13)
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#define SERIAL_SYNC_VALID_MODE _SBF(11, 0x00)
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#define PARALLEL_SYNC_VALID_MODE _SBF(11, 0x01)
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#define PARALLEL_SYNC_BURST_MODE _SBF(11, 0x02)
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#define PARALLEL_NOSYNC_VALID_MODE _SBF(11, 0x03)
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#define TSI_BIT_ORDER BIT(10)
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/* 0: memory, 1: hsadc */
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#define TSI_SEL BIT(9)
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#define OUT_BYTESWAP BIT(8)
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#define IN_BYTESWAP BIT(7)
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#define SOFT_CLEAR BIT(0)
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#define PTI0_LLP_CFG 0x0104
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#define PTI0_LLP_BASE 0x0108
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#define PTI0_LLP_WRITE 0x010c
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#define PTI0_LLP_READ 0x0110
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#define PTI0_PID_STS0 0x0114
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#define PTI0_PID_STS1 0x0118
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#define PTI0_PID_STS2 0x011c
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#define PTI0_PID_STS3 0x0120
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#define PTI0_PID_INT_ENA0 0x0124
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#define PTI0_PID_INT_ENA1 0x0128
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#define PTI0_PID_INT_ENA2 0x012c
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#define PTI0_PID_INT_ENA3 0x0130
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#define PTI0_PCR_INT_STS 0x0134
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#define PTI0_PCR_INT_ENA 0x0138
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#define PTI0_PCR0_CTRL 0x013c
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#define PTI0_PCR0_H 0x015c
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#define PTI0_PCR0_L 0x0160
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#define PTI0_DMA_STS 0x019c
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#define PTI0_DMA_ENA 0x01a0
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#define PTI0_DATA_FLAG0 0x01a4
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#define PTI0_DATA_FLAG1 0x01a8
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#define PTI0_LIST_FLAG 0x01ac
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#define PTI0_DST_STS0 0x01b0
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#define PTI0_DST_STS1 0x01b4
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#define PTI0_DST_ENA0 0x01b8
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#define PTI0_DST_ENA1 0x01bc
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#define PTI0_ECW0_H 0x0200
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#define PTI0_ECW0_L 0x0204
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#define PTI0_OCW0_H 0x0208
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#define PTI0_OCW0_L 0x020c
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#define PTI0_PID0_CTRL 0x0300
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#define PTI0_PID0_BASE 0x0400
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#define PTI0_PID0_TOP 0x0404
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#define PTI0_PID0_WRITE 0x0408
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#define PTI0_PID0_READ 0x040c
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#define PTI0_LIST0_BASE 0x0800
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#define PTI0_LIST0_TOP 0x0804
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#define PTI0_LIST0_WRITE 0x0808
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#define PTI0_LIST0_READ 0x080c
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#define PTI0_PID0_CFG 0x0900
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#define PTI0_PID0_FILT_0 0x0904
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#define PTI0_PID0_FILT_1 0x0908
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#define PTI0_PID0_FILT_2 0x090c
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#define PTI0_PID0_FILT_3 0x0910
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#define MMU_DTE_ADDR 0x08800
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#define MMU_STATUS 0x08804
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#define MMU_COMMAND 0x08808
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#define MMU_PAGE_FAULT_ADDR 0x0880c
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#define MMU_ZAP_ONE_LINE 0x08810
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#define MMU_INT_RAWSTAT 0x08814
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#define MMU_INT_CLEAR 0x08818
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#define MMU_INT_MASK 0x0881c
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#define MMU_INT_STATUS 0x08820
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#define MMU_AUTO_GATING 0x08824
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#define MMU_MISS_CNT 0x08828
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#define MMU_BURST_CNT 0x0882c
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#define GRF_REG_FIELD(reg, lsb, msb) ((reg << 16) | (lsb << 8) | (msb))
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enum soc_type {
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RK312X,
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RK3228,
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RK3328,
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};
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enum grf_fields {
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TSP_IO_GROUP_SEL,
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TSP_VALID,
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TSP_FAIL,
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TSP_CLK,
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TSP_SYNCM0,
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TSP_D0,
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TSP_D1,
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TSP_D2,
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TSP_D3,
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TSP_D4,
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TSP_D5M0,
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TSP_D6M0,
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TSP_D7M0,
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TSP_SYNCM1,
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TSP_D5M1,
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TSP_D6M1,
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TSP_D7M1,
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MAX_FIELDS,
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};
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enum tsp_filter_type {
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TSP_SECTION_FILTER = 1,
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TSP_PES_FILTER = 2,
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TSP_ES_FILTER = 4,
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TSP_TS_FILTER = 8,
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};
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struct rockchip_tsp_plat_data {
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const u32 *grf_reg_fields;
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enum soc_type soc_type;
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};
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struct tsp_ctx {
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int pid;
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int index;
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uint filter_type; /*bit 0~3: section, pes, es, ts*/
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u8 *base;
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u8 *top;
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u8 *write;
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u8 *read;
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u8 *buf;
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u32 buf_len;
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dma_addr_t dma_buf;
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u8 filter_byte[TSP_DMX_FILTER_SIZE];
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u8 filter_mask[TSP_DMX_FILTER_SIZE];
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void (*get_data_callback)(const u8 *buf, size_t count, u16 pid);
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struct list_head pid_list;
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};
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struct tsp_dev {
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struct device *dev;
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void __iomem *ioaddr;
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struct regmap *grf;
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struct clk *tsp_clk;
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struct clk *tsp_aclk;
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struct clk *tsp_hclk;
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int tsp_irq;
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int serial_parallel_mode;
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struct list_head pid_list;
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/* lock for list operate */
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spinlock_t list_lock;
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int is_open;
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/* timer */
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struct timer_list timer;
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/* ts workque */
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struct work_struct ts_work;
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struct workqueue_struct *ts_queue;
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/* mutex for feed buf to dvb-core */
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struct mutex ts_mutex;
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/* section workque */
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struct work_struct sec_work;
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struct workqueue_struct *sec_queue;
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int tsp_start_descram;
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struct rockchip_tsp_channel_info channel_info[64];
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unsigned long channel_release_timeout[64];
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const struct rockchip_tsp_plat_data *pdata;
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};
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#define TSP_CMD_IO_OPEN _IO('o', 120)
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#define TSP_CMD_IO_CLOSE _IO('o', 121)
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#define TSP_CMD_SET_PCR_PID _IOW('o', 122, ca_descr_t)
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#define TSP_CMD_GET_PCR_VAL _IOR('o', 123, ca_descr_t)
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#define TSP_CMD_SET_DESCAM_PID _IOW('o', 124, ca_descr_t)
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#define TSP_CMD_SET_LIVE_STATUS _IOW('o', 125, ca_descr_t)
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#define TSP_CMD_RESET_REGS _IOW('o', 126, ca_descr_t)
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#endif
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