243 lines
5.9 KiB
C
243 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* NVIDIA Tegra Video decoder driver
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*
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* Copyright (C) 2016-2019 GRATE-DRIVER project
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*/
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#ifndef TEGRA_VDE_H
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#define TEGRA_VDE_H
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#include <linux/completion.h>
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#include <linux/dma-direction.h>
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#include <linux/iova.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/types.h>
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#include <linux/workqueue.h>
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#include <media/media-device.h>
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#include <media/videobuf2-dma-contig.h>
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#include <media/videobuf2-dma-sg.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-event.h>
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#include <media/v4l2-ioctl.h>
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#include <media/v4l2-mem2mem.h>
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#define ICMDQUE_WR 0x00
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#define CMDQUE_CONTROL 0x08
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#define INTR_STATUS 0x18
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#define BSE_INT_ENB 0x40
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#define BSE_CONFIG 0x44
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#define BSE_ICMDQUE_EMPTY BIT(3)
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#define BSE_DMA_BUSY BIT(23)
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#define BSEV_ALIGN SZ_1
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#define FRAMEID_ALIGN SZ_256
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#define SXE_BUFFER SZ_32K
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#define VDE_ATOM SZ_16
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struct clk;
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struct dma_buf;
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struct gen_pool;
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struct tegra_ctx;
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struct iommu_group;
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struct iommu_domain;
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struct reset_control;
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struct dma_buf_attachment;
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struct tegra_vde_h264_frame;
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struct tegra_vde_h264_decoder_ctx;
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struct tegra_video_frame {
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struct dma_buf_attachment *y_dmabuf_attachment;
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struct dma_buf_attachment *cb_dmabuf_attachment;
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struct dma_buf_attachment *cr_dmabuf_attachment;
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struct dma_buf_attachment *aux_dmabuf_attachment;
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dma_addr_t y_addr;
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dma_addr_t cb_addr;
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dma_addr_t cr_addr;
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dma_addr_t aux_addr;
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u32 frame_num;
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u32 flags;
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u32 luma_atoms_pitch;
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u32 chroma_atoms_pitch;
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};
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struct tegra_coded_fmt_desc {
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u32 fourcc;
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struct v4l2_frmsize_stepwise frmsize;
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unsigned int num_decoded_fmts;
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const u32 *decoded_fmts;
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int (*decode_run)(struct tegra_ctx *ctx);
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int (*decode_wait)(struct tegra_ctx *ctx);
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};
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struct tegra_vde_soc {
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bool supports_ref_pic_marking;
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const struct tegra_coded_fmt_desc *coded_fmts;
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u32 num_coded_fmts;
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};
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struct tegra_vde_bo {
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struct iova *iova;
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struct sg_table sgt;
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struct tegra_vde *vde;
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enum dma_data_direction dma_dir;
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unsigned long dma_attrs;
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dma_addr_t dma_handle;
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dma_addr_t dma_addr;
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void *dma_cookie;
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size_t size;
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};
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struct tegra_vde {
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void __iomem *sxe;
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void __iomem *bsev;
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void __iomem *mbe;
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void __iomem *ppe;
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void __iomem *mce;
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void __iomem *tfe;
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void __iomem *ppb;
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void __iomem *vdma;
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void __iomem *frameid;
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struct device *dev;
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struct mutex lock;
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struct mutex map_lock;
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struct list_head map_list;
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struct reset_control *rst;
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struct reset_control *rst_mc;
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struct gen_pool *iram_pool;
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struct completion decode_completion;
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struct clk *clk;
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struct iommu_domain *domain;
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struct iommu_group *group;
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struct iova_domain iova;
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struct iova *iova_resv_static_addresses;
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struct iova *iova_resv_last_page;
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const struct tegra_vde_soc *soc;
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struct tegra_vde_bo *secure_bo;
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dma_addr_t bitstream_data_addr;
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dma_addr_t iram_lists_addr;
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u32 *iram;
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struct v4l2_device v4l2_dev;
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struct v4l2_m2m_dev *m2m;
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struct media_device mdev;
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struct video_device vdev;
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struct mutex v4l2_lock;
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struct workqueue_struct *wq;
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struct tegra_video_frame frames[V4L2_H264_NUM_DPB_ENTRIES + 1];
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};
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int tegra_vde_alloc_bo(struct tegra_vde *vde,
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struct tegra_vde_bo **ret_bo,
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enum dma_data_direction dma_dir,
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size_t size);
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void tegra_vde_free_bo(struct tegra_vde_bo *bo);
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struct tegra_ctx_h264 {
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const struct v4l2_ctrl_h264_decode_params *decode_params;
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const struct v4l2_ctrl_h264_sps *sps;
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const struct v4l2_ctrl_h264_pps *pps;
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};
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struct tegra_ctx {
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struct tegra_vde *vde;
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struct tegra_ctx_h264 h264;
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struct work_struct work;
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struct v4l2_fh fh;
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struct v4l2_ctrl_handler hdl;
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struct v4l2_format coded_fmt;
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struct v4l2_format decoded_fmt;
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const struct tegra_coded_fmt_desc *coded_fmt_desc;
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struct v4l2_ctrl *ctrls[];
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};
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struct tegra_m2m_buffer {
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struct v4l2_m2m_buffer m2m;
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struct dma_buf_attachment *a[VB2_MAX_PLANES];
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dma_addr_t dma_base[VB2_MAX_PLANES];
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dma_addr_t dma_addr[VB2_MAX_PLANES];
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struct iova *iova[VB2_MAX_PLANES];
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struct tegra_vde_bo *aux;
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bool b_frame;
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};
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static inline struct tegra_m2m_buffer *
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vb_to_tegra_buf(struct vb2_buffer *vb)
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{
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struct v4l2_m2m_buffer *m2m = container_of(vb, struct v4l2_m2m_buffer,
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vb.vb2_buf);
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return container_of(m2m, struct tegra_m2m_buffer, m2m);
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}
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void tegra_vde_prepare_control_data(struct tegra_ctx *ctx, u32 id);
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void tegra_vde_writel(struct tegra_vde *vde, u32 value, void __iomem *base,
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u32 offset);
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u32 tegra_vde_readl(struct tegra_vde *vde, void __iomem *base, u32 offset);
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void tegra_vde_set_bits(struct tegra_vde *vde, u32 mask, void __iomem *base,
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u32 offset);
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int tegra_vde_h264_decode_run(struct tegra_ctx *ctx);
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int tegra_vde_h264_decode_wait(struct tegra_ctx *ctx);
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int tegra_vde_iommu_init(struct tegra_vde *vde);
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void tegra_vde_iommu_deinit(struct tegra_vde *vde);
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int tegra_vde_iommu_map(struct tegra_vde *vde,
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struct sg_table *sgt,
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struct iova **iovap,
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size_t size);
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void tegra_vde_iommu_unmap(struct tegra_vde *vde, struct iova *iova);
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int tegra_vde_dmabuf_cache_map(struct tegra_vde *vde,
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struct dma_buf *dmabuf,
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enum dma_data_direction dma_dir,
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struct dma_buf_attachment **ap,
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dma_addr_t *addrp);
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void tegra_vde_dmabuf_cache_unmap(struct tegra_vde *vde,
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struct dma_buf_attachment *a,
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bool release);
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void tegra_vde_dmabuf_cache_unmap_sync(struct tegra_vde *vde);
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void tegra_vde_dmabuf_cache_unmap_all(struct tegra_vde *vde);
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static __maybe_unused char const *
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tegra_vde_reg_base_name(struct tegra_vde *vde, void __iomem *base)
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{
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if (vde->sxe == base)
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return "SXE";
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if (vde->bsev == base)
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return "BSEV";
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if (vde->mbe == base)
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return "MBE";
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if (vde->ppe == base)
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return "PPE";
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if (vde->mce == base)
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return "MCE";
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if (vde->tfe == base)
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return "TFE";
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if (vde->ppb == base)
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return "PPB";
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if (vde->vdma == base)
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return "VDMA";
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if (vde->frameid == base)
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return "FRAMEID";
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return "???";
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}
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int tegra_vde_v4l2_init(struct tegra_vde *vde);
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void tegra_vde_v4l2_deinit(struct tegra_vde *vde);
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#endif /* TEGRA_VDE_H */
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