661 lines
16 KiB
C
661 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Driver for Cadence MIPI-CSI2 TX Controller
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*
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* Copyright (C) 2017-2019 Cadence Design Systems Inc.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_graph.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <media/mipi-csi2.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-fwnode.h>
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#include <media/v4l2-subdev.h>
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#define CSI2TX_DEVICE_CONFIG_REG 0x00
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#define CSI2TX_DEVICE_CONFIG_STREAMS_MASK GENMASK(6, 4)
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#define CSI2TX_DEVICE_CONFIG_HAS_DPHY BIT(3)
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#define CSI2TX_DEVICE_CONFIG_LANES_MASK GENMASK(2, 0)
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#define CSI2TX_CONFIG_REG 0x20
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#define CSI2TX_CONFIG_CFG_REQ BIT(2)
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#define CSI2TX_CONFIG_SRST_REQ BIT(1)
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#define CSI2TX_DPHY_CFG_REG 0x28
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#define CSI2TX_DPHY_CFG_CLK_RESET BIT(16)
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#define CSI2TX_DPHY_CFG_LANE_RESET(n) BIT((n) + 12)
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#define CSI2TX_DPHY_CFG_MODE_MASK GENMASK(9, 8)
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#define CSI2TX_DPHY_CFG_MODE_LPDT (2 << 8)
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#define CSI2TX_DPHY_CFG_MODE_HS (1 << 8)
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#define CSI2TX_DPHY_CFG_MODE_ULPS (0 << 8)
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#define CSI2TX_DPHY_CFG_CLK_ENABLE BIT(4)
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#define CSI2TX_DPHY_CFG_LANE_ENABLE(n) BIT(n)
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#define CSI2TX_DPHY_CLK_WAKEUP_REG 0x2c
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#define CSI2TX_DPHY_CLK_WAKEUP_ULPS_CYCLES(n) ((n) & 0xffff)
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#define CSI2TX_DT_CFG_REG(n) (0x80 + (n) * 8)
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#define CSI2TX_DT_CFG_DT(n) (((n) & 0x3f) << 2)
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#define CSI2TX_DT_FORMAT_REG(n) (0x84 + (n) * 8)
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#define CSI2TX_DT_FORMAT_BYTES_PER_LINE(n) (((n) & 0xffff) << 16)
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#define CSI2TX_DT_FORMAT_MAX_LINE_NUM(n) ((n) & 0xffff)
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#define CSI2TX_STREAM_IF_CFG_REG(n) (0x100 + (n) * 4)
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#define CSI2TX_STREAM_IF_CFG_FILL_LEVEL(n) ((n) & 0x1f)
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/* CSI2TX V2 Registers */
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#define CSI2TX_V2_DPHY_CFG_REG 0x28
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#define CSI2TX_V2_DPHY_CFG_RESET BIT(16)
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#define CSI2TX_V2_DPHY_CFG_CLOCK_MODE BIT(10)
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#define CSI2TX_V2_DPHY_CFG_MODE_MASK GENMASK(9, 8)
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#define CSI2TX_V2_DPHY_CFG_MODE_LPDT (2 << 8)
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#define CSI2TX_V2_DPHY_CFG_MODE_HS (1 << 8)
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#define CSI2TX_V2_DPHY_CFG_MODE_ULPS (0 << 8)
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#define CSI2TX_V2_DPHY_CFG_CLK_ENABLE BIT(4)
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#define CSI2TX_V2_DPHY_CFG_LANE_ENABLE(n) BIT(n)
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#define CSI2TX_LANES_MAX 4
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#define CSI2TX_STREAMS_MAX 4
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enum csi2tx_pads {
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CSI2TX_PAD_SOURCE,
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CSI2TX_PAD_SINK_STREAM0,
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CSI2TX_PAD_SINK_STREAM1,
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CSI2TX_PAD_SINK_STREAM2,
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CSI2TX_PAD_SINK_STREAM3,
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CSI2TX_PAD_MAX,
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};
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struct csi2tx_fmt {
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u32 mbus;
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u32 dt;
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u32 bpp;
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};
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struct csi2tx_priv;
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/* CSI2TX Variant Operations */
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struct csi2tx_vops {
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void (*dphy_setup)(struct csi2tx_priv *csi2tx);
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};
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struct csi2tx_priv {
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struct device *dev;
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unsigned int count;
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/*
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* Used to prevent race conditions between multiple,
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* concurrent calls to start and stop.
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*/
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struct mutex lock;
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void __iomem *base;
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struct csi2tx_vops *vops;
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struct clk *esc_clk;
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struct clk *p_clk;
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struct clk *pixel_clk[CSI2TX_STREAMS_MAX];
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struct v4l2_subdev subdev;
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struct media_pad pads[CSI2TX_PAD_MAX];
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struct v4l2_mbus_framefmt pad_fmts[CSI2TX_PAD_MAX];
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bool has_internal_dphy;
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u8 lanes[CSI2TX_LANES_MAX];
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unsigned int num_lanes;
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unsigned int max_lanes;
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unsigned int max_streams;
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};
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static const struct csi2tx_fmt csi2tx_formats[] = {
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{
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.mbus = MEDIA_BUS_FMT_UYVY8_1X16,
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.bpp = 2,
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.dt = MIPI_CSI2_DT_YUV422_8B,
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},
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{
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.mbus = MEDIA_BUS_FMT_RGB888_1X24,
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.bpp = 3,
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.dt = MIPI_CSI2_DT_RGB888,
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},
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};
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static const struct v4l2_mbus_framefmt fmt_default = {
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.width = 1280,
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.height = 720,
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.code = MEDIA_BUS_FMT_RGB888_1X24,
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.field = V4L2_FIELD_NONE,
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.colorspace = V4L2_COLORSPACE_DEFAULT,
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};
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static inline
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struct csi2tx_priv *v4l2_subdev_to_csi2tx(struct v4l2_subdev *subdev)
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{
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return container_of(subdev, struct csi2tx_priv, subdev);
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}
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static const struct csi2tx_fmt *csi2tx_get_fmt_from_mbus(u32 mbus)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(csi2tx_formats); i++)
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if (csi2tx_formats[i].mbus == mbus)
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return &csi2tx_formats[i];
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return NULL;
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}
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static int csi2tx_enum_mbus_code(struct v4l2_subdev *subdev,
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struct v4l2_subdev_state *sd_state,
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struct v4l2_subdev_mbus_code_enum *code)
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{
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if (code->pad || code->index >= ARRAY_SIZE(csi2tx_formats))
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return -EINVAL;
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code->code = csi2tx_formats[code->index].mbus;
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return 0;
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}
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static struct v4l2_mbus_framefmt *
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__csi2tx_get_pad_format(struct v4l2_subdev *subdev,
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struct v4l2_subdev_state *sd_state,
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struct v4l2_subdev_format *fmt)
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{
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struct csi2tx_priv *csi2tx = v4l2_subdev_to_csi2tx(subdev);
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if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
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return v4l2_subdev_get_try_format(subdev, sd_state,
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fmt->pad);
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return &csi2tx->pad_fmts[fmt->pad];
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}
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static int csi2tx_get_pad_format(struct v4l2_subdev *subdev,
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struct v4l2_subdev_state *sd_state,
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struct v4l2_subdev_format *fmt)
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{
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const struct v4l2_mbus_framefmt *format;
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/* Multiplexed pad? */
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if (fmt->pad == CSI2TX_PAD_SOURCE)
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return -EINVAL;
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format = __csi2tx_get_pad_format(subdev, sd_state, fmt);
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if (!format)
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return -EINVAL;
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fmt->format = *format;
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return 0;
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}
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static int csi2tx_set_pad_format(struct v4l2_subdev *subdev,
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struct v4l2_subdev_state *sd_state,
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struct v4l2_subdev_format *fmt)
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{
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const struct v4l2_mbus_framefmt *src_format = &fmt->format;
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struct v4l2_mbus_framefmt *dst_format;
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/* Multiplexed pad? */
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if (fmt->pad == CSI2TX_PAD_SOURCE)
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return -EINVAL;
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if (!csi2tx_get_fmt_from_mbus(fmt->format.code))
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src_format = &fmt_default;
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dst_format = __csi2tx_get_pad_format(subdev, sd_state, fmt);
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if (!dst_format)
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return -EINVAL;
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*dst_format = *src_format;
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return 0;
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}
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static const struct v4l2_subdev_pad_ops csi2tx_pad_ops = {
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.enum_mbus_code = csi2tx_enum_mbus_code,
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.get_fmt = csi2tx_get_pad_format,
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.set_fmt = csi2tx_set_pad_format,
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};
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/* Set Wake Up value in the D-PHY */
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static void csi2tx_dphy_set_wakeup(struct csi2tx_priv *csi2tx)
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{
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writel(CSI2TX_DPHY_CLK_WAKEUP_ULPS_CYCLES(32),
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csi2tx->base + CSI2TX_DPHY_CLK_WAKEUP_REG);
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}
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/*
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* Finishes the D-PHY initialization
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* reg dphy cfg value to be used
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*/
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static void csi2tx_dphy_init_finish(struct csi2tx_priv *csi2tx, u32 reg)
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{
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unsigned int i;
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udelay(10);
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/* Enable our (clock and data) lanes */
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reg |= CSI2TX_DPHY_CFG_CLK_ENABLE;
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for (i = 0; i < csi2tx->num_lanes; i++)
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reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1);
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writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
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udelay(10);
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/* Switch to HS mode */
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reg &= ~CSI2TX_DPHY_CFG_MODE_MASK;
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writel(reg | CSI2TX_DPHY_CFG_MODE_HS,
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csi2tx->base + CSI2TX_DPHY_CFG_REG);
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}
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/* Configures D-PHY in CSIv1.3 */
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static void csi2tx_dphy_setup(struct csi2tx_priv *csi2tx)
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{
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u32 reg;
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unsigned int i;
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csi2tx_dphy_set_wakeup(csi2tx);
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/* Put our lanes (clock and data) out of reset */
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reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT;
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for (i = 0; i < csi2tx->num_lanes; i++)
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reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1);
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writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
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csi2tx_dphy_init_finish(csi2tx, reg);
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}
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/* Configures D-PHY in CSIv2 */
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static void csi2tx_v2_dphy_setup(struct csi2tx_priv *csi2tx)
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{
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u32 reg;
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csi2tx_dphy_set_wakeup(csi2tx);
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/* Put our lanes (clock and data) out of reset */
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reg = CSI2TX_V2_DPHY_CFG_RESET | CSI2TX_V2_DPHY_CFG_MODE_LPDT;
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writel(reg, csi2tx->base + CSI2TX_V2_DPHY_CFG_REG);
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csi2tx_dphy_init_finish(csi2tx, reg);
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}
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static void csi2tx_reset(struct csi2tx_priv *csi2tx)
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{
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writel(CSI2TX_CONFIG_SRST_REQ, csi2tx->base + CSI2TX_CONFIG_REG);
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udelay(10);
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}
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static int csi2tx_start(struct csi2tx_priv *csi2tx)
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{
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struct media_entity *entity = &csi2tx->subdev.entity;
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struct media_link *link;
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unsigned int i;
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csi2tx_reset(csi2tx);
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writel(CSI2TX_CONFIG_CFG_REQ, csi2tx->base + CSI2TX_CONFIG_REG);
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udelay(10);
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if (csi2tx->vops && csi2tx->vops->dphy_setup) {
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csi2tx->vops->dphy_setup(csi2tx);
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udelay(10);
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}
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/*
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* Create a static mapping between the CSI virtual channels
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* and the input streams.
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*
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* This should be enhanced, but v4l2 lacks the support for
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* changing that mapping dynamically at the moment.
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*
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* We're protected from the userspace setting up links at the
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* same time by the upper layer having called
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* media_pipeline_start().
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*/
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list_for_each_entry(link, &entity->links, list) {
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struct v4l2_mbus_framefmt *mfmt;
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const struct csi2tx_fmt *fmt;
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unsigned int stream;
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int pad_idx = -1;
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/* Only consider our enabled input pads */
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for (i = CSI2TX_PAD_SINK_STREAM0; i < CSI2TX_PAD_MAX; i++) {
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struct media_pad *pad = &csi2tx->pads[i];
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if ((pad == link->sink) &&
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(link->flags & MEDIA_LNK_FL_ENABLED)) {
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pad_idx = i;
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break;
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}
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}
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if (pad_idx < 0)
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continue;
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mfmt = &csi2tx->pad_fmts[pad_idx];
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fmt = csi2tx_get_fmt_from_mbus(mfmt->code);
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if (!fmt)
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continue;
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stream = pad_idx - CSI2TX_PAD_SINK_STREAM0;
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/*
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* We use the stream ID there, but it's wrong.
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*
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* A stream could very well send a data type that is
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* not equal to its stream ID. We need to find a
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* proper way to address it.
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*/
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writel(CSI2TX_DT_CFG_DT(fmt->dt),
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csi2tx->base + CSI2TX_DT_CFG_REG(stream));
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writel(CSI2TX_DT_FORMAT_BYTES_PER_LINE(mfmt->width * fmt->bpp) |
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CSI2TX_DT_FORMAT_MAX_LINE_NUM(mfmt->height + 1),
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csi2tx->base + CSI2TX_DT_FORMAT_REG(stream));
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/*
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* TODO: This needs to be calculated based on the
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* output CSI2 clock rate.
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*/
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writel(CSI2TX_STREAM_IF_CFG_FILL_LEVEL(4),
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csi2tx->base + CSI2TX_STREAM_IF_CFG_REG(stream));
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}
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/* Disable the configuration mode */
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writel(0, csi2tx->base + CSI2TX_CONFIG_REG);
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return 0;
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}
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static void csi2tx_stop(struct csi2tx_priv *csi2tx)
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{
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writel(CSI2TX_CONFIG_CFG_REQ | CSI2TX_CONFIG_SRST_REQ,
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csi2tx->base + CSI2TX_CONFIG_REG);
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}
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static int csi2tx_s_stream(struct v4l2_subdev *subdev, int enable)
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{
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struct csi2tx_priv *csi2tx = v4l2_subdev_to_csi2tx(subdev);
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int ret = 0;
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mutex_lock(&csi2tx->lock);
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if (enable) {
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/*
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* If we're not the first users, there's no need to
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* enable the whole controller.
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*/
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if (!csi2tx->count) {
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ret = csi2tx_start(csi2tx);
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if (ret)
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goto out;
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}
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csi2tx->count++;
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} else {
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csi2tx->count--;
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/*
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* Let the last user turn off the lights.
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*/
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if (!csi2tx->count)
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csi2tx_stop(csi2tx);
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}
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out:
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mutex_unlock(&csi2tx->lock);
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return ret;
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}
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static const struct v4l2_subdev_video_ops csi2tx_video_ops = {
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.s_stream = csi2tx_s_stream,
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};
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static const struct v4l2_subdev_ops csi2tx_subdev_ops = {
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.pad = &csi2tx_pad_ops,
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.video = &csi2tx_video_ops,
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};
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static int csi2tx_get_resources(struct csi2tx_priv *csi2tx,
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struct platform_device *pdev)
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{
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unsigned int i;
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u32 dev_cfg;
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int ret;
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csi2tx->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(csi2tx->base))
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return PTR_ERR(csi2tx->base);
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csi2tx->p_clk = devm_clk_get(&pdev->dev, "p_clk");
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if (IS_ERR(csi2tx->p_clk)) {
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dev_err(&pdev->dev, "Couldn't get p_clk\n");
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return PTR_ERR(csi2tx->p_clk);
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}
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csi2tx->esc_clk = devm_clk_get(&pdev->dev, "esc_clk");
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if (IS_ERR(csi2tx->esc_clk)) {
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dev_err(&pdev->dev, "Couldn't get the esc_clk\n");
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return PTR_ERR(csi2tx->esc_clk);
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}
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ret = clk_prepare_enable(csi2tx->p_clk);
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if (ret) {
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dev_err(&pdev->dev, "Couldn't prepare and enable p_clk\n");
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return ret;
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}
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dev_cfg = readl(csi2tx->base + CSI2TX_DEVICE_CONFIG_REG);
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clk_disable_unprepare(csi2tx->p_clk);
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csi2tx->max_lanes = dev_cfg & CSI2TX_DEVICE_CONFIG_LANES_MASK;
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if (csi2tx->max_lanes > CSI2TX_LANES_MAX) {
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dev_err(&pdev->dev, "Invalid number of lanes: %u\n",
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csi2tx->max_lanes);
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return -EINVAL;
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}
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csi2tx->max_streams = (dev_cfg & CSI2TX_DEVICE_CONFIG_STREAMS_MASK) >> 4;
|
|
if (csi2tx->max_streams > CSI2TX_STREAMS_MAX) {
|
|
dev_err(&pdev->dev, "Invalid number of streams: %u\n",
|
|
csi2tx->max_streams);
|
|
return -EINVAL;
|
|
}
|
|
|
|
csi2tx->has_internal_dphy = !!(dev_cfg & CSI2TX_DEVICE_CONFIG_HAS_DPHY);
|
|
|
|
for (i = 0; i < csi2tx->max_streams; i++) {
|
|
char clk_name[16];
|
|
|
|
snprintf(clk_name, sizeof(clk_name), "pixel_if%u_clk", i);
|
|
csi2tx->pixel_clk[i] = devm_clk_get(&pdev->dev, clk_name);
|
|
if (IS_ERR(csi2tx->pixel_clk[i])) {
|
|
dev_err(&pdev->dev, "Couldn't get clock %s\n",
|
|
clk_name);
|
|
return PTR_ERR(csi2tx->pixel_clk[i]);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int csi2tx_check_lanes(struct csi2tx_priv *csi2tx)
|
|
{
|
|
struct v4l2_fwnode_endpoint v4l2_ep = { .bus_type = 0 };
|
|
struct device_node *ep;
|
|
int ret, i;
|
|
|
|
ep = of_graph_get_endpoint_by_regs(csi2tx->dev->of_node, 0, 0);
|
|
if (!ep)
|
|
return -EINVAL;
|
|
|
|
ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &v4l2_ep);
|
|
if (ret) {
|
|
dev_err(csi2tx->dev, "Could not parse v4l2 endpoint\n");
|
|
goto out;
|
|
}
|
|
|
|
if (v4l2_ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
|
|
dev_err(csi2tx->dev, "Unsupported media bus type: 0x%x\n",
|
|
v4l2_ep.bus_type);
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
csi2tx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes;
|
|
if (csi2tx->num_lanes > csi2tx->max_lanes) {
|
|
dev_err(csi2tx->dev,
|
|
"Current configuration uses more lanes than supported\n");
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
for (i = 0; i < csi2tx->num_lanes; i++) {
|
|
if (v4l2_ep.bus.mipi_csi2.data_lanes[i] < 1) {
|
|
dev_err(csi2tx->dev, "Invalid lane[%d] number: %u\n",
|
|
i, v4l2_ep.bus.mipi_csi2.data_lanes[i]);
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
memcpy(csi2tx->lanes, v4l2_ep.bus.mipi_csi2.data_lanes,
|
|
sizeof(csi2tx->lanes));
|
|
|
|
out:
|
|
of_node_put(ep);
|
|
return ret;
|
|
}
|
|
|
|
static const struct csi2tx_vops csi2tx_vops = {
|
|
.dphy_setup = csi2tx_dphy_setup,
|
|
};
|
|
|
|
static const struct csi2tx_vops csi2tx_v2_vops = {
|
|
.dphy_setup = csi2tx_v2_dphy_setup,
|
|
};
|
|
|
|
static const struct of_device_id csi2tx_of_table[] = {
|
|
{
|
|
.compatible = "cdns,csi2tx",
|
|
.data = &csi2tx_vops
|
|
},
|
|
{
|
|
.compatible = "cdns,csi2tx-1.3",
|
|
.data = &csi2tx_vops
|
|
},
|
|
{
|
|
.compatible = "cdns,csi2tx-2.1",
|
|
.data = &csi2tx_v2_vops
|
|
},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, csi2tx_of_table);
|
|
|
|
static int csi2tx_probe(struct platform_device *pdev)
|
|
{
|
|
struct csi2tx_priv *csi2tx;
|
|
const struct of_device_id *of_id;
|
|
unsigned int i;
|
|
int ret;
|
|
|
|
csi2tx = kzalloc(sizeof(*csi2tx), GFP_KERNEL);
|
|
if (!csi2tx)
|
|
return -ENOMEM;
|
|
platform_set_drvdata(pdev, csi2tx);
|
|
mutex_init(&csi2tx->lock);
|
|
csi2tx->dev = &pdev->dev;
|
|
|
|
ret = csi2tx_get_resources(csi2tx, pdev);
|
|
if (ret)
|
|
goto err_free_priv;
|
|
|
|
of_id = of_match_node(csi2tx_of_table, pdev->dev.of_node);
|
|
csi2tx->vops = (struct csi2tx_vops *)of_id->data;
|
|
|
|
v4l2_subdev_init(&csi2tx->subdev, &csi2tx_subdev_ops);
|
|
csi2tx->subdev.owner = THIS_MODULE;
|
|
csi2tx->subdev.dev = &pdev->dev;
|
|
csi2tx->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
|
|
snprintf(csi2tx->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s.%s",
|
|
KBUILD_MODNAME, dev_name(&pdev->dev));
|
|
|
|
ret = csi2tx_check_lanes(csi2tx);
|
|
if (ret)
|
|
goto err_free_priv;
|
|
|
|
/* Create our media pads */
|
|
csi2tx->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
|
|
csi2tx->pads[CSI2TX_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
|
|
for (i = CSI2TX_PAD_SINK_STREAM0; i < CSI2TX_PAD_MAX; i++)
|
|
csi2tx->pads[i].flags = MEDIA_PAD_FL_SINK;
|
|
|
|
/*
|
|
* Only the input pads are considered to have a format at the
|
|
* moment. The CSI link can multiplex various streams with
|
|
* different formats, and we can't expose this in v4l2 right
|
|
* now.
|
|
*/
|
|
for (i = CSI2TX_PAD_SINK_STREAM0; i < CSI2TX_PAD_MAX; i++)
|
|
csi2tx->pad_fmts[i] = fmt_default;
|
|
|
|
ret = media_entity_pads_init(&csi2tx->subdev.entity, CSI2TX_PAD_MAX,
|
|
csi2tx->pads);
|
|
if (ret)
|
|
goto err_free_priv;
|
|
|
|
ret = v4l2_async_register_subdev(&csi2tx->subdev);
|
|
if (ret < 0)
|
|
goto err_free_priv;
|
|
|
|
dev_info(&pdev->dev,
|
|
"Probed CSI2TX with %u/%u lanes, %u streams, %s D-PHY\n",
|
|
csi2tx->num_lanes, csi2tx->max_lanes, csi2tx->max_streams,
|
|
csi2tx->has_internal_dphy ? "internal" : "no");
|
|
|
|
return 0;
|
|
|
|
err_free_priv:
|
|
kfree(csi2tx);
|
|
return ret;
|
|
}
|
|
|
|
static int csi2tx_remove(struct platform_device *pdev)
|
|
{
|
|
struct csi2tx_priv *csi2tx = platform_get_drvdata(pdev);
|
|
|
|
v4l2_async_unregister_subdev(&csi2tx->subdev);
|
|
kfree(csi2tx);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver csi2tx_driver = {
|
|
.probe = csi2tx_probe,
|
|
.remove = csi2tx_remove,
|
|
|
|
.driver = {
|
|
.name = "cdns-csi2tx",
|
|
.of_match_table = csi2tx_of_table,
|
|
},
|
|
};
|
|
module_platform_driver(csi2tx_driver);
|
|
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@bootlin.com>");
|
|
MODULE_DESCRIPTION("Cadence CSI2-TX controller");
|
|
MODULE_LICENSE("GPL");
|