312 lines
		
	
	
		
			6.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			312 lines
		
	
	
		
			6.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0-only
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| /*
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|  * Microchip Image Sensor Controller (ISC) common clock driver setup
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|  *
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|  * Copyright (C) 2016 Microchip Technology, Inc.
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|  *
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|  * Author: Songjun Wu
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|  * Author: Eugen Hristev <eugen.hristev@microchip.com>
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|  *
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|  */
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| #include <linux/clk.h>
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| #include <linux/clkdev.h>
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| #include <linux/clk-provider.h>
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| #include <linux/pm_runtime.h>
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| #include <linux/regmap.h>
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| 
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| #include "atmel-isc-regs.h"
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| #include "atmel-isc.h"
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| 
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| static int isc_wait_clk_stable(struct clk_hw *hw)
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| {
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| 	struct isc_clk *isc_clk = to_isc_clk(hw);
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| 	struct regmap *regmap = isc_clk->regmap;
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| 	unsigned long timeout = jiffies + usecs_to_jiffies(1000);
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| 	unsigned int status;
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| 
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| 	while (time_before(jiffies, timeout)) {
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| 		regmap_read(regmap, ISC_CLKSR, &status);
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| 		if (!(status & ISC_CLKSR_SIP))
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| 			return 0;
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| 
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| 		usleep_range(10, 250);
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| 	}
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| 
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| 	return -ETIMEDOUT;
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| }
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| 
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| static int isc_clk_prepare(struct clk_hw *hw)
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| {
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| 	struct isc_clk *isc_clk = to_isc_clk(hw);
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| 	int ret;
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| 
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| 	ret = pm_runtime_resume_and_get(isc_clk->dev);
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| 	if (ret < 0)
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| 		return ret;
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| 
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| 	return isc_wait_clk_stable(hw);
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| }
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| 
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| static void isc_clk_unprepare(struct clk_hw *hw)
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| {
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| 	struct isc_clk *isc_clk = to_isc_clk(hw);
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| 
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| 	isc_wait_clk_stable(hw);
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| 
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| 	pm_runtime_put_sync(isc_clk->dev);
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| }
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| 
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| static int isc_clk_enable(struct clk_hw *hw)
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| {
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| 	struct isc_clk *isc_clk = to_isc_clk(hw);
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| 	u32 id = isc_clk->id;
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| 	struct regmap *regmap = isc_clk->regmap;
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| 	unsigned long flags;
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| 	unsigned int status;
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| 
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| 	dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n",
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| 		__func__, id, isc_clk->div, isc_clk->parent_id);
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| 
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| 	spin_lock_irqsave(&isc_clk->lock, flags);
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| 	regmap_update_bits(regmap, ISC_CLKCFG,
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| 			   ISC_CLKCFG_DIV_MASK(id) | ISC_CLKCFG_SEL_MASK(id),
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| 			   (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) |
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| 			   (isc_clk->parent_id << ISC_CLKCFG_SEL_SHIFT(id)));
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| 
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| 	regmap_write(regmap, ISC_CLKEN, ISC_CLK(id));
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| 	spin_unlock_irqrestore(&isc_clk->lock, flags);
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| 
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| 	regmap_read(regmap, ISC_CLKSR, &status);
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| 	if (status & ISC_CLK(id))
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| 		return 0;
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| 	else
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| 		return -EINVAL;
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| }
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| 
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| static void isc_clk_disable(struct clk_hw *hw)
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| {
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| 	struct isc_clk *isc_clk = to_isc_clk(hw);
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| 	u32 id = isc_clk->id;
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| 	unsigned long flags;
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| 
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| 	spin_lock_irqsave(&isc_clk->lock, flags);
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| 	regmap_write(isc_clk->regmap, ISC_CLKDIS, ISC_CLK(id));
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| 	spin_unlock_irqrestore(&isc_clk->lock, flags);
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| }
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| 
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| static int isc_clk_is_enabled(struct clk_hw *hw)
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| {
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| 	struct isc_clk *isc_clk = to_isc_clk(hw);
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| 	u32 status;
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| 	int ret;
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| 
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| 	ret = pm_runtime_resume_and_get(isc_clk->dev);
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| 	if (ret < 0)
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| 		return 0;
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| 
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| 	regmap_read(isc_clk->regmap, ISC_CLKSR, &status);
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| 
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| 	pm_runtime_put_sync(isc_clk->dev);
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| 
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| 	return status & ISC_CLK(isc_clk->id) ? 1 : 0;
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| }
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| 
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| static unsigned long
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| isc_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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| {
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| 	struct isc_clk *isc_clk = to_isc_clk(hw);
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| 
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| 	return DIV_ROUND_CLOSEST(parent_rate, isc_clk->div + 1);
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| }
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| 
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| static int isc_clk_determine_rate(struct clk_hw *hw,
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| 				  struct clk_rate_request *req)
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| {
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| 	struct isc_clk *isc_clk = to_isc_clk(hw);
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| 	long best_rate = -EINVAL;
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| 	int best_diff = -1;
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| 	unsigned int i, div;
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| 
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| 	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
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| 		struct clk_hw *parent;
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| 		unsigned long parent_rate;
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| 
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| 		parent = clk_hw_get_parent_by_index(hw, i);
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| 		if (!parent)
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| 			continue;
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| 
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| 		parent_rate = clk_hw_get_rate(parent);
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| 		if (!parent_rate)
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| 			continue;
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| 
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| 		for (div = 1; div < ISC_CLK_MAX_DIV + 2; div++) {
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| 			unsigned long rate;
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| 			int diff;
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| 
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| 			rate = DIV_ROUND_CLOSEST(parent_rate, div);
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| 			diff = abs(req->rate - rate);
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| 
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| 			if (best_diff < 0 || best_diff > diff) {
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| 				best_rate = rate;
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| 				best_diff = diff;
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| 				req->best_parent_rate = parent_rate;
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| 				req->best_parent_hw = parent;
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| 			}
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| 
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| 			if (!best_diff || rate < req->rate)
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| 				break;
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| 		}
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| 
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| 		if (!best_diff)
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| 			break;
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| 	}
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| 
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| 	dev_dbg(isc_clk->dev,
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| 		"ISC CLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
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| 		__func__, best_rate,
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| 		__clk_get_name((req->best_parent_hw)->clk),
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| 		req->best_parent_rate);
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| 
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| 	if (best_rate < 0)
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| 		return best_rate;
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| 
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| 	req->rate = best_rate;
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| 
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| 	return 0;
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| }
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| 
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| static int isc_clk_set_parent(struct clk_hw *hw, u8 index)
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| {
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| 	struct isc_clk *isc_clk = to_isc_clk(hw);
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| 
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| 	if (index >= clk_hw_get_num_parents(hw))
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| 		return -EINVAL;
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| 
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| 	isc_clk->parent_id = index;
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| 
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| 	return 0;
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| }
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| 
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| static u8 isc_clk_get_parent(struct clk_hw *hw)
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| {
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| 	struct isc_clk *isc_clk = to_isc_clk(hw);
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| 
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| 	return isc_clk->parent_id;
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| }
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| 
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| static int isc_clk_set_rate(struct clk_hw *hw,
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| 			    unsigned long rate,
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| 			    unsigned long parent_rate)
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| {
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| 	struct isc_clk *isc_clk = to_isc_clk(hw);
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| 	u32 div;
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| 
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| 	if (!rate)
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| 		return -EINVAL;
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| 
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| 	div = DIV_ROUND_CLOSEST(parent_rate, rate);
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| 	if (div > (ISC_CLK_MAX_DIV + 1) || !div)
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| 		return -EINVAL;
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| 
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| 	isc_clk->div = div - 1;
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| 
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| 	return 0;
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| }
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| 
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| static const struct clk_ops isc_clk_ops = {
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| 	.prepare	= isc_clk_prepare,
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| 	.unprepare	= isc_clk_unprepare,
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| 	.enable		= isc_clk_enable,
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| 	.disable	= isc_clk_disable,
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| 	.is_enabled	= isc_clk_is_enabled,
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| 	.recalc_rate	= isc_clk_recalc_rate,
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| 	.determine_rate	= isc_clk_determine_rate,
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| 	.set_parent	= isc_clk_set_parent,
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| 	.get_parent	= isc_clk_get_parent,
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| 	.set_rate	= isc_clk_set_rate,
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| };
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| 
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| static int isc_clk_register(struct isc_device *isc, unsigned int id)
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| {
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| 	struct regmap *regmap = isc->regmap;
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| 	struct device_node *np = isc->dev->of_node;
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| 	struct isc_clk *isc_clk;
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| 	struct clk_init_data init;
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| 	const char *clk_name = np->name;
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| 	const char *parent_names[3];
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| 	int num_parents;
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| 
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| 	if (id == ISC_ISPCK && !isc->ispck_required)
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| 		return 0;
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| 
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| 	num_parents = of_clk_get_parent_count(np);
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| 	if (num_parents < 1 || num_parents > 3)
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| 		return -EINVAL;
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| 
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| 	if (num_parents > 2 && id == ISC_ISPCK)
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| 		num_parents = 2;
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| 
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| 	of_clk_parent_fill(np, parent_names, num_parents);
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| 
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| 	if (id == ISC_MCK)
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| 		of_property_read_string(np, "clock-output-names", &clk_name);
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| 	else
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| 		clk_name = "isc-ispck";
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| 
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| 	init.parent_names	= parent_names;
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| 	init.num_parents	= num_parents;
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| 	init.name		= clk_name;
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| 	init.ops		= &isc_clk_ops;
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| 	init.flags		= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
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| 
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| 	isc_clk = &isc->isc_clks[id];
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| 	isc_clk->hw.init	= &init;
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| 	isc_clk->regmap		= regmap;
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| 	isc_clk->id		= id;
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| 	isc_clk->dev		= isc->dev;
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| 	spin_lock_init(&isc_clk->lock);
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| 
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| 	isc_clk->clk = clk_register(isc->dev, &isc_clk->hw);
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| 	if (IS_ERR(isc_clk->clk)) {
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| 		dev_err(isc->dev, "%s: clock register fail\n", clk_name);
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| 		return PTR_ERR(isc_clk->clk);
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| 	} else if (id == ISC_MCK) {
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| 		of_clk_add_provider(np, of_clk_src_simple_get, isc_clk->clk);
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| 	}
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| 
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| 	return 0;
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| }
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| 
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| int isc_clk_init(struct isc_device *isc)
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| {
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| 	unsigned int i;
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| 	int ret;
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| 
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| 	for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++)
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| 		isc->isc_clks[i].clk = ERR_PTR(-EINVAL);
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| 
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| 	for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
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| 		ret = isc_clk_register(isc, i);
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| 		if (ret)
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| 			return ret;
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| 	}
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| 
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| 	return 0;
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| }
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| EXPORT_SYMBOL_GPL(isc_clk_init);
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| 
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| void isc_clk_cleanup(struct isc_device *isc)
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| {
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| 	unsigned int i;
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| 
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| 	of_clk_del_provider(isc->dev->of_node);
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| 
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| 	for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
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| 		struct isc_clk *isc_clk = &isc->isc_clks[i];
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| 
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| 		if (!IS_ERR(isc_clk->clk))
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| 			clk_unregister(isc_clk->clk);
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| 	}
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| }
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| EXPORT_SYMBOL_GPL(isc_clk_cleanup);
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