95 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			95 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0+
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| //
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| // OWL divider clock driver
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| //
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| // Copyright (c) 2014 Actions Semi Inc.
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| // Author: David Liu <liuwei@actions-semi.com>
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| //
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| // Copyright (c) 2018 Linaro Ltd.
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| // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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| 
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| #include <linux/clk-provider.h>
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| #include <linux/regmap.h>
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| 
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| #include "owl-divider.h"
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| 
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| long owl_divider_helper_round_rate(struct owl_clk_common *common,
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| 				const struct owl_divider_hw *div_hw,
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| 				unsigned long rate,
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| 				unsigned long *parent_rate)
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| {
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| 	return divider_round_rate(&common->hw, rate, parent_rate,
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| 				  div_hw->table, div_hw->width,
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| 				  div_hw->div_flags);
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| }
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| 
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| static long owl_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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| 				unsigned long *parent_rate)
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| {
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| 	struct owl_divider *div = hw_to_owl_divider(hw);
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| 
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| 	return owl_divider_helper_round_rate(&div->common, &div->div_hw,
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| 					     rate, parent_rate);
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| }
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| 
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| unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common,
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| 					 const struct owl_divider_hw *div_hw,
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| 					 unsigned long parent_rate)
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| {
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| 	unsigned long val;
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| 	unsigned int reg;
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| 
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| 	regmap_read(common->regmap, div_hw->reg, ®);
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| 	val = reg >> div_hw->shift;
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| 	val &= (1 << div_hw->width) - 1;
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| 
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| 	return divider_recalc_rate(&common->hw, parent_rate,
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| 				   val, div_hw->table,
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| 				   div_hw->div_flags,
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| 				   div_hw->width);
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| }
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| 
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| static unsigned long owl_divider_recalc_rate(struct clk_hw *hw,
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| 					  unsigned long parent_rate)
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| {
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| 	struct owl_divider *div = hw_to_owl_divider(hw);
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| 
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| 	return owl_divider_helper_recalc_rate(&div->common,
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| 					      &div->div_hw, parent_rate);
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| }
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| 
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| int owl_divider_helper_set_rate(const struct owl_clk_common *common,
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| 				const struct owl_divider_hw *div_hw,
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| 				unsigned long rate,
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| 				unsigned long parent_rate)
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| {
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| 	unsigned long val;
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| 	unsigned int reg;
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| 
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| 	val = divider_get_val(rate, parent_rate, div_hw->table,
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| 			      div_hw->width, 0);
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| 
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| 	regmap_read(common->regmap, div_hw->reg, ®);
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| 	reg &= ~GENMASK(div_hw->width + div_hw->shift - 1, div_hw->shift);
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| 
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| 	regmap_write(common->regmap, div_hw->reg,
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| 			  reg | (val << div_hw->shift));
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| 
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| 	return 0;
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| }
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| 
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| static int owl_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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| 				unsigned long parent_rate)
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| {
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| 	struct owl_divider *div = hw_to_owl_divider(hw);
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| 
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| 	return owl_divider_helper_set_rate(&div->common, &div->div_hw,
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| 					rate, parent_rate);
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| }
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| 
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| const struct clk_ops owl_divider_ops = {
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| 	.recalc_rate = owl_divider_recalc_rate,
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| 	.round_rate = owl_divider_round_rate,
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| 	.set_rate = owl_divider_set_rate,
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| };
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