546 lines
15 KiB
C
546 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
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*
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* Copyright (C) STMicroelectronics SA 2017
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* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
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*/
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#include <linux/clk.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_net.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_wakeirq.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/stmmac.h>
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#include "stmmac_platform.h"
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#define SYSCFG_MCU_ETH_MASK BIT(23)
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#define SYSCFG_MP1_ETH_MASK GENMASK(23, 16)
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#define SYSCFG_PMCCLRR_OFFSET 0x40
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#define SYSCFG_PMCR_ETH_CLK_SEL BIT(16)
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#define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17)
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/* CLOCK feed to PHY*/
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#define ETH_CK_F_25M 25000000
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#define ETH_CK_F_50M 50000000
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#define ETH_CK_F_125M 125000000
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/* Ethernet PHY interface selection in register SYSCFG Configuration
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*------------------------------------------
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* src |BIT(23)| BIT(22)| BIT(21)|BIT(20)|
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*------------------------------------------
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* MII | 0 | 0 | 0 | 1 |
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*------------------------------------------
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* GMII | 0 | 0 | 0 | 0 |
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*------------------------------------------
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* RGMII | 0 | 0 | 1 | n/a |
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*------------------------------------------
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* RMII | 1 | 0 | 0 | n/a |
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*------------------------------------------
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*/
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#define SYSCFG_PMCR_ETH_SEL_MII BIT(20)
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#define SYSCFG_PMCR_ETH_SEL_RGMII BIT(21)
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#define SYSCFG_PMCR_ETH_SEL_RMII BIT(23)
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#define SYSCFG_PMCR_ETH_SEL_GMII 0
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#define SYSCFG_MCU_ETH_SEL_MII 0
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#define SYSCFG_MCU_ETH_SEL_RMII 1
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/* STM32MP1 register definitions
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*
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* Below table summarizes the clock requirement and clock sources for
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* supported phy interface modes.
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* __________________________________________________________________________
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*|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125Mhz from PHY|
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*| | | 25MHz | 50MHz | |
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* ---------------------------------------------------------------------------
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*| MII | - | eth-ck | n/a | n/a |
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*| | | st,ext-phyclk | | |
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* ---------------------------------------------------------------------------
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*| GMII | - | eth-ck | n/a | n/a |
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*| | | st,ext-phyclk | | |
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* ---------------------------------------------------------------------------
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*| RGMII | - | eth-ck | n/a | eth-ck |
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*| | | st,ext-phyclk | | st,eth-clk-sel or|
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*| | | | | st,ext-phyclk |
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* ---------------------------------------------------------------------------
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*| RMII | - | eth-ck | eth-ck | n/a |
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*| | | st,ext-phyclk | st,eth-ref-clk-sel | |
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*| | | | or st,ext-phyclk | |
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* ---------------------------------------------------------------------------
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*
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*/
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struct stm32_dwmac {
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struct clk *clk_tx;
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struct clk *clk_rx;
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struct clk *clk_eth_ck;
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struct clk *clk_ethstp;
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struct clk *syscfg_clk;
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int ext_phyclk;
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int enable_eth_ck;
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int eth_clk_sel_reg;
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int eth_ref_clk_sel_reg;
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int irq_pwr_wakeup;
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u32 mode_reg; /* MAC glue-logic mode register */
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struct regmap *regmap;
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u32 speed;
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const struct stm32_ops *ops;
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struct device *dev;
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};
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struct stm32_ops {
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int (*set_mode)(struct plat_stmmacenet_data *plat_dat);
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int (*clk_prepare)(struct stm32_dwmac *dwmac, bool prepare);
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int (*suspend)(struct stm32_dwmac *dwmac);
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void (*resume)(struct stm32_dwmac *dwmac);
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int (*parse_data)(struct stm32_dwmac *dwmac,
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struct device *dev);
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u32 syscfg_eth_mask;
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bool clk_rx_enable_in_suspend;
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};
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static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat)
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{
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struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
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int ret;
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if (dwmac->ops->set_mode) {
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ret = dwmac->ops->set_mode(plat_dat);
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if (ret)
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return ret;
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}
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ret = clk_prepare_enable(dwmac->clk_tx);
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if (ret)
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return ret;
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if (!dwmac->ops->clk_rx_enable_in_suspend ||
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!dwmac->dev->power.is_suspended) {
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ret = clk_prepare_enable(dwmac->clk_rx);
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if (ret) {
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clk_disable_unprepare(dwmac->clk_tx);
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return ret;
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}
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}
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if (dwmac->ops->clk_prepare) {
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ret = dwmac->ops->clk_prepare(dwmac, true);
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if (ret) {
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clk_disable_unprepare(dwmac->clk_rx);
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clk_disable_unprepare(dwmac->clk_tx);
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}
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}
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return ret;
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}
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static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
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{
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int ret = 0;
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if (prepare) {
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ret = clk_prepare_enable(dwmac->syscfg_clk);
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if (ret)
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return ret;
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if (dwmac->enable_eth_ck) {
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ret = clk_prepare_enable(dwmac->clk_eth_ck);
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if (ret) {
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clk_disable_unprepare(dwmac->syscfg_clk);
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return ret;
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}
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}
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} else {
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clk_disable_unprepare(dwmac->syscfg_clk);
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if (dwmac->enable_eth_ck)
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clk_disable_unprepare(dwmac->clk_eth_ck);
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}
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return ret;
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}
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static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
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{
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struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
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u32 reg = dwmac->mode_reg, clk_rate;
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int val;
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clk_rate = clk_get_rate(dwmac->clk_eth_ck);
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dwmac->enable_eth_ck = false;
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switch (plat_dat->interface) {
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case PHY_INTERFACE_MODE_MII:
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if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk)
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dwmac->enable_eth_ck = true;
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val = SYSCFG_PMCR_ETH_SEL_MII;
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
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break;
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case PHY_INTERFACE_MODE_GMII:
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val = SYSCFG_PMCR_ETH_SEL_GMII;
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if (clk_rate == ETH_CK_F_25M &&
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(dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
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dwmac->enable_eth_ck = true;
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val |= SYSCFG_PMCR_ETH_CLK_SEL;
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}
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
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break;
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case PHY_INTERFACE_MODE_RMII:
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val = SYSCFG_PMCR_ETH_SEL_RMII;
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if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) &&
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(dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) {
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dwmac->enable_eth_ck = true;
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val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
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}
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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val = SYSCFG_PMCR_ETH_SEL_RGMII;
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if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) &&
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(dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
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dwmac->enable_eth_ck = true;
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val |= SYSCFG_PMCR_ETH_CLK_SEL;
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}
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
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break;
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default:
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pr_debug("SYSCFG init : Do not manage %d interface\n",
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plat_dat->interface);
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/* Do not manage others interfaces */
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return -EINVAL;
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}
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/* Need to update PMCCLRR (clear register) */
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regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
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dwmac->ops->syscfg_eth_mask);
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/* Update PMCSETR (set register) */
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return regmap_update_bits(dwmac->regmap, reg,
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dwmac->ops->syscfg_eth_mask, val);
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}
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static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
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{
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struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
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u32 reg = dwmac->mode_reg;
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int val;
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switch (plat_dat->interface) {
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case PHY_INTERFACE_MODE_MII:
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val = SYSCFG_MCU_ETH_SEL_MII;
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
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break;
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case PHY_INTERFACE_MODE_RMII:
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val = SYSCFG_MCU_ETH_SEL_RMII;
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
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break;
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default:
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pr_debug("SYSCFG init : Do not manage %d interface\n",
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plat_dat->interface);
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/* Do not manage others interfaces */
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return -EINVAL;
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}
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return regmap_update_bits(dwmac->regmap, reg,
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dwmac->ops->syscfg_eth_mask, val << 23);
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}
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static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac)
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{
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clk_disable_unprepare(dwmac->clk_tx);
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clk_disable_unprepare(dwmac->clk_rx);
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if (dwmac->ops->clk_prepare)
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dwmac->ops->clk_prepare(dwmac, false);
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}
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static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
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struct device *dev)
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{
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struct device_node *np = dev->of_node;
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int err;
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/* Get TX/RX clocks */
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dwmac->clk_tx = devm_clk_get(dev, "mac-clk-tx");
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if (IS_ERR(dwmac->clk_tx)) {
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dev_err(dev, "No ETH Tx clock provided...\n");
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return PTR_ERR(dwmac->clk_tx);
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}
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dwmac->clk_rx = devm_clk_get(dev, "mac-clk-rx");
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if (IS_ERR(dwmac->clk_rx)) {
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dev_err(dev, "No ETH Rx clock provided...\n");
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return PTR_ERR(dwmac->clk_rx);
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}
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if (dwmac->ops->parse_data) {
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err = dwmac->ops->parse_data(dwmac, dev);
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if (err)
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return err;
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}
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/* Get mode register */
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dwmac->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
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if (IS_ERR(dwmac->regmap))
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return PTR_ERR(dwmac->regmap);
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err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg);
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if (err)
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dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err);
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return err;
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}
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static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
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struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct device_node *np = dev->of_node;
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int err = 0;
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/* Ethernet PHY have no crystal */
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dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
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/* Gigabit Ethernet 125MHz clock selection. */
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dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel");
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/* Ethernet 50Mhz RMII clock selection */
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dwmac->eth_ref_clk_sel_reg =
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of_property_read_bool(np, "st,eth-ref-clk-sel");
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/* Get ETH_CLK clocks */
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dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck");
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if (IS_ERR(dwmac->clk_eth_ck)) {
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dev_info(dev, "No phy clock provided...\n");
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dwmac->clk_eth_ck = NULL;
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}
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/* Clock used for low power mode */
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dwmac->clk_ethstp = devm_clk_get(dev, "ethstp");
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if (IS_ERR(dwmac->clk_ethstp)) {
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dev_err(dev,
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"No ETH peripheral clock provided for CStop mode ...\n");
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return PTR_ERR(dwmac->clk_ethstp);
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}
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/* Optional Clock for sysconfig */
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dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk");
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if (IS_ERR(dwmac->syscfg_clk))
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dwmac->syscfg_clk = NULL;
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/* Get IRQ information early to have an ability to ask for deferred
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* probe if needed before we went too far with resource allocation.
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*/
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dwmac->irq_pwr_wakeup = platform_get_irq_byname_optional(pdev,
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"stm32_pwr_wakeup");
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if (dwmac->irq_pwr_wakeup == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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if (!dwmac->clk_eth_ck && dwmac->irq_pwr_wakeup >= 0) {
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err = device_init_wakeup(&pdev->dev, true);
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if (err) {
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dev_err(&pdev->dev, "Failed to init wake up irq\n");
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return err;
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}
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err = dev_pm_set_dedicated_wake_irq(&pdev->dev,
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dwmac->irq_pwr_wakeup);
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if (err) {
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dev_err(&pdev->dev, "Failed to set wake up irq\n");
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device_init_wakeup(&pdev->dev, false);
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}
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device_set_wakeup_enable(&pdev->dev, false);
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}
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return err;
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}
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static int stm32_dwmac_probe(struct platform_device *pdev)
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{
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struct plat_stmmacenet_data *plat_dat;
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struct stmmac_resources stmmac_res;
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struct stm32_dwmac *dwmac;
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const struct stm32_ops *data;
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int ret;
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ret = stmmac_get_platform_resources(pdev, &stmmac_res);
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if (ret)
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return ret;
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plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
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if (IS_ERR(plat_dat))
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return PTR_ERR(plat_dat);
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dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
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if (!dwmac) {
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ret = -ENOMEM;
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goto err_remove_config_dt;
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}
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data = of_device_get_match_data(&pdev->dev);
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if (!data) {
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dev_err(&pdev->dev, "no of match data provided\n");
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ret = -EINVAL;
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goto err_remove_config_dt;
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}
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dwmac->ops = data;
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dwmac->dev = &pdev->dev;
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ret = stm32_dwmac_parse_data(dwmac, &pdev->dev);
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if (ret) {
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dev_err(&pdev->dev, "Unable to parse OF data\n");
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goto err_remove_config_dt;
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}
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plat_dat->bsp_priv = dwmac;
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ret = stm32_dwmac_init(plat_dat);
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if (ret)
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goto err_remove_config_dt;
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ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
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if (ret)
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goto err_clk_disable;
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return 0;
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err_clk_disable:
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stm32_dwmac_clk_disable(dwmac);
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err_remove_config_dt:
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stmmac_remove_config_dt(pdev, plat_dat);
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return ret;
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}
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static int stm32_dwmac_remove(struct platform_device *pdev)
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{
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struct net_device *ndev = platform_get_drvdata(pdev);
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struct stmmac_priv *priv = netdev_priv(ndev);
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int ret = stmmac_dvr_remove(&pdev->dev);
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struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
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stm32_dwmac_clk_disable(priv->plat->bsp_priv);
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if (dwmac->irq_pwr_wakeup >= 0) {
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dev_pm_clear_wake_irq(&pdev->dev);
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device_init_wakeup(&pdev->dev, false);
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}
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return ret;
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}
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static int stm32mp1_suspend(struct stm32_dwmac *dwmac)
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{
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int ret = 0;
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ret = clk_prepare_enable(dwmac->clk_ethstp);
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if (ret)
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return ret;
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clk_disable_unprepare(dwmac->clk_tx);
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clk_disable_unprepare(dwmac->syscfg_clk);
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if (dwmac->enable_eth_ck)
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clk_disable_unprepare(dwmac->clk_eth_ck);
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return ret;
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}
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static void stm32mp1_resume(struct stm32_dwmac *dwmac)
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{
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clk_disable_unprepare(dwmac->clk_ethstp);
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}
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static int stm32mcu_suspend(struct stm32_dwmac *dwmac)
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{
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clk_disable_unprepare(dwmac->clk_tx);
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clk_disable_unprepare(dwmac->clk_rx);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int stm32_dwmac_suspend(struct device *dev)
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{
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struct net_device *ndev = dev_get_drvdata(dev);
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struct stmmac_priv *priv = netdev_priv(ndev);
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struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
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int ret;
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ret = stmmac_suspend(dev);
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if (dwmac->ops->suspend)
|
|
ret = dwmac->ops->suspend(dwmac);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int stm32_dwmac_resume(struct device *dev)
|
|
{
|
|
struct net_device *ndev = dev_get_drvdata(dev);
|
|
struct stmmac_priv *priv = netdev_priv(ndev);
|
|
struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
|
|
int ret;
|
|
|
|
if (dwmac->ops->resume)
|
|
dwmac->ops->resume(dwmac);
|
|
|
|
ret = stm32_dwmac_init(priv->plat);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = stmmac_resume(dev);
|
|
|
|
return ret;
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
|
|
stm32_dwmac_suspend, stm32_dwmac_resume);
|
|
|
|
static struct stm32_ops stm32mcu_dwmac_data = {
|
|
.set_mode = stm32mcu_set_mode,
|
|
.suspend = stm32mcu_suspend,
|
|
.syscfg_eth_mask = SYSCFG_MCU_ETH_MASK
|
|
};
|
|
|
|
static struct stm32_ops stm32mp1_dwmac_data = {
|
|
.set_mode = stm32mp1_set_mode,
|
|
.clk_prepare = stm32mp1_clk_prepare,
|
|
.suspend = stm32mp1_suspend,
|
|
.resume = stm32mp1_resume,
|
|
.parse_data = stm32mp1_parse_data,
|
|
.syscfg_eth_mask = SYSCFG_MP1_ETH_MASK,
|
|
.clk_rx_enable_in_suspend = true
|
|
};
|
|
|
|
static const struct of_device_id stm32_dwmac_match[] = {
|
|
{ .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},
|
|
{ .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, stm32_dwmac_match);
|
|
|
|
static struct platform_driver stm32_dwmac_driver = {
|
|
.probe = stm32_dwmac_probe,
|
|
.remove = stm32_dwmac_remove,
|
|
.driver = {
|
|
.name = "stm32-dwmac",
|
|
.pm = &stm32_dwmac_pm_ops,
|
|
.of_match_table = stm32_dwmac_match,
|
|
},
|
|
};
|
|
module_platform_driver(stm32_dwmac_driver);
|
|
|
|
MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@gmail.com>");
|
|
MODULE_AUTHOR("Christophe Roullier <christophe.roullier@st.com>");
|
|
MODULE_DESCRIPTION("STMicroelectronics STM32 DWMAC Specific Glue layer");
|
|
MODULE_LICENSE("GPL v2");
|