176 lines
5.4 KiB
C
176 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2024 Rockchip Electronics Co., Ltd.
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*/
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#ifndef __LINUX_MFD_ROCKCHIP_FLEXBUS_H__
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#define __LINUX_MFD_ROCKCHIP_FLEXBUS_H__
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#define FLEXBUS_ENR 0x000
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#define FLEXBUS_FREE_SCLK 0x004
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#define FLEXBUS_CSN_CFG 0x008
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#define FLEXBUS_COM_CTL 0x00C
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#define FLEXBUS_REMAP 0x010
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#define FLEXBUS_STOP 0x014
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#define FLEXBUS_SLAVE_MODE 0x018
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#define FLEXBUS_DVP_POL 0x01C
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#define FLEXBUS_DVP_CROP_SIZE 0x020
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#define FLEXBUS_DVP_CROP_START 0x024
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#define FLEXBUS_DVP_ORDER 0x028
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#define FLEXBUS_DVP_YUV2RGB 0x02C
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#define FLEXBUS_TX_CTL 0x040
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#define FLEXBUS_TX_NUM 0x044
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#define FLEXBUS_TXWAT_START 0x048
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#define FLEXBUS_TXFIFO_DNUM 0x04C
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#define FLEXBUS_TX_WIDTH 0x050
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#define FLEXBUS_TX_CSN_DUMMY 0x054
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#define FLEXBUS_TX_CMD_LEN 0x058
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#define FLEXBUS_TX_CMD0 0x05C
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#define FLEXBUS_TX_CMD1 0x060
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#define FLEXBUS_RX_CTL 0x080
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#define FLEXBUS_RX_NUM 0x084
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#define FLEXBUS_RXFIFO_DNUM 0x088
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#define FLEXBUS_DLL_EN 0x08C
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#define FLEXBUS_DLL_NUM 0x090
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#define FLEXBUS_RXCLK_DUMMY 0x094
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#define FLEXBUS_RXCLK_CAP_CNT 0x098
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#define FLEXBUS_DMA_RD_OUTSTD 0x100
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#define FLEXBUS_DMA_WR_OUTSTD 0x104
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#define FLEXBUS_DMA_SRC_ADDR0 0x108
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#define FLEXBUS_DMA_DST_ADDR0 0x10C
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#define FLEXBUS_DMA_SRC_ADDR1 0x110
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#define FLEXBUS_DMA_DST_ADDR1 0x114
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#define FLEXBUS_DMA_SRC_LEN0 0x118
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#define FLEXBUS_DMA_DST_LEN0 0x11C
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#define FLEXBUS_DMA_SRC_LEN1 0x120
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#define FLEXBUS_DMA_DST_LEN1 0x124
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#define FLEXBUS_DMA_WAT_INT 0x128
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#define FLEXBUS_DMA_TIMEOUT 0x12C
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#define FLEXBUS_DMA_RD_LEN 0x130
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#define FLEXBUS_STATUS 0x160
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#define FLEXBUS_IMR 0x164
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#define FLEXBUS_RISR 0x168
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#define FLEXBUS_ISR 0x16C
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#define FLEXBUS_ICR 0x170
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#define FLEXBUS_REVISION 0x1F0
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/* Bit fields in ENR */
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#define FLEXBUS_RX_ENR (BIT(16 + 1) | BIT(1))
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#define FLEXBUS_RX_DIS BIT(16 + 1)
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#define FLEXBUS_TX_ENR (BIT(16) | BIT(0))
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#define FLEXBUS_TX_DIS BIT(16)
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/* Bit fields in FREE_SCLK */
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#define FLEXBUS_RX_FREE_MODE (BIT(16 + 1) | BIT(1))
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#define FLEXBUS_TX_FREE_MODE (BIT(16) | BIT(0))
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/* Bit fields in COM_CTL */
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#define FLEXBUS_TX_AND_RX 0x0
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#define FLEXBUS_TX_ONLY 0x1
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#define FLEXBUS_RX_ONLY 0x2
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#define FLEXBUS_TX_THEN_RX 0x3
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#define FLEXBUS_SCLK_SHARE BIT(2)
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#define FLEXBUS_TX_USE_RX BIT(3)
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/* Bit fields in SLAVE_MODE */
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#define FLEXBUS_DVP_SEL BIT(1)
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#define FLEXBUS_CLK1_IN BIT(0)
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/* Bit fields in TX_CTL and RX_CTL */
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#define FLEXBUS_CONTINUE_MODE BIT(4)
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#define FLEXBUS_CPOL BIT(3)
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#define FLEXBUS_CPHA BIT(2)
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/* Bit fields in TX_CTL */
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#define FLEXBUS_TX_CTL_UNIT_BYTE BIT(14)
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#define FLEXBUS_TX_CTL_MSB BIT(13)
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#define FLEXBUS_TX_CTL_CPHA_SHIFT 2
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/* Bit fields in RX_CTL */
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#define FLEXBUS_RX_CTL_FILL_DUMMY BIT(17)
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#define FLEXBUS_RX_CTL_UNIT_BYTE BIT(16)
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#define FLEXBUS_RX_CTL_MSB BIT(15)
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#define FLEXBUS_AUTOPAD BIT(14)
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#define FLEXBUS_RXD_DY BIT(5)
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#define FLEXBUS_RX_CTL_CPHA_SHIFT 2
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/* Bit fields in DMA_WAT_INT */
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#define FLEXBUS_SRC_WAT_LVL_MASK 0x3
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#define FLEXBUS_SRC_WAT_LVL_SHIFT 2
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#define FLEXBUS_DST_WAT_LVL_MASK 0x3
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#define FLEXBUS_DST_WAT_LVL_SHIFT 0
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/* Bit fields in IMR, RISR, ISR and ICR */
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#define FLEXBUS_DMA_TIMEOUT_ISR BIT(13)
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#define FLEXBUS_DMA_ERR_ISR BIT(12)
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#define FLEXBUS_DMA_DST1_ISR BIT(11)
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#define FLEXBUS_DMA_DST0_ISR BIT(10)
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#define FLEXBUS_DMA_SRC1_ISR BIT(9)
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#define FLEXBUS_DMA_SRC0_ISR BIT(8)
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#define FLEXBUS_DVP_FRAME_START_ISR BIT(7)
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#define FLEXBUS_DVP_FRAME_AB_ISR BIT(6)
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#define FLEXBUS_RX_DONE_ISR BIT(5)
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#define FLEXBUS_RX_UDF_ISR BIT(4)
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#define FLEXBUS_RX_OVF_ISR BIT(3)
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#define FLEXBUS_TX_DONE_ISR BIT(2)
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#define FLEXBUS_TX_UDF_ISR BIT(1)
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#define FLEXBUS_TX_OVF_ISR BIT(0)
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struct rockchip_flexbus;
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struct rockchip_flexbus_dfs_reg {
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u32 dfs_1bit;
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u32 dfs_2bit;
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u32 dfs_4bit;
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u32 dfs_8bit;
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u32 dfs_16bit;
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u32 dfs_mask;
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};
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struct rockchip_flexbus_config {
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void (*init_config)(struct rockchip_flexbus *rkfb);
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void (*grf_config)(struct rockchip_flexbus *rkfb, bool slave_mode, bool cpol, bool cpha);
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u32 txwat_start_max;
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};
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struct rockchip_flexbus {
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struct device *dev;
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void __iomem *base;
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struct regmap *regmap_grf;
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unsigned int opmode0;
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unsigned int opmode1;
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struct clk_bulk_data *clks;
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int num_clks;
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void *fb0_data;
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void *fb1_data;
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void (*fb0_isr)(struct rockchip_flexbus *rkfb, u32 isr);
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void (*fb1_isr)(struct rockchip_flexbus *rkfb, u32 isr);
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struct rockchip_flexbus_dfs_reg *dfs_reg;
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const struct rockchip_flexbus_config *config;
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};
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static inline void rockchip_flexbus_set_fb0(struct rockchip_flexbus *rkfb, void *fb0_data,
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void (*fb0_isr)(struct rockchip_flexbus *rkfb, u32 isr))
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{
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rkfb->fb0_data = fb0_data;
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rkfb->fb0_isr = fb0_isr;
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}
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static inline void rockchip_flexbus_set_fb1(struct rockchip_flexbus *rkfb, void *fb1_data,
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void (*fb1_isr)(struct rockchip_flexbus *rkfb, u32 isr))
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{
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rkfb->fb1_data = fb1_data;
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rkfb->fb1_isr = fb1_isr;
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}
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unsigned int rockchip_flexbus_readl(struct rockchip_flexbus *rkfb, unsigned int reg);
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void rockchip_flexbus_writel(struct rockchip_flexbus *rkfb, unsigned int reg, unsigned int val);
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void rockchip_flexbus_clrbits(struct rockchip_flexbus *rkfb, unsigned int reg,
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unsigned int clr_val);
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void rockchip_flexbus_setbits(struct rockchip_flexbus *rkfb, unsigned int reg,
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unsigned int set_val);
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void rockchip_flexbus_clrsetbits(struct rockchip_flexbus *rkfb, unsigned int reg,
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unsigned int clr_val, unsigned int set_val);
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#endif /* __LINUX_MFD_ROCKCHIP_FLEXBUS_H__ */
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