490 lines
13 KiB
C
490 lines
13 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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* Author: Finley Xiao <finley.xiao@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H
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/* cru plls */
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#define PLL_GPLL 1
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#define PLL_V0PLL 2
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#define PLL_V1PLL 3
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/* cru-clocks indices */
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#define ARMCLK 15
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#define CLK_DDR 16
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#define XIN24M_GATE 17
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#define CLK_GPLL_GATE 18
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#define CLK_V0PLL_GATE 19
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#define CLK_V1PLL_GATE 20
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#define CLK_GPLL_DIV 21
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#define CLK_GPLL_DIV_100M 22
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#define CLK_V0PLL_DIV 23
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#define CLK_V1PLL_DIV 24
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#define CLK_INT_VOICE_MATRIX0 25
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#define CLK_INT_VOICE_MATRIX1 26
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#define CLK_INT_VOICE_MATRIX2 27
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#define CLK_FRAC_UART_MATRIX0_MUX 28
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#define CLK_FRAC_UART_MATRIX1_MUX 29
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#define CLK_FRAC_VOICE_MATRIX0_MUX 30
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#define CLK_FRAC_VOICE_MATRIX1_MUX 31
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#define CLK_FRAC_COMMON_MATRIX0_MUX 32
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#define CLK_FRAC_COMMON_MATRIX1_MUX 33
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#define CLK_FRAC_COMMON_MATRIX2_MUX 34
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#define CLK_FRAC_UART_MATRIX0 35
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#define CLK_FRAC_UART_MATRIX1 36
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#define CLK_FRAC_VOICE_MATRIX0 37
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#define CLK_FRAC_VOICE_MATRIX1 38
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#define CLK_FRAC_COMMON_MATRIX0 39
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#define CLK_FRAC_COMMON_MATRIX1 40
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#define CLK_FRAC_COMMON_MATRIX2 41
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#define CLK_REF_USBPHY_TOP 42
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#define CLK_REF_DPHY_TOP 43
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#define ACLK_CORE_ROOT 44
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#define PCLK_CORE_ROOT 45
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#define PCLK_DBG 48
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#define PCLK_CORE_GRF 49
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#define PCLK_CORE_CRU 50
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#define CLK_CORE_EMA_DETECT 51
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#define CLK_REF_PVTPLL_CORE 52
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#define PCLK_GPIO1 53
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#define DBCLK_GPIO1 54
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#define ACLK_CORE_PERI_ROOT 55
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#define HCLK_CORE_PERI_ROOT 56
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#define PCLK_CORE_PERI_ROOT 57
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#define CLK_DSMC 58
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#define ACLK_DSMC 59
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#define PCLK_DSMC 60
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#define CLK_FLEXBUS_TX 61
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#define CLK_FLEXBUS_RX 62
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#define ACLK_FLEXBUS 63
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#define HCLK_FLEXBUS 64
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#define ACLK_DSMC_SLV 65
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#define HCLK_DSMC_SLV 66
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#define ACLK_BUS_ROOT 67
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#define HCLK_BUS_ROOT 68
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#define PCLK_BUS_ROOT 69
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#define ACLK_SYSRAM 70
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#define HCLK_SYSRAM 71
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#define ACLK_DMAC0 72
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#define ACLK_DMAC1 73
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#define HCLK_M0 74
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#define PCLK_BUS_GRF 75
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#define PCLK_TIMER 76
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#define CLK_TIMER0_CH0 77
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#define CLK_TIMER0_CH1 78
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#define CLK_TIMER0_CH2 79
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#define CLK_TIMER0_CH3 80
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#define CLK_TIMER0_CH4 81
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#define CLK_TIMER0_CH5 82
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#define PCLK_WDT0 83
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#define TCLK_WDT0 84
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#define PCLK_WDT1 85
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#define TCLK_WDT1 86
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#define PCLK_MAILBOX 87
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#define PCLK_INTMUX 88
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#define PCLK_SPINLOCK 89
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#define PCLK_DDRC 90
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#define HCLK_DDRPHY 91
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#define PCLK_DDRMON 92
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#define CLK_DDRMON_OSC 93
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#define PCLK_STDBY 94
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#define HCLK_USBOTG0 95
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#define HCLK_USBOTG0_PMU 96
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#define CLK_USBOTG0_ADP 97
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#define HCLK_USBOTG1 98
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#define HCLK_USBOTG1_PMU 99
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#define CLK_USBOTG1_ADP 100
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#define PCLK_USBPHY 101
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#define ACLK_DMA2DDR 102
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#define PCLK_DMA2DDR 103
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#define STCLK_M0 104
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#define CLK_DDRPHY 105
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#define CLK_DDRC_SRC 106
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#define ACLK_DDRC_0 107
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#define ACLK_DDRC_1 108
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#define CLK_DDRC 109
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#define CLK_DDRMON 110
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#define HCLK_LSPERI_ROOT 111
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#define PCLK_LSPERI_ROOT 112
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#define PCLK_UART0 113
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#define PCLK_UART1 114
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#define PCLK_UART2 115
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#define PCLK_UART3 116
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#define PCLK_UART4 117
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#define SCLK_UART0 118
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#define SCLK_UART1 119
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#define SCLK_UART2 120
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#define SCLK_UART3 121
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#define SCLK_UART4 122
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#define PCLK_I2C0 123
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#define CLK_I2C0 124
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#define PCLK_I2C1 125
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#define CLK_I2C1 126
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#define PCLK_I2C2 127
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#define CLK_I2C2 128
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#define PCLK_PWM1 129
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#define CLK_PWM1 130
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#define CLK_OSC_PWM1 131
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#define CLK_RC_PWM1 132
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#define CLK_FREQ_PWM1 133
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#define CLK_COUNTER_PWM1 134
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#define PCLK_SPI0 135
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#define CLK_SPI0 136
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#define PCLK_SPI1 137
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#define CLK_SPI1 138
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#define PCLK_GPIO2 139
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#define DBCLK_GPIO2 140
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#define PCLK_GPIO3 141
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#define DBCLK_GPIO3 142
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#define PCLK_GPIO4 143
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#define DBCLK_GPIO4 144
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#define HCLK_CAN0 145
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#define CLK_CAN0 146
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#define HCLK_CAN1 147
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#define CLK_CAN1 148
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#define HCLK_PDM 149
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#define MCLK_PDM 150
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#define CLKOUT_PDM 151
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#define MCLK_SPDIFTX 152
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#define HCLK_SPDIFTX 153
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#define HCLK_SPDIFRX 154
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#define MCLK_SPDIFRX 155
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#define MCLK_SAI0 156
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#define HCLK_SAI0 157
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#define MCLK_OUT_SAI0 158
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#define MCLK_SAI1 159
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#define HCLK_SAI1 160
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#define MCLK_OUT_SAI1 161
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#define HCLK_ASRC0 162
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#define CLK_ASRC0 163
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#define HCLK_ASRC1 164
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#define CLK_ASRC1 165
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#define PCLK_CRU 166
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#define PCLK_PMU_ROOT 167
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#define MCLK_ASRC0 168
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#define MCLK_ASRC1 169
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#define MCLK_ASRC2 170
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#define MCLK_ASRC3 171
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#define LRCK_ASRC0_SRC 172
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#define LRCK_ASRC0_DST 173
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#define LRCK_ASRC1_SRC 174
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#define LRCK_ASRC1_DST 175
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#define ACLK_HSPERI_ROOT 176
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#define HCLK_HSPERI_ROOT 177
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#define PCLK_HSPERI_ROOT 178
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#define CCLK_SRC_SDMMC 179
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#define HCLK_SDMMC 180
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#define HCLK_FSPI 181
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#define SCLK_FSPI 182
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#define PCLK_SPI2 183
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#define ACLK_MAC0 184
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#define ACLK_MAC1 185
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#define PCLK_MAC0 186
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#define PCLK_MAC1 187
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#define CLK_MAC_ROOT 188
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#define CLK_MAC0 189
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#define CLK_MAC1 190
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#define MCLK_SAI2 191
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#define HCLK_SAI2 192
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#define MCLK_OUT_SAI2 193
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#define MCLK_SAI3_SRC 194
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#define HCLK_SAI3 195
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#define MCLK_SAI3 196
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#define MCLK_OUT_SAI3 197
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#define MCLK_SAI4_SRC 198
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#define HCLK_SAI4 199
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#define MCLK_SAI4 200
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#define HCLK_DSM 201
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#define MCLK_DSM 202
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#define PCLK_AUDIO_ADC 203
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#define MCLK_AUDIO_ADC 204
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#define MCLK_AUDIO_ADC_DIV4 205
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#define PCLK_SARADC 206
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#define CLK_SARADC 207
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#define PCLK_OTPC_NS 208
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#define CLK_SBPI_OTPC_NS 209
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#define CLK_USER_OTPC_NS 210
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#define PCLK_UART5 211
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#define SCLK_UART5 212
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#define PCLK_GPIO234_IOC 213
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#define CLK_MAC_PTP_ROOT 214
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#define CLK_MAC0_PTP 215
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#define CLK_MAC1_PTP 216
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#define CLK_SPI2 217
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#define ACLK_VIO_ROOT 218
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#define HCLK_VIO_ROOT 219
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#define PCLK_VIO_ROOT 220
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#define HCLK_RGA 221
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#define ACLK_RGA 222
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#define CLK_CORE_RGA 223
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#define ACLK_VOP 224
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#define HCLK_VOP 225
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#define DCLK_VOP 226
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#define PCLK_DPHY 227
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#define PCLK_DSI_HOST 228
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#define PCLK_TSADC 229
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#define CLK_TSADC 230
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#define CLK_TSADC_TSEN 231
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#define PCLK_GPIO1_IOC 232
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#define PCLK_OTPC_S 233
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#define CLK_SBPI_OTPC_S 234
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#define CLK_USER_OTPC_S 235
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#define PCLK_OTP_MASK 236
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#define PCLK_KEYREADER 237
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#define HCLK_BOOTROM 238
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#define PCLK_DDR_SERVICE 239
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#define HCLK_CRYPTO_S 240
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#define HCLK_KEYLAD 241
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#define CLK_CORE_CRYPTO 242
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#define CLK_PKA_CRYPTO 243
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#define CLK_CORE_CRYPTO_S 244
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#define CLK_PKA_CRYPTO_S 245
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#define ACLK_CRYPTO_S 246
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#define HCLK_RNG_S 247
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#define CLK_CORE_CRYPTO_NS 248
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#define CLK_PKA_CRYPTO_NS 249
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#define ACLK_CRYPTO_NS 250
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#define HCLK_CRYPTO_NS 251
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#define HCLK_RNG 252
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#define CLK_PMU 253
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#define PCLK_PMU 254
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#define CLK_PMU_32K 255
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#define PCLK_PMU_CRU 256
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#define PCLK_PMU_GRF 257
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#define PCLK_GPIO0_IOC 258
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#define PCLK_GPIO0 259
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#define DBCLK_GPIO0 260
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#define PCLK_GPIO1_SHADOW 261
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#define DBCLK_GPIO1_SHADOW 262
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#define PCLK_PMU_HP_TIMER 263
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#define CLK_PMU_HP_TIMER 264
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#define CLK_PMU_HP_TIMER_32K 265
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#define PCLK_PWM0 266
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#define CLK_PWM0 267
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#define CLK_OSC_PWM0 268
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#define CLK_RC_PWM0 269
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#define CLK_MAC_OUT 270
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#define CLK_REF_OUT0 271
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#define CLK_REF_OUT1 272
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#define CLK_32K_FRAC 273
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#define CLK_32K_RC 274
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#define CLK_32K 275
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#define CLK_32K_PMU 276
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#define PCLK_TOUCH_KEY 277
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#define CLK_TOUCH_KEY 278
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#define CLK_REF_PHY_PLL 279
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#define CLK_REF_PHY_PMU_MUX 280
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#define CLK_WIFI_OUT 281
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#define CLK_V0PLL_REF 282
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#define CLK_V1PLL_REF 283
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#define CLK_NR_CLKS (CLK_V1PLL_REF + 1)
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/* soft-reset indices */
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/********Name=SOFTRST_CON00,Offset=0xA00********/
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#define SRST_NCOREPORESET0_AC 0
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#define SRST_NCOREPORESET1_AC 1
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#define SRST_NCOREPORESET2_AC 2
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#define SRST_NCORESET0_AC 4
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#define SRST_NCORESET1_AC 5
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#define SRST_NCORESET2_AC 6
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#define SRST_NL2RESET_AC 8
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#define SRST_ARESETN_CORE_BIU_AC 9
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#define SRST_HRESETN_M0_AC 10
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/********Name=SOFTRST_CON02,Offset=0xA08********/
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#define SRST_N_DBG 42
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#define SRST_P_CORE_BIU 46
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#define SRST_PMU 47
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/********Name=SOFTRST_CON03,Offset=0xA0C********/
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#define SRST_P_DBG 49
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#define SRST_POT_DBG 50
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#define SRST_P_CORE_GRF 52
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#define SRST_CORE_EMA_DETECT 54
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#define SRST_REF_PVTPLL_CORE 55
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#define SRST_P_GPIO1 56
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#define SRST_DB_GPIO1 57
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/********Name=SOFTRST_CON04,Offset=0xA10********/
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#define SRST_A_CORE_PERI_BIU 67
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#define SRST_A_DSMC 69
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#define SRST_P_DSMC 70
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#define SRST_FLEXBUS 71
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#define SRST_A_FLEXBUS 73
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#define SRST_H_FLEXBUS 74
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#define SRST_A_DSMC_SLV 75
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#define SRST_H_DSMC_SLV 76
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#define SRST_DSMC_SLV 77
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/********Name=SOFTRST_CON05,Offset=0xA14********/
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#define SRST_A_BUS_BIU 83
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#define SRST_H_BUS_BIU 84
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#define SRST_P_BUS_BIU 85
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#define SRST_A_SYSTEM 86
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#define SRST_H_SySTEM 87
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#define SRST_A_DMAC0 88
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#define SRST_A_DMAC1 89
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#define SRST_H_M0 90
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#define SRST_M0_JTAG 91
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#define SRST_H_CRYPTO 95
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/********Name=SOFTRST_CON06,Offset=0xA18********/
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#define SRST_H_RNG 96
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#define SRST_P_BUS_GRF 97
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#define SRST_P_TIMER0 98
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#define SRST_TIMER0_CH0 99
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#define SRST_TIMER0_CH1 100
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#define SRST_TIMER0_CH2 101
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#define SRST_TIMER0_CH3 102
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#define SRST_TIMER0_CH4 103
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#define SRST_TIMER0_CH5 104
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#define SRST_P_WDT0 105
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#define SRST_T_WDT0 106
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#define SRST_P_WDT1 107
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#define SRST_T_WDT1 108
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#define SRST_P_MAILBOX 109
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#define SRST_P_INTMUX 110
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#define SRST_P_SPINLOCK 111
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/********Name=SOFTRST_CON07,Offset=0xA1C********/
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#define SRST_P_DDRC 112
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#define SRST_H_DDRPHY 113
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#define SRST_P_DDRMON 114
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#define SRST_DDRMON_OSC 115
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#define SRST_P_DDR_LPC 116
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#define SRST_H_USBOTG0 117
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#define SRST_USBOTG0_ADP 119
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#define SRST_H_USBOTG1 120
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#define SRST_USBOTG1_ADP 122
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#define SRST_P_USBPHY 123
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#define SRST_USBPHY_POR 124
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#define SRST_USBPHY_OTG0 125
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#define SRST_USBPHY_OTG1 126
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/********Name=SOFTRST_CON08,Offset=0xA20********/
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#define SRST_A_DMA2DDR 128
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#define SRST_P_DMA2DDR 129
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/********Name=SOFTRST_CON09,Offset=0xA24********/
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#define SRST_USBOTG0_UTMI 144
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#define SRST_USBOTG1_UTMI 145
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/********Name=SOFTRST_CON10,Offset=0xA28********/
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#define SRST_A_DDRC_0 160
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#define SRST_A_DDRC_1 161
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#define SRST_A_DDR_BIU 162
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#define SRST_DDRC 163
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#define SRST_DDRMON 164
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/********Name=SOFTRST_CON11,Offset=0xA2C********/
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#define SRST_H_LSPERI_BIU 178
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#define SRST_P_UART0 180
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#define SRST_P_UART1 181
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#define SRST_P_UART2 182
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#define SRST_P_UART3 183
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#define SRST_P_UART4 184
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#define SRST_UART0 185
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#define SRST_UART1 186
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#define SRST_UART2 187
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#define SRST_UART3 188
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#define SRST_UART4 189
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#define SRST_P_I2C0 190
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#define SRST_I2C0 191
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/********Name=SOFTRST_CON12,Offset=0xA30********/
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#define SRST_P_I2C1 192
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#define SRST_I2C1 193
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#define SRST_P_I2C2 194
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#define SRST_I2C2 195
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#define SRST_P_PWM1 196
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#define SRST_PWM1 197
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#define SRST_P_SPI0 202
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#define SRST_SPI0 203
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#define SRST_P_SPI1 204
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#define SRST_SPI1 205
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#define SRST_P_GPIO2 206
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#define SRST_DB_GPIO2 207
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/********Name=SOFTRST_CON13,Offset=0xA34********/
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#define SRST_P_GPIO3 208
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#define SRST_DB_GPIO3 209
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#define SRST_P_GPIO4 210
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#define SRST_DB_GPIO4 211
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#define SRST_H_CAN0 212
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#define SRST_CAN0 213
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#define SRST_H_CAN1 214
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#define SRST_CAN1 215
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#define SRST_H_PDM 216
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#define SRST_M_PDM 217
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#define SRST_PDM 218
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#define SRST_SPDIFTX 219
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#define SRST_H_SPDIFTX 220
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#define SRST_H_SPDIFRX 221
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#define SRST_SPDIFRX 222
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#define SRST_M_SAI0 223
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/********Name=SOFTRST_CON14,Offset=0xA38********/
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#define SRST_H_SAI0 224
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#define SRST_M_SAI1 226
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#define SRST_H_SAI1 227
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#define SRST_H_ASRC0 229
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#define SRST_ASRC0 230
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#define SRST_H_ASRC1 231
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#define SRST_ASRC1 232
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/********Name=SOFTRST_CON17,Offset=0xA44********/
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#define SRST_H_HSPERI_BIU 276
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#define SRST_H_SDMMC 279
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#define SRST_H_FSPI 280
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#define SRST_S_FSPI 281
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#define SRST_P_SPI2 282
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#define SRST_A_MAC0 283
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#define SRST_A_MAC1 284
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/********Name=SOFTRST_CON18,Offset=0xA48********/
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#define SRST_M_SAI2 290
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#define SRST_H_SAI2 291
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#define SRST_H_SAI3 294
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#define SRST_M_SAI3 295
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#define SRST_H_SAI4 298
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#define SRST_M_SAI4 299
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#define SRST_H_DSM 300
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#define SRST_M_DSM 301
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#define SRST_P_AUDIO_ADC 302
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#define SRST_M_AUDIO_ADC 303
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/********Name=SOFTRST_CON19,Offset=0xA4C********/
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#define SRST_P_SARADC 304
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#define SRST_SARADC 305
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#define SRST_SARADC_PHY 306
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#define SRST_P_OTPC_NS 307
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#define SRST_SBPI_OTPC_NS 308
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#define SRST_USER_OTPC_NS 309
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#define SRST_P_UART5 310
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#define SRST_UART5 311
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#define SRST_P_GPIO234_IOC 312
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/********Name=SOFTRST_CON21,Offset=0xA54********/
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#define SRST_A_VIO_BIU 339
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#define SRST_H_VIO_BIU 340
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#define SRST_H_RGA 342
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#define SRST_A_RGA 343
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#define SRST_CORE_RGA 344
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#define SRST_A_VOP 345
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#define SRST_H_VOP 346
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#define SRST_VOP 347
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#define SRST_P_DPHY 348
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#define SRST_P_DSI_HOST 349
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#define SRST_P_TSADC 350
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#define SRST_TSADC 351
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/********Name=SOFTRST_CON22,Offset=0xA58********/
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#define SRST_P_GPIO1_IOC 353
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#endif
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