656 lines
17 KiB
C
656 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Rockchip UFS Host Controller driver
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*
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* Copyright (C) 2024 Rockchip Electronics Co.Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/gpio.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <ufs/ufshcd.h>
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#include <ufs/unipro.h>
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#include "ufshcd-pltfrm.h"
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#include "ufshcd-dwc.h"
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#include "ufs-rockchip.h"
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static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
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{
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return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE;
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}
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static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
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{
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return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT;
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}
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#ifdef MODULE
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static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
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{
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#define MIN_DELAY_BEFORE_DME_CMDS_US 1000
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unsigned long min_sleep_time_us;
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if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
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return;
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/*
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* last_dme_cmd_tstamp will be 0 only for 1st call to
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* this function
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*/
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if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
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min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
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} else {
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unsigned long delta =
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(unsigned long) ktime_to_us(
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ktime_sub(ktime_get(),
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hba->last_dme_cmd_tstamp));
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if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
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min_sleep_time_us =
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MIN_DELAY_BEFORE_DME_CMDS_US - delta;
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else
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return; /* no more delay required */
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}
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/* allow sleep for extra 50us if needed */
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usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
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}
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#define UIC_CMD_TIMEOUT 500
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static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
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{
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u32 val;
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int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY,
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500, UIC_CMD_TIMEOUT * 1000, false, hba,
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REG_CONTROLLER_STATUS);
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return ret == 0 ? true : false;
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}
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static inline void
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ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
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{
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lockdep_assert_held(&hba->uic_cmd_mutex);
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WARN_ON(hba->active_uic_cmd);
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hba->active_uic_cmd = uic_cmd;
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/* Write Args */
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ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
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ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
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ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
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/* Write UIC Cmd */
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ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
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REG_UIC_COMMAND);
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}
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static int
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ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
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{
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int ret;
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unsigned long flags;
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lockdep_assert_held(&hba->uic_cmd_mutex);
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if (wait_for_completion_timeout(&uic_cmd->done,
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msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
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ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
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} else {
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ret = -ETIMEDOUT;
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dev_err(hba->dev,
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"uic cmd 0x%x with arg3 0x%x completion timeout\n",
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uic_cmd->command, uic_cmd->argument3);
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if (!uic_cmd->cmd_active) {
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dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
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__func__);
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ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
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}
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}
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spin_lock_irqsave(hba->host->host_lock, flags);
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hba->active_uic_cmd = NULL;
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spin_unlock_irqrestore(hba->host->host_lock, flags);
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return ret;
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}
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static int
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__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
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bool completion)
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{
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lockdep_assert_held(&hba->uic_cmd_mutex);
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if (!ufshcd_ready_for_uic_cmd(hba)) {
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dev_err(hba->dev,
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"Controller not ready to accept UIC commands\n");
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return -EIO;
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}
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if (completion)
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init_completion(&uic_cmd->done);
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uic_cmd->cmd_active = 1;
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ufshcd_dispatch_uic_cmd(hba, uic_cmd);
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return 0;
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}
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static int ufs_rockchip_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
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{
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int ret;
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if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
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return 0;
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ufshcd_hold(hba, false);
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mutex_lock(&hba->uic_cmd_mutex);
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ufshcd_add_delay_before_dme_cmd(hba);
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ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
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if (!ret)
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ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
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mutex_unlock(&hba->uic_cmd_mutex);
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ufshcd_release(hba);
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return ret;
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}
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#endif /* MODULE */
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static int ufshcd_dme_link_startup(struct ufs_hba *hba)
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{
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struct uic_command uic_cmd = {0};
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int ret;
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uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
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#ifdef MODULE
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ret = ufs_rockchip_send_uic_cmd(hba, &uic_cmd);
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#else
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ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
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#endif
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if (ret)
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dev_err(hba->dev,
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"dme-link-startup: error code %d\n", ret);
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return ret;
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}
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static void ufs_rockchip_controller_reset(struct ufs_rockchip_host *host)
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{
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reset_control_assert(host->rst);
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udelay(1);
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reset_control_deassert(host->rst);
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}
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static int ufs_rockchip_hce_enable_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status)
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{
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struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
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int err = 0;
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if (status == PRE_CHANGE) {
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int retry_outer = 3;
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int retry_inner;
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ufs_rockchip_controller_reset(host);
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start:
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if (ufshcd_is_hba_active(hba))
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/* change controller state to "reset state" */
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ufshcd_hba_stop(hba);
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/* UniPro link is disabled at this point */
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ufshcd_set_link_off(hba);
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/* start controller initialization sequence */
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ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
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usleep_range(100, 200);
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/* wait for the host controller to complete initialization */
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retry_inner = 50;
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while (!ufshcd_is_hba_active(hba)) {
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if (retry_inner) {
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retry_inner--;
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} else {
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dev_err(hba->dev,
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"Controller enable failed\n");
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if (retry_outer) {
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retry_outer--;
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goto start;
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}
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return -EIO;
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}
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usleep_range(1000, 1100);
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}
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} else { /* POST_CHANGE */
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err = ufshcd_vops_phy_initialization(hba);
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}
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return err;
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}
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static void ufs_rockchip_set_pm_lvl(struct ufs_hba *hba)
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{
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hba->rpm_lvl = UFS_PM_LVL_1;
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hba->spm_lvl = UFS_PM_LVL_3;
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}
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static const unsigned char rk3576_phy_value[15][4] = {
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{0x03, 0x38, 0x50, 0x80},
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{0x03, 0x14, 0x58, 0x80},
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{0x03, 0x26, 0x58, 0x80},
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{0x03, 0x49, 0x58, 0x80},
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{0x03, 0x5A, 0x58, 0x80},
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{0xC3, 0x38, 0x50, 0xC0},
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{0xC3, 0x14, 0x58, 0xC0},
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{0xC3, 0x26, 0x58, 0xC0},
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{0xC3, 0x49, 0x58, 0xC0},
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{0xC3, 0x5A, 0x58, 0xC0},
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{0x43, 0x38, 0x50, 0xC0},
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{0x43, 0x14, 0x58, 0xC0},
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{0x43, 0x26, 0x58, 0xC0},
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{0x43, 0x49, 0x58, 0xC0},
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{0x43, 0x5A, 0x58, 0xC0}
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};
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static int ufs_rockchip_rk3576_phy_init(struct ufs_hba *hba)
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{
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struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
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u32 try_case = host->phy_config_mode, value;
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if (try_case >= ARRAY_SIZE(rk3576_phy_value))
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try_case = 0;
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(PA_LOCAL_TX_LCC_ENABLE, 0x0), 0x0);
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/* enable the mphy DME_SET cfg */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x200, 0x0), 0x40);
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for (int i = 0; i < 2; i++) {
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/* Configuration M-TX */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xaa, SEL_TX_LANE0 + i), 0x06);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xa9, SEL_TX_LANE0 + i), 0x02);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xad, SEL_TX_LANE0 + i), 0x44);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xac, SEL_TX_LANE0 + i), 0xe6);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xab, SEL_TX_LANE0 + i), 0x07);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x94, SEL_TX_LANE0 + i), 0x93);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x93, SEL_TX_LANE0 + i), 0xc9);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7f, SEL_TX_LANE0 + i), 0x00);
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/* Configuration M-RX */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, SEL_RX_LANE0 + i), 0x06);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x11, SEL_RX_LANE0 + i), 0x00);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, SEL_RX_LANE0 + i), 0x58);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, SEL_RX_LANE0 + i), 0x8c);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, SEL_RX_LANE0 + i), 0x02);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, SEL_RX_LANE0 + i), 0xf6);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, SEL_RX_LANE0 + i), 0x69);
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}
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/* disable the mphy DME_SET cfg */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x200, 0x0), 0x00);
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ufs_sys_writel(host->mphy_base, 0x80, 0x08C);
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ufs_sys_writel(host->mphy_base, 0xB5, 0x110);
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ufs_sys_writel(host->mphy_base, 0xB5, 0x250);
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value = rk3576_phy_value[try_case][0];
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ufs_sys_writel(host->mphy_base, value, 0x134);
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ufs_sys_writel(host->mphy_base, value, 0x274);
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value = rk3576_phy_value[try_case][1];
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ufs_sys_writel(host->mphy_base, value, 0x0E0);
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ufs_sys_writel(host->mphy_base, value, 0x220);
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value = rk3576_phy_value[try_case][2];
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ufs_sys_writel(host->mphy_base, value, 0x164);
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ufs_sys_writel(host->mphy_base, value, 0x2A4);
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value = rk3576_phy_value[try_case][3];
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ufs_sys_writel(host->mphy_base, value, 0x178);
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ufs_sys_writel(host->mphy_base, value, 0x2B8);
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ufs_sys_writel(host->mphy_base, 0x18, 0x1B0);
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ufs_sys_writel(host->mphy_base, 0x18, 0x2F0);
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ufs_sys_writel(host->mphy_base, 0x03, 0x128);
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ufs_sys_writel(host->mphy_base, 0x03, 0x268);
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ufs_sys_writel(host->mphy_base, 0x20, 0x12C);
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ufs_sys_writel(host->mphy_base, 0x20, 0x26C);
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ufs_sys_writel(host->mphy_base, 0xC0, 0x120);
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ufs_sys_writel(host->mphy_base, 0xC0, 0x260);
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ufs_sys_writel(host->mphy_base, 0x03, 0x094);
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ufs_sys_writel(host->mphy_base, 0x03, 0x1B4);
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ufs_sys_writel(host->mphy_base, 0x03, 0x2F4);
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ufs_sys_writel(host->mphy_base, 0xC0, 0x08C);
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udelay(1);
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ufs_sys_writel(host->mphy_base, 0x00, 0x08C);
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udelay(200);
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/* start link up */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_TX_ENDIAN, 0), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_RX_ENDIAN, 0), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID, 0), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID_VALID, 0), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_PEERDEVICEID, 0), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_CONNECTIONSTATE, 0), 0x1);
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return 0;
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}
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static int ufs_rockchip_common_init(struct ufs_hba *hba)
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{
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struct device *dev = hba->dev;
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struct platform_device *pdev = to_platform_device(dev);
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struct ufs_rockchip_host *host;
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int err = 0;
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host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
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if (!host)
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return -ENOMEM;
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/* system control register for hci */
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host->ufs_sys_ctrl = devm_platform_ioremap_resource_byname(pdev, "hci_grf");
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if (IS_ERR(host->ufs_sys_ctrl)) {
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dev_err(dev, "cannot ioremap for hci system control register\n");
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return PTR_ERR(host->ufs_sys_ctrl);
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}
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/* system control register for mphy */
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host->ufs_phy_ctrl = devm_platform_ioremap_resource_byname(pdev, "mphy_grf");
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if (IS_ERR(host->ufs_phy_ctrl)) {
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dev_err(dev, "cannot ioremap for mphy system control register\n");
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return PTR_ERR(host->ufs_phy_ctrl);
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}
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/* mphy base register */
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host->mphy_base = devm_platform_ioremap_resource_byname(pdev, "mphy");
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if (IS_ERR(host->mphy_base)) {
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dev_err(dev, "cannot ioremap for mphy base register\n");
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return PTR_ERR(host->mphy_base);
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}
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host->rst = devm_reset_control_array_get_exclusive(dev);
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if (IS_ERR(host->rst)) {
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dev_err(dev, "failed to get reset control\n");
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return PTR_ERR(host->rst);
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}
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ufs_rockchip_controller_reset(host);
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host->ref_out_clk = devm_clk_get(dev, "ref_out");
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if (IS_ERR(host->ref_out_clk)) {
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dev_err(dev, "ciu-drive not available\n");
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return PTR_ERR(host->ref_out_clk);
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}
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err = clk_prepare_enable(host->ref_out_clk);
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if (err) {
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dev_err(dev, "failed to enable ref out clock %d\n", err);
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return err;
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}
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host->rst_gpio = devm_gpiod_get(&pdev->dev, "reset", GPIOD_OUT_LOW);
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if (IS_ERR(host->rst_gpio)) {
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dev_err(&pdev->dev, "invalid reset-gpios property in node\n");
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err = PTR_ERR(host->rst_gpio);
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goto out;
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}
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udelay(20);
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gpiod_set_value_cansleep(host->rst_gpio, 1);
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host->clks[0].id = "core";
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host->clks[1].id = "pclk";
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host->clks[2].id = "pclk_mphy";
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err = devm_clk_bulk_get_optional(dev, UFS_MAX_CLKS, host->clks);
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if (err) {
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dev_err(dev, "failed to get clocks %d\n", err);
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goto out;
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}
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err = clk_bulk_prepare_enable(UFS_MAX_CLKS, host->clks);
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if (err) {
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dev_err(dev, "failed to enable clocks %d\n", err);
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goto out;
|
|
}
|
|
|
|
if (device_property_read_u32(dev, "ufs-phy-config-mode",
|
|
&host->phy_config_mode))
|
|
host->phy_config_mode = 0;
|
|
|
|
pm_runtime_set_active(&pdev->dev);
|
|
|
|
host->hba = hba;
|
|
ufs_rockchip_set_pm_lvl(hba);
|
|
|
|
ufshcd_set_variant(hba, host);
|
|
|
|
return 0;
|
|
out:
|
|
clk_disable_unprepare(host->ref_out_clk);
|
|
return err;
|
|
}
|
|
|
|
static int ufs_rockchip_rk3576_init(struct ufs_hba *hba)
|
|
{
|
|
int ret = 0;
|
|
struct device *dev = hba->dev;
|
|
|
|
hba->quirks = UFSHCI_QUIRK_BROKEN_HCE | UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING;
|
|
|
|
/* Enable BKOPS when suspend */
|
|
hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
|
|
/* Enable putting device into deep sleep */
|
|
hba->caps |= UFSHCD_CAP_DEEPSLEEP;
|
|
/* Enable WriteBooster */
|
|
hba->caps |= UFSHCD_CAP_WB_EN;
|
|
|
|
ret = ufs_rockchip_common_init(hba);
|
|
if (ret) {
|
|
dev_err(dev, "ufs common init fail\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ufs_rockchip_device_reset(struct ufs_hba *hba)
|
|
{
|
|
struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
|
|
|
|
if (!host->rst_gpio)
|
|
return -EOPNOTSUPP;
|
|
|
|
gpiod_set_value_cansleep(host->rst_gpio, 0);
|
|
udelay(20);
|
|
|
|
gpiod_set_value_cansleep(host->rst_gpio, 1);
|
|
udelay(20);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct ufs_hba_variant_ops ufs_hba_rk3576_vops = {
|
|
.name = "rk3576",
|
|
.init = ufs_rockchip_rk3576_init,
|
|
.device_reset = ufs_rockchip_device_reset,
|
|
.hce_enable_notify = ufs_rockchip_hce_enable_notify,
|
|
.phy_initialization = ufs_rockchip_rk3576_phy_init,
|
|
};
|
|
|
|
static const struct of_device_id ufs_rockchip_of_match[] = {
|
|
{ .compatible = "rockchip,rk3576-ufs", .data = &ufs_hba_rk3576_vops},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ufs_rockchip_of_match);
|
|
|
|
static int ufs_rockchip_probe(struct platform_device *pdev)
|
|
{
|
|
int err;
|
|
struct device *dev = &pdev->dev;
|
|
const struct ufs_hba_variant_ops *vops;
|
|
|
|
vops = device_get_match_data(dev);
|
|
err = ufshcd_pltfrm_init(pdev, vops);
|
|
if (err)
|
|
dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int ufs_rockchip_remove(struct platform_device *pdev)
|
|
{
|
|
struct ufs_hba *hba = platform_get_drvdata(pdev);
|
|
struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
|
|
|
|
pm_runtime_forbid(&pdev->dev);
|
|
pm_runtime_get_noresume(&pdev->dev);
|
|
ufshcd_remove(hba);
|
|
ufshcd_dealloc_host(hba);
|
|
clk_disable_unprepare(host->ref_out_clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ufs_rockchip_restore_link(struct ufs_hba *hba, bool is_store)
|
|
{
|
|
struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
|
|
int err, retry = 3;
|
|
|
|
if (is_store) {
|
|
host->ie = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
|
|
host->ahit = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
|
|
return 0;
|
|
}
|
|
|
|
/* Enable controller */
|
|
err = ufshcd_hba_enable(hba);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Link startup and wait for DP */
|
|
do {
|
|
err = ufshcd_dme_link_startup(hba);
|
|
if (!err && ufshcd_is_device_present(hba)) {
|
|
dev_dbg_ratelimited(hba->dev, "rockchip link startup successfully.\n");
|
|
break;
|
|
}
|
|
} while (retry--);
|
|
|
|
if (retry < 0) {
|
|
dev_err(hba->dev, "rockchip link startup failed.\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
/* Restore negotiated power mode */
|
|
err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
|
|
if (err)
|
|
dev_err(hba->dev, "Failed to restore power mode, err = %d\n", err);
|
|
|
|
/* Restore task and transfer list */
|
|
ufshcd_writel(hba, 0xffffffff, REG_INTERRUPT_STATUS);
|
|
ufshcd_make_hba_operational(hba);
|
|
|
|
/* Restore lost regs */
|
|
ufshcd_writel(hba, host->ie, REG_INTERRUPT_ENABLE);
|
|
ufshcd_writel(hba, host->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
|
|
ufshcd_writel(hba, 0x1, REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
|
|
ufshcd_writel(hba, 0x1, REG_UTP_TASK_REQ_LIST_RUN_STOP);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int ufs_rockchip_runtime_suspend(struct device *dev)
|
|
{
|
|
struct ufs_hba *hba = dev_get_drvdata(dev);
|
|
struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
|
|
|
|
clk_disable_unprepare(host->ref_out_clk);
|
|
return ufs_rockchip_restore_link(hba, true);
|
|
}
|
|
|
|
static int ufs_rockchip_runtime_resume(struct device *dev)
|
|
{
|
|
struct ufs_hba *hba = dev_get_drvdata(dev);
|
|
struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
|
|
int err;
|
|
|
|
err = clk_prepare_enable(host->ref_out_clk);
|
|
if (err) {
|
|
dev_err(hba->dev, "failed to enable ref out clock %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
reset_control_assert(host->rst);
|
|
udelay(1);
|
|
reset_control_deassert(host->rst);
|
|
|
|
return ufs_rockchip_restore_link(hba, false);
|
|
}
|
|
|
|
static int ufs_rockchip_suspend(struct device *dev)
|
|
{
|
|
struct ufs_hba *hba = dev_get_drvdata(dev);
|
|
|
|
if (pm_runtime_suspended(hba->dev))
|
|
return 0;
|
|
|
|
ufs_rockchip_restore_link(hba, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ufs_rockchip_resume(struct device *dev)
|
|
{
|
|
struct ufs_hba *hba = dev_get_drvdata(dev);
|
|
|
|
if (pm_runtime_suspended(hba->dev))
|
|
return 0;
|
|
|
|
/* Reset device if possible */
|
|
ufs_rockchip_device_reset(hba);
|
|
ufs_rockchip_restore_link(hba, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ufs_rockchip_shutdown(struct platform_device *pdev)
|
|
{
|
|
struct ufs_hba *hba = platform_get_drvdata(pdev);
|
|
|
|
dev_info(&pdev->dev, "shutting down...\n");
|
|
|
|
ufshcd_pltfrm_shutdown(pdev);
|
|
ufs_rockchip_device_reset(hba);
|
|
}
|
|
|
|
static const struct dev_pm_ops ufs_rockchip_pm_ops = {
|
|
SYSTEM_SLEEP_PM_OPS(ufs_rockchip_suspend, ufs_rockchip_resume)
|
|
RUNTIME_PM_OPS(ufs_rockchip_runtime_suspend, ufs_rockchip_runtime_resume, NULL)
|
|
.prepare = ufshcd_suspend_prepare,
|
|
.complete = ufshcd_resume_complete,
|
|
};
|
|
|
|
static struct platform_driver ufs_rockchip_pltform = {
|
|
.probe = ufs_rockchip_probe,
|
|
.remove = ufs_rockchip_remove,
|
|
.shutdown = ufs_rockchip_shutdown,
|
|
.driver = {
|
|
.name = "ufshcd-rockchip",
|
|
.pm = pm_ptr(&ufs_rockchip_pm_ops),
|
|
.of_match_table = of_match_ptr(ufs_rockchip_of_match),
|
|
},
|
|
};
|
|
module_platform_driver(ufs_rockchip_pltform);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("Rockchip UFS Host Driver");
|