82 lines
1.5 KiB
C
82 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Rockchip Samsung mipi dcphy driver
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*
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* Copyright (C) 2020 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _PHY_ROCKCHIP_SAMSUNG_DCPHY_H_
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#define _PHY_ROCKCHIP_SAMSUNG_DCPHY_H_
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#define MAX_NUM_CSI2_DPHY (0x2)
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enum hs_drv_res_ohm {
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_30_OHM = 0x8,
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_31_2_OHM,
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_32_5_OHM,
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_34_OHM,
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_35_5_OHM,
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_37_OHM,
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_39_OHM,
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_41_OHM,
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_43_OHM = 0x0,
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_46_OHM,
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_49_OHM,
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_52_OHM,
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_56_OHM,
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_60_OHM,
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_66_OHM,
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_73_OHM,
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};
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struct hs_drv_res_cfg {
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enum hs_drv_res_ohm clk_hs_drv_up_ohm;
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enum hs_drv_res_ohm clk_hs_drv_down_ohm;
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enum hs_drv_res_ohm data_hs_drv_up_ohm;
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enum hs_drv_res_ohm data_hs_drv_down_ohm;
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};
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struct samsung_mipi_dcphy_plat_data {
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const struct hs_drv_res_cfg *dphy_hs_drv_res_cfg;
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u32 dphy_tx_max_kbps_per_lane;
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u32 cphy_tx_max_ksps_per_lane;
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};
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struct samsung_mipi_dcphy {
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struct device *dev;
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struct clk *ref_clk;
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struct clk *pclk;
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struct regmap *regmap;
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struct regmap *grf_regmap;
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struct reset_control *m_phy_rst;
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struct reset_control *s_phy_rst;
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struct reset_control *apb_rst;
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struct reset_control *grf_apb_rst;
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struct mutex mutex;
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struct csi2_dphy *dphy_dev[MAX_NUM_CSI2_DPHY];
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atomic_t stream_cnt;
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int dphy_dev_num;
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bool c_option;
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unsigned int lanes;
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const struct samsung_mipi_dcphy_plat_data *pdata;
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struct {
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unsigned long long rate;
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u8 prediv;
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u16 fbdiv;
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u16 dsm;
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u8 scaler;
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bool ssc_en;
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u8 mfr;
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u8 mrr;
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} pll;
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int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
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int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
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struct resource *res;
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};
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#endif
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