561 lines
20 KiB
C
Executable File
561 lines
20 KiB
C
Executable File
/*++
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Copyright (c) 2021 Motor-comm Corporation.
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Confidential and Proprietary. All rights reserved.
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This is Motor-comm Corporation NIC driver relevant files.
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Please don't copy, modify,distribute without commercial permission.
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--*/
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#ifndef __FUXI_OS_H__
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#define __FUXI_OS_H__
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#include <linux/dma-mapping.h>
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#include <linux/netdevice.h>
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#include <linux/workqueue.h>
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#include <linux/phy.h>
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#include <linux/if_vlan.h>
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#include <linux/bitops.h>
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#include <linux/timecounter.h>
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#ifdef CONFIG_PCI_MSI
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#include <linux/pci.h>
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#endif
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#include <linux/pm_wakeup.h>
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#include <linux/mdio.h>
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#include <linux/clk.h>
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#include <linux/bitrev.h>
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#include <linux/crc32.h>
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#include <linux/dcbnl.h>
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#include <linux/inet.h>
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#define LINUX
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#ifndef LINUX_VERSION_CODE
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#include <linux/version.h>
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#else
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#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
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#endif
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,19,0))
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#include <linux/crc32poly.h>
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#endif
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#include "fuxi-dbg.h"
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struct fxgmac_ring;
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struct fxgmac_pdata;
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#define FXGMAC_DRV_VERSION "1.0.27"
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#ifdef CONFIG_PCI_MSI
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//#undef CONFIG_PCI_MSI //undefined for legacy interupt mode
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#endif
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#define PCIE_LP_ASPM_L0S 1
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#define PCIE_LP_ASPM_L1 2
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#define PCIE_LP_ASPM_L1SS 4
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#define PCIE_LP_ASPM_LTR 8
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,19,0))
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/*
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* There are multiple 16-bit CRC polynomials in common use, but this is
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* *the* standard CRC-32 polynomial, first popularized by Ethernet.
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* x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x^1+x^0
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*/
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#define CRC32_POLY_LE 0xedb88320
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#define CRC32_POLY_BE 0x04c11db7
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/*
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* This is the CRC32c polynomial, as outlined by Castagnoli.
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* x^32+x^28+x^27+x^26+x^25+x^23+x^22+x^20+x^19+x^18+x^14+x^13+x^11+x^10+x^9+
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* x^8+x^6+x^0
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*/
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#define CRC32C_POLY_LE 0x82F63B78
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#endif
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#define FXGMAC_FAIL -1
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#define FXGMAC_SUCCESS 0
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#define FXGMAC_DEV_CMD (SIOCDEVPRIVATE + 1)
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#define FXGMAC_IOCTL_DFS_COMMAND _IOWR('M', 0x80, struct ext_ioctl_data)
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#define FXGMAC_MAX_DBG_TEST_PKT 150
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#define FXGMAC_MAX_DBG_BUF_LEN 64000
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#define FXGMAC_MAX_DBG_RX_DATA 1600
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#define FXGMAC_NETDEV_OPS_BUF_LEN 256
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#define FXGMAC_TEST_MAC_HEAD_LEN 14
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#define FUXI_PM_WPI_READ_FEATURE_EN 1
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#define RSS_Q_COUNT 4
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//#define FXGMAC_TX_INTERRUPT_EN 1
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#define FXGMAC_TX_HANG_TIMER_EN 0
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/* only for debug. for normal run, pls keep them both 0 */
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//0: use default tx q; other: specify txq-1: 1 txq;
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#define FXGMAC_NUM_OF_TX_Q_USED 0
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//1 to enable a dummy tx,ie, no tail for gmac;
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#define FXGMAC_DUMMY_TX_DEBUG 0
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//1 to trigger(write reg 0x1000) for sniffer stop
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#define FXGMAC_TRIGGER_TX_HANG 0
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/* driver feature configuration */
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#if FXGMAC_TX_HANG_TIMER_EN
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//0: check hw current desc; 1: check software dirty
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#define FXGMAC_TX_HANG_CHECH_DIRTY 0
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#endif
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// 1:poll tx of 4 channels; 0: since only 1 tx channel supported in this
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// version, poll ch 0 always.
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#define FXGMAC_FULL_TX_CHANNEL 0
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#ifdef CONFIG_ARM64
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// when you want to run this driver on 64bit arm,you should open this,otherwise
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// dma's mask cannot be set successfully.
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#define FUXI_DMA_BIT_MASK 64
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#endif
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#ifdef CONFIG_PCI_MSI
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//should be same as FXGMAC_MAX_DMA_CHANNELS + 1 tx_irq
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#define FXGMAC_MAX_MSIX_Q_VECTORS (FXGMAC_MSIX_Q_VECTORS + 1)
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#define FXGMAC_MSIX_CH0RXDIS_EN 0 //set to 1 for ch0 unbalance fix;
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#define FXGMAC_MSIX_INTCTRL_EN 1
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#define FXGMAC_PHY_INT_NUM 1
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#define FXGMAC_MSIX_INT_NUMS (FXGMAC_MAX_MSIX_Q_VECTORS + FXGMAC_PHY_INT_NUM)
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#else //for case of no CONFIG_PCI_MSI
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#define FXGMAC_MSIX_CH0RXDIS_EN 0 //NO modification needed! for non-MSI, set to 0 always
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#define FXGMAC_MSIX_INTCTRL_EN 0
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#endif
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/*RSS features*/
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#ifdef FXGMAC_ONE_CHANNEL
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#define FXGMAC_RSS_FEATURE_ENABLED 0 // 1:enable rss ; 0: rss not included.
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#else
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#define FXGMAC_RSS_FEATURE_ENABLED 1 // 1:enable rss ; 0: rss not included.
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#endif
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#define FXGMAC_RSS_HASH_KEY_LINUX 1 // 0:hard to default rss key ;1: normal hash key process from Linux.
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/*WOL features*/
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#define FXGMAC_WOL_FEATURE_ENABLED 1 // 1:enable wol ; 0: wol not included.
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/*since wol upon link will cause issue, disabled it always. */
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#define FXGMAC_WOL_UPON_EPHY_LINK 1 // 1:enable ephy link change wol ; 0: ephy link change wol is not supported.
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/*Pause features*/
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#define FXGMAC_PAUSE_FEATURE_ENABLED 1 // 1:enable flow control/pause framce ; 0: flow control/pause frame not included.
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/*ARP offload engine (AOE)*/
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#define FXGMAC_AOE_FEATURE_ENABLED 1 // 1:enable arp offload engine ; 0: aoe is not included.
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/*NS offload engine*/
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#define FXGMAC_NS_OFFLOAD_ENABLED 1 // 1:enable NS offload for IPv6 ; 0: NS is not included.
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/*for fpga ver after, which needs release phy before set of MAC tx/rx */
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#define FXGMAC_TXRX_EN_AFTER_PHY_RELEASE 1 // 1:release ephy before mac tx/rx bits are set.
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/*power management features*/
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#define FXGMAC_PM_FEATURE_ENABLED 1 // 1:enable PM ; 0: PM not included.
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/*sanity check*/
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#define FXGMAC_SANITY_CHECK_ENABLED 0 // 1:enable health checking ;
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/*vlan id filter*/
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#define FXGMAC_FILTER_SINGLE_VLAN_ENABLED 1 // 1:enable health checking ;
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//Linux driver implement VLAN HASH Table feature to support mutliple VLAN feautre
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#define FXGMAC_FILTER_MULTIPLE_VLAN_ENABLED 1
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//Linux driver implement MAC HASH Table feature
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#define FUXI_MAC_HASH_TABLE 1
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//Linux driver implement write multiple mac addr
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#define FXGMAC_FILTER_MULTIPLE_MAC_ADDR_ENABLED 1
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//Linux driver disable MISC Interrupt
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#define FUXI_MISC_INT_HANDLE_FEATURE_EN 1
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#define HAVE_FXGMAC_DEBUG_FS
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#ifndef offsetof
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#define offsetof(TYPE, MEMBER) ((size_t) &(((TYPE*)0)->MEMBER))
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#endif
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#define ETH_IS_ZEROADDRESS(Address) \
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((((u8*)(Address))[0] == ((u8)0x00)) \
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&& (((u8*)(Address))[1] == ((u8)0x00)) \
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&& (((u8*)(Address))[2] == ((u8)0x00)) \
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&& (((u8*)(Address))[3] == ((u8)0x00)) \
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&& (((u8*)(Address))[4] == ((u8)0x00)) \
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&& (((u8*)(Address))[5] == ((u8)0x00)))
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/* read from 8bit register via pci config space */
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#define cfg_r8(_pdata, reg, pdat) pci_read_config_byte((_pdata)->pdev, (reg), (u8 *)(pdat))
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/* read from 16bit register via pci config space */
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#define cfg_r16(_pdata, reg, pdat) pci_read_config_word((_pdata)->pdev, (reg), (u16 *)(pdat))
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/* read from 32bit register via pci config space */
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#define cfg_r32(_pdata, reg, pdat) pci_read_config_dword((_pdata)->pdev, (reg), (u32 *)(pdat))
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/* write to 8bit register via pci config space */
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#define cfg_w8(_pdata, reg, val) pci_write_config_byte((_pdata)->pdev, (reg), (u8)(val))
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/* write to 16bit register via pci config space */
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#define cfg_w16(_pdata, reg, val) pci_write_config_word((_pdata)->pdev, (reg), (u16)(val))
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/* write to 32bit register via pci config space */
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#define cfg_w32(_pdata, reg, val) pci_write_config_dword((_pdata)->pdev, (reg), (u32)(val))
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#define readreg(pAdapter, addr) (readl(addr))
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#define writereg(pAdapter, val, addr) (writel(val, addr))
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#define usleep_range_ex(pAdapter, a, b) (usleep_range(a, b))
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#define _CR(Record, TYPE, Field) ((TYPE *) ((char *) (Record) - (char *) &(((TYPE *) 0)->Field)))
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#define FXGMAC_GET_REG_BITS(var, pos, len) ({ \
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typeof(pos) _pos = (pos); \
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typeof(len) _len = (len); \
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((var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos); \
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})
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#define FXGMAC_GET_REG_BITS_LE(var, pos, len) ({ \
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typeof(pos) _pos = (pos); \
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typeof(len) _len = (len); \
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typeof(var) _var = le32_to_cpu((var)); \
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((_var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos); \
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})
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#define FXGMAC_SET_REG_BITS(var, pos, len, val) ({ \
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typeof(var) _var = (var); \
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typeof(pos) _pos = (pos); \
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typeof(len) _len = (len); \
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typeof(val) _val = (val); \
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_val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos); \
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_var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val; \
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})
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#define FXGMAC_SET_REG_BITS_LE(var, pos, len, val) ({ \
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typeof(var) _var = (var); \
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typeof(pos) _pos = (pos); \
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typeof(len) _len = (len); \
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typeof(val) _val = (val); \
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_val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos); \
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_var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val; \
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cpu_to_le32(_var); \
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})
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#define STR_FORMAT "%s"
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#define DbgPrintF(level, fmt, ...)
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#define DBGPRINT(Level, Fmt)
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#define DBGPRINT_RAW(Level, Fmt)
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#define DBGPRINT_S(Status, Fmt)
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#define DBGPRINT_UNICODE(Level, UString)
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#define Dump(p,cb,fAddress,ulGroup)
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#undef ASSERT
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#define ASSERT(x)
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#define DbgPrintOidName(_Oid)
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#define DbgPrintAddress(_pAddress)
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#define fxgmac_dump_buffer(_skb, _len, _tx_rx)
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#define DumpLine(_p, _cbLine, _fAddress, _ulGroup )
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#ifndef FXGMAC_DEBUG
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#define FXGMAC_DEBUG
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#endif
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/* For debug prints */
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#ifdef FXGMAC_DEBUG
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#define FXGMAC_PR(fmt, args...) \
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pr_alert("[%s,%d]:" fmt, __func__, __LINE__, ## args)
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#define DPRINTK printk
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#else
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#define FXGMAC_PR(x...) do { } while (0)
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#define DPRINTK(x...)
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#endif
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#define IOC_MAGIC 'M'
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#define IOC_MAXNR (0x80 + 5)
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#define FUXI_DFS_IOCTL_DEVICE_INACTIVE 0x10001
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#define FUXI_DFS_IOCTL_DEVICE_RESET 0x10002
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#define FUXI_DFS_IOCTL_DIAG_BEGIN 0x10003
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#define FUXI_DFS_IOCTL_DIAG_END 0x10004
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#define FUXI_DFS_IOCTL_DIAG_TX_PKT 0x10005
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#define FUXI_DFS_IOCTL_DIAG_RX_PKT 0x10006
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#define FXGMAC_EFUSE_UPDATE_LED_CFG 0x10007
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#define FXGMAC_EFUSE_WRITE_LED 0x10008
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#define FXGMAC_EFUSE_WRITE_PATCH_REG 0x10009
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#define FXGMAC_EFUSE_WRITE_PATCH_PER_INDEX 0x1000A
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#define FXGMAC_EFUSE_WRITE_OOB 0x1000B
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#define FXGMAC_EFUSE_LOAD 0x1000C
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#define FXGMAC_EFUSE_READ_REGIONABC 0x1000D
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#define FXGMAC_EFUSE_READ_PATCH_REG 0x1000E
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#define FXGMAC_EFUSE_READ_PATCH_PER_INDEX 0x1000F
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#define FXGMAC_EFUSE_LED_TEST 0x10010
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#define FXGMAC_GET_MAC_DATA 0x10011
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#define FXGMAC_SET_MAC_DATA 0x10012
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#define FXGMAC_GET_SUBSYS_ID 0x10013
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#define FXGMAC_SET_SUBSYS_ID 0x10014
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#define FXGMAC_GET_GMAC_REG 0x10015
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#define FXGMAC_SET_GMAC_REG 0x10016
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#define FXGMAC_GET_PHY_REG 0x10017
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#define FXGMAC_SET_PHY_REG 0x10018
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#define FXGMAC_EPHYSTATISTICS 0x10019
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#define FXGMAC_GET_STATISTICS 0x1001A
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#define FXGMAC_GET_PCIE_LOCATION 0x1001B
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#define FXGMAC_GET_GSO_SIZE 0x1001C
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#define FXGMAC_SET_GSO_SIZE 0x1001D
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#define FXGMAC_SET_RX_MODERATION 0x1001E
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#define FXGMAC_SET_TX_MODERATION 0x1001F
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#define FXGMAC_GET_TXRX_MODERATION 0x10020
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#define MAX_PKT_BUF 1
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#define FXGAMC_MAX_DATA_SIZE (1024 * 4 + 16)
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#ifndef PCI_CAP_ID_MSI
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#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
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#endif
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#ifndef PCI_CAP_ID_MSIX
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#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
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#endif
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#define PCI_CAP_ID_MSI_ENABLE_POS 0x10
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#define PCI_CAP_ID_MSI_ENABLE_LEN 0x1
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#define PCI_CAP_ID_MSIX_ENABLE_POS 0x1F
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#define PCI_CAP_ID_MSIX_ENABLE_LEN 0x1
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#ifndef fallthrough
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#if __has_attribute(__fallthrough__)
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# define fallthrough __attribute__((__fallthrough__))
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#else
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# define fallthrough do {} while (0) /* fallthrough */
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#endif
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#endif
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#pragma pack(1)
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// it's better to make this struct's size to 128byte.
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struct pattern_packet{
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u8 ether_daddr[ETH_ALEN];
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u8 ether_saddr[ETH_ALEN];
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u16 ether_type;
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__be16 ar_hrd; /* format of hardware address */
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__be16 ar_pro; /* format of protocol */
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unsigned char ar_hln; /* length of hardware address */
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unsigned char ar_pln; /* length of protocol address */
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__be16 ar_op; /* ARP opcode (command) */
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unsigned char ar_sha[ETH_ALEN]; /* sender hardware address */
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unsigned char ar_sip[4]; /* sender IP address */
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unsigned char ar_tha[ETH_ALEN]; /* target hardware address */
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unsigned char ar_tip[4]; /* target IP address */
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u8 reverse[86];
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};
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#pragma pack()
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typedef enum
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{
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CURRENT_STATE_SHUTDOWN = 0,
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CURRENT_STATE_RESUME = 1,
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CURRENT_STATE_INIT = 2,
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CURRENT_STATE_SUSPEND = 3,
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CURRENT_STATE_CLOSE = 4,
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CURRENT_STATE_OPEN = 5,
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CURRENT_STATE_RESTART = 6,
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CURRENT_STATE_REMOVE = 7,
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}CURRENT_STATE;
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typedef dma_addr_t DMA_ADDR_T;
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typedef enum pkt_hash_types RSS_HASH_TYPE;
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typedef void __iomem* IOMEM;
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typedef struct pci_dev PCI_DEV;
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struct ext_command_buf {
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void* buf;
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u32 size_in;
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u32 size_out;
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};
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struct ext_command_mac {
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u32 num;
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union {
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u32 val32;
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u16 val16;
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u8 val8;
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};
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};
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struct ext_command_mii {
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u16 dev;
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u16 num;
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u16 val;
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};
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struct ext_ioctl_data {
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u32 cmd_type;
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struct ext_command_buf cmd_buf;
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};
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typedef struct _fxgmac_test_buf {
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u8* addr;
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u32 offset;
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u32 length;
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} fxgmac_test_buf, *pfxgmac_test_buf;
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typedef struct _fxgmac_test_packet {
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struct _fxgmac_test_packet * next;
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u32 length; /* total length of the packet(buffers) */
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u32 type; /* packet type, vlan, ip checksum, TSO, etc. */
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fxgmac_test_buf buf[MAX_PKT_BUF];
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fxgmac_test_buf sGList[MAX_PKT_BUF];
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u16 vlanID;
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u16 mss;
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u32 hash;
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u16 cpuNum;
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u16 xsum; /* rx, ip-payload checksum */
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u16 csumStart; /* custom checksum offset to the mac-header */
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u16 csumPos; /* custom checksom position (to the mac_header) */
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void* upLevelReserved[4];
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void* lowLevelReserved[4];
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} fxgmac_test_packet, *pfxgmac_test_packet;
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typedef struct fxgmac_channel_of_platform
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{
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char dma_irq_name[IFNAMSIZ + 32];
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u32 dma_irq_tx; //for MSIx to match the type of struct msix_entry.vector
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char dma_irq_name_tx[IFNAMSIZ + 32];
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/* Netdev related settings */
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struct napi_struct napi_tx;
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/* Netdev related settings */
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struct napi_struct napi_rx;
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struct timer_list tx_timer;
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#if FXGMAC_TX_HANG_TIMER_EN
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unsigned int tx_hang_timer_active;
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struct timer_list tx_hang_timer;
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unsigned int tx_hang_hw_cur;
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#endif
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}FXGMAC_CHANNEL_OF_PLATFORM;
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typedef struct per_regisiter_info
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{
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unsigned int size;
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unsigned int address;
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unsigned int value;
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unsigned char data[FXGAMC_MAX_DATA_SIZE];
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}PER_REG_INFO;
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// for FXGMAC_EFUSE_WRITE_PATCH_PER_INDEX,val0 is index, val1 is offset,
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// val2 is value
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typedef struct ext_command_data {
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u32 val0;
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u32 val1;
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u32 val2;
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}CMD_DATA;
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|
|
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typedef struct fxgmac_pdata_of_platform
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{
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u32 cfg_pci_cmd;
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u32 cfg_cache_line_size;
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u32 cfg_mem_base;
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|
u32 cfg_mem_base_hi;
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|
u32 cfg_io_base;
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|
u32 cfg_int_line;
|
|
u32 cfg_device_ctrl1;
|
|
u32 cfg_pci_link_ctrl;
|
|
u32 cfg_device_ctrl2;
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|
u32 cfg_msix_capability;
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|
|
|
struct work_struct restart_work;
|
|
u32 int_flags; //legacy, msi or msix
|
|
int phy_irq;
|
|
#ifdef CONFIG_PCI_MSI
|
|
struct msix_entry *msix_entries;
|
|
#endif
|
|
|
|
/* power management and wol*/
|
|
u32 wol; //wol options
|
|
unsigned long powerstate; //power state
|
|
unsigned int ns_offload_tab_idx; //for ns-offload table. 2 entries supported.
|
|
CURRENT_STATE current_state;
|
|
netdev_features_t netdev_features;
|
|
struct napi_struct napi;
|
|
struct napi_struct napi_phy;
|
|
u32 mgm_intctrl_val;
|
|
bool phy_link;
|
|
bool fxgmac_test_tso_flag;
|
|
u32 fxgmac_test_tso_seg_num;
|
|
u32 fxgmac_test_last_tso_len;
|
|
u32 fxgmac_test_packet_len;
|
|
volatile u32 fxgmac_test_skb_arr_in_index;
|
|
volatile u32 fxgmac_test_skb_arr_out_index;
|
|
//CMD_DATA ex_cmd_data;
|
|
//PER_REG_INFO per_reg_data;
|
|
struct sk_buff *fxgmac_test_skb_array[FXGMAC_MAX_DBG_TEST_PKT];
|
|
#ifdef HAVE_FXGMAC_DEBUG_FS
|
|
struct dentry *dbg_adapter;
|
|
struct dentry *fxgmac_dbg_root;
|
|
char fxgmac_dbg_netdev_ops_buf[FXGMAC_NETDEV_OPS_BUF_LEN];
|
|
#endif
|
|
}FXGMAC_PDATA_OF_PLATFORM;
|
|
|
|
|
|
#ifdef HAVE_FXGMAC_DEBUG_FS
|
|
void fxgmac_dbg_adapter_init(struct fxgmac_pdata *pdata);
|
|
void fxgmac_dbg_adapter_exit(struct fxgmac_pdata *pdata);
|
|
void fxgmac_dbg_init(struct fxgmac_pdata *pdata);
|
|
void fxgmac_dbg_exit(struct fxgmac_pdata *pdata);
|
|
#endif /* HAVE_FXGMAC_DEBUG_FS */
|
|
|
|
void fxgmac_restart_dev(struct fxgmac_pdata *pdata);
|
|
long fxgmac_dbg_netdev_ops_ioctl(struct file *file, unsigned int cmd,
|
|
unsigned long arg);
|
|
|
|
int fxgmac_init(struct fxgmac_pdata *pdata, bool save_private_reg);
|
|
/* for phy interface */
|
|
int fxgmac_ephy_autoneg_ability_get(struct fxgmac_pdata *pdata,
|
|
unsigned int *cap_mask);
|
|
int fxgmac_ephy_status_get(struct fxgmac_pdata *pdata, int* speed,
|
|
int* duplex, int* ret_link, int *media);
|
|
int fxgmac_ephy_soft_reset(struct fxgmac_pdata *pdata);
|
|
void fxgmac_phy_force_speed(struct fxgmac_pdata *pdata, int speed);
|
|
void fxgmac_phy_force_duplex(struct fxgmac_pdata *pdata, int duplex);
|
|
void fxgmac_phy_force_autoneg(struct fxgmac_pdata *pdata, int autoneg);
|
|
|
|
unsigned int fxgmac_get_netdev_ip4addr(struct fxgmac_pdata *pdata);
|
|
unsigned char * fxgmac_get_netdev_ip6addr(struct fxgmac_pdata *pdata,
|
|
unsigned char *ipval,
|
|
unsigned char *ip6addr_solicited,
|
|
unsigned int ifa_flag);
|
|
|
|
#if FXGMAC_PM_FEATURE_ENABLED
|
|
void fxgmac_net_powerdown(struct fxgmac_pdata *pdata, unsigned int wol);
|
|
void fxgmac_net_powerup(struct fxgmac_pdata *pdata);
|
|
#endif
|
|
|
|
inline unsigned int fxgmac_tx_avail_desc(struct fxgmac_ring *ring);
|
|
inline unsigned int fxgmac_rx_dirty_desc(struct fxgmac_ring *ring);
|
|
int fxgmac_start(struct fxgmac_pdata *pdata);
|
|
void fxgmac_stop(struct fxgmac_pdata *pdata);
|
|
void fxgmac_free_rx_data(struct fxgmac_pdata *pdata);
|
|
void fxgmac_free_tx_data(struct fxgmac_pdata *pdata);
|
|
|
|
#endif //__FUXI_OS_H__
|
|
|