925 lines
34 KiB
C
Executable File
925 lines
34 KiB
C
Executable File
/*++
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Copyright (c) 2021 Motorcomm, Inc.
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Motorcomm Confidential and Proprietary.
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This is Motorcomm NIC driver relevant files. Please don't copy, modify,
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distribute without commercial permission.
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--*/
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#ifndef __FUXI_GMAC_H__
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#define __FUXI_GMAC_H__
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#include "fuxi-os.h"
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// For fpga before 20210507
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#define FXGMAC_FPGA_VER_B4_0507 0
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#define FXGMAC_FPGA_VER_20210507 1
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#define FXGMAC_DRV_NAME "yt6801"
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#define FXGMAC_DRV_DESC "Motorcomm FUXI GMAC Driver"
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#define FUXI_MAC_REGS_OFFSET 0x2000
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#define FUXI_EPHY_INTERRUPT_D0_OFF 0 //1: in normal D0 state, turn off ephy link change interrupt.
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#define FUXI_ALLOC_NEW_RECBUFFER 0 //1:when rec buffer is not enough,to create rbd and rec buffer ,but the rdb need to be continus with the intialized rdb,so close the feature
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#define RESUME_MAX_TIME 3000000
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#define PHY_LINK_TIMEOUT 3000
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#define ESD_RESET_MAXIMUM 0
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#define REGWR_RETRY_MAXIMUM 2600
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#define PCIE_LINKDOWN_VALUE 0xFFFFFFFF
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#define FXGMAC_MSIX_Q_VECTORS 4
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#define FXGMAC_IS_CHANNEL_WITH_TX_IRQ(chId) (0 == (chId) ? 1 : 0)
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/* flags for ipv6 NS offload address, local link or Global unicast */
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#define FXGMAC_NS_IFA_LOCAL_LINK 1
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#define FXGMAC_NS_IFA_GLOBAL_UNICAST 2
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#define FXGMAX_ASPM_WAR_EN
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/* Descriptor related parameters */
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#if FXGMAC_TX_HANG_TIMER_EN
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#define FXGMAC_TX_DESC_CNT 1024
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#else
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#define FXGMAC_TX_DESC_CNT 256 //256 to make sure the tx ring is in the 4k range when FXGMAC_TX_HANG_TIMER_EN is 0
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#endif
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#define FXGMAC_TX_DESC_MIN_FREE (FXGMAC_TX_DESC_CNT >> 3)
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#define FXGMAC_TX_DESC_MAX_PROC (FXGMAC_TX_DESC_CNT >> 1)
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#define FXGMAC_RX_DESC_CNT 1024
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#define FXGMAC_RX_DESC_MAX_DIRTY (FXGMAC_RX_DESC_CNT >> 3)
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/* Descriptors required for maximum contiguous TSO/GSO packet */
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#define FXGMAC_TX_MAX_SPLIT ((GSO_MAX_SIZE / FXGMAC_TX_MAX_BUF_SIZE) + 1)
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/* Maximum possible descriptors needed for a SKB */
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#define FXGMAC_TX_MAX_DESC_NR (MAX_SKB_FRAGS + FXGMAC_TX_MAX_SPLIT + 2)
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#define FXGMAC_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
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#define FXGMAC_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
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#define FXGMAC_RX_BUF_ALIGN 64
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/* Maximum Size for Splitting the Header Data
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* Keep in sync with SKB_ALLOC_SIZE
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* 3'b000: 64 bytes, 3'b001: 128 bytes
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* 3'b010: 256 bytes, 3'b011: 512 bytes
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* 3'b100: 1023 bytes , 3'b101'3'b111: Reserved
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*/
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#define FXGMAC_SPH_HDSMS_SIZE 3
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#define FXGMAC_SKB_ALLOC_SIZE 512
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//2022-04-22 xiaojiang comment
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//In Linux Driver, it set MAX_FIFO size 131072, here it uses the same value as windows driver
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#define FXGMAC_MAX_FIFO 81920
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#define FXGMAC_MAX_DMA_CHANNELS FXGMAC_MSIX_Q_VECTORS
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#define FXGMAC_DMA_STOP_TIMEOUT 5
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#define FXGMAC_DMA_INTERRUPT_MASK 0x31c7
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#define FXGMAC_MAX_DMA_CHANNELS_PLUS_1TX (FXGMAC_MAX_DMA_CHANNELS + 1)
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/* Default coalescing parameters */
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//2022-04-22 xiaojiang comment
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//In Windows Driver, the DMA_TX_USECS is not used, here it uses the linux driver value
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#define FXGMAC_INIT_DMA_TX_USECS INT_MOD_IN_US
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#define FXGMAC_INIT_DMA_TX_FRAMES 25
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#define FXGMAC_INIT_DMA_RX_USECS INT_MOD_IN_US
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#define FXGMAC_INIT_DMA_RX_FRAMES 25
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#define FXGMAC_MAX_DMA_RIWT 0xff
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#define FXGMAC_MIN_DMA_RIWT 0x01
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/* Flow control queue count */
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#define FXGMAC_MAX_FLOW_CONTROL_QUEUES 8
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/* System clock is 125 MHz */
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#define FXGMAC_SYSCLOCK 125000000
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/* Maximum MAC address hash table size (256 bits = 8 bytes) */
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#define FXGMAC_MAC_HASH_TABLE_SIZE 8
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/* wol pattern settings */
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#define MAX_PATTERN_SIZE 128 // PATTERN length
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#define MAX_PATTERN_COUNT 16 // pattern count
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#define MAX_LPP_ARP_OFFLOAD_COUNT 1
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#define MAX_LPP_NS_OFFLOAD_COUNT 2
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#define MAX_WPI_LENGTH_SIZE 1536 // WPI packet.
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#define PM_WAKE_PKT_ALIGN 8 // try use 64 bit boundary...
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/* Receive Side Scaling */
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#define FXGMAC_RSS_HASH_KEY_SIZE 40
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#define FXGMAC_RSS_MAX_TABLE_SIZE 128
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#define FXGMAC_RSS_LOOKUP_TABLE_TYPE 0
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#define FXGMAC_RSS_HASH_KEY_TYPE 1
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#define MAX_MSI_COUNT 16 // Max Msi/Msix supported.
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#define FXGMAC_STD_PACKET_MTU 1500
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#define FXGMAC_JUMBO_PACKET_MTU 9014
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#define NIC_MAX_TCP_OFFLOAD_SIZE 7300
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#define NIC_MIN_LSO_SEGMENT_COUNT 2
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/* power management */
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#define FXGMAC_POWER_STATE_DOWN 0
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#define FXGMAC_POWER_STATE_UP 1
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// Don't change the member variables or types, this inherits from Windows OS.
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struct wol_bitmap_pattern
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{
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u32 flags;
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u32 pattern_size;
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u32 mask_size;
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u8 mask_info[MAX_PATTERN_SIZE / 8];
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u8 pattern_info[MAX_PATTERN_SIZE];
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u8 pattern_offset;
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u16 pattern_crc;
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};
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struct led_setting
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{
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u32 s0_led_setting[5];
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u32 s3_led_setting[5];
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u32 s5_led_setting[5];
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u32 disable_led_setting[5];
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};
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typedef struct led_setting LED_SETTING;
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typedef struct wol_bitmap_pattern WOL_BITMAP_PATTERN;
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typedef enum
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{
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WAKE_REASON_NONE = 0,
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WAKE_REASON_MAGIC,
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WAKE_REASON_PATTERNMATCH,
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WAKE_REASON_LINK,
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WAKE_REASON_TCPSYNV4,
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WAKE_REASON_TCPSYNV6,
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WAKE_REASON_TBD, //for wake up method like Link-change, for that, GMAC cannot identify and need more checking.
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WAKE_REASON_HW_ERR,
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} WAKE_REASON; //note, maybe we should refer to NDIS_PM_WAKE_REASON_TYPE to avoid duplication definition....
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/* Helper macro for descriptor handling
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* Always use FXGMAC_GET_DESC_DATA to access the descriptor data
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*/
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#if 0 //No need to round
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#define FXGMAC_GET_DESC_DATA(ring, idx) ({ \
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typeof(ring) _ring = (ring); \
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((_ring)->desc_data_head + \
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((idx) & ((_ring)->dma_desc_count - 1))); \
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})
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#endif
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#define FXGMAC_GET_DESC_DATA(ring, idx) ((ring)->desc_data_head + (idx))
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#define FXGMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
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struct fxgmac_pdata;
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enum fxgmac_int {
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FXGMAC_INT_DMA_CH_SR_TI,
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FXGMAC_INT_DMA_CH_SR_TPS,
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FXGMAC_INT_DMA_CH_SR_TBU,
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FXGMAC_INT_DMA_CH_SR_RI,
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FXGMAC_INT_DMA_CH_SR_RBU,
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FXGMAC_INT_DMA_CH_SR_RPS,
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FXGMAC_INT_DMA_CH_SR_TI_RI,
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FXGMAC_INT_DMA_CH_SR_FBE,
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FXGMAC_INT_DMA_ALL,
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};
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struct fxgmac_stats {
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/* MMC TX counters */
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u64 txoctetcount_gb;
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u64 txframecount_gb;
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u64 txbroadcastframes_g;
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u64 txmulticastframes_g;
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u64 tx64octets_gb;
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u64 tx65to127octets_gb;
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u64 tx128to255octets_gb;
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u64 tx256to511octets_gb;
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u64 tx512to1023octets_gb;
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u64 tx1024tomaxoctets_gb;
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u64 txunicastframes_gb;
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u64 txmulticastframes_gb;
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u64 txbroadcastframes_gb;
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u64 txunderflowerror;
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u64 txsinglecollision_g;
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u64 txmultiplecollision_g;
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u64 txdeferredframes;
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u64 txlatecollisionframes;
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u64 txexcessivecollisionframes;
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u64 txcarriererrorframes;
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u64 txoctetcount_g;
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u64 txframecount_g;
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u64 txexcessivedeferralerror;
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u64 txpauseframes;
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u64 txvlanframes_g;
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u64 txoversize_g;
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/* MMC RX counters */
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u64 rxframecount_gb;
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u64 rxoctetcount_gb;
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u64 rxoctetcount_g;
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u64 rxbroadcastframes_g;
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u64 rxmulticastframes_g;
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u64 rxcrcerror;
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u64 rxalignerror;
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u64 rxrunterror;
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u64 rxjabbererror;
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u64 rxundersize_g;
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u64 rxoversize_g;
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u64 rx64octets_gb;
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u64 rx65to127octets_gb;
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u64 rx128to255octets_gb;
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u64 rx256to511octets_gb;
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u64 rx512to1023octets_gb;
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u64 rx1024tomaxoctets_gb;
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u64 rxunicastframes_g;
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u64 rxlengtherror;
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u64 rxoutofrangetype;
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u64 rxpauseframes;
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u64 rxfifooverflow;
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u64 rxvlanframes_gb;
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u64 rxwatchdogerror;
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u64 rxreceiveerrorframe;
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u64 rxcontrolframe_g;
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/* Extra counters */
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u64 tx_tso_packets;
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u64 rx_split_header_packets;
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u64 tx_process_stopped;
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u64 rx_process_stopped;
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u64 tx_buffer_unavailable;
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u64 rx_buffer_unavailable;
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u64 fatal_bus_error;
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u64 tx_vlan_packets;
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u64 rx_vlan_packets;
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u64 napi_poll_isr;
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u64 napi_poll_txtimer;
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u64 cnt_alive_txtimer;
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u64 ephy_poll_timer_cnt;
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u64 mgmt_int_isr;
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};
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struct fxgmac_ring_buf {
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struct sk_buff* skb;
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DMA_ADDR_T skb_dma;
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unsigned int skb_len;
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};
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/* Common Tx and Rx DMA hardware descriptor */
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struct fxgmac_dma_desc {
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__le32 desc0;
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__le32 desc1;
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__le32 desc2;
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__le32 desc3;
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};
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/* Page allocation related values */
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struct fxgmac_page_alloc {
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struct page* pages;
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unsigned int pages_len;
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unsigned int pages_offset;
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DMA_ADDR_T pages_dma;
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};
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/* Ring entry buffer data */
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struct fxgmac_buffer_data {
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struct fxgmac_page_alloc pa;
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struct fxgmac_page_alloc pa_unmap;
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DMA_ADDR_T dma_base;
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unsigned long dma_off;
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unsigned int dma_len;
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};
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/* Tx-related desc data */
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struct fxgmac_tx_desc_data {
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unsigned int packets; /* BQL packet count */
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unsigned int bytes; /* BQL byte count */
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};
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/* Rx-related desc data */
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struct fxgmac_rx_desc_data {
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struct fxgmac_buffer_data hdr; /* Header locations */
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struct fxgmac_buffer_data buf; /* Payload locations */
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unsigned short hdr_len; /* Length of received header */
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unsigned short len; /* Length of received packet */
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};
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struct fxgmac_pkt_info {
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struct sk_buff* skb;
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unsigned int attributes;
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unsigned int errors;
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/* descriptors needed for this packet */
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unsigned int desc_count;
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unsigned int length;
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unsigned int tx_packets;
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unsigned int tx_bytes;
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unsigned int header_len;
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unsigned int tcp_header_len;
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unsigned int tcp_payload_len;
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unsigned short mss;
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unsigned short vlan_ctag;
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u64 rx_tstamp;
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u32 rss_hash;
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RSS_HASH_TYPE rss_hash_type;
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};
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struct fxgmac_desc_data {
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/* dma_desc: Virtual address of descriptor
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* dma_desc_addr: DMA address of descriptor
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*/
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struct fxgmac_dma_desc* dma_desc;
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DMA_ADDR_T dma_desc_addr;
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/* skb: Virtual address of SKB
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* skb_dma: DMA address of SKB data
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* skb_dma_len: Length of SKB DMA area
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*/
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struct sk_buff* skb;
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DMA_ADDR_T skb_dma;
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unsigned int skb_dma_len;
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/* Tx/Rx -related data */
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struct fxgmac_tx_desc_data tx;
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struct fxgmac_rx_desc_data rx;
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unsigned int mapped_as_page;
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/* Incomplete receive save location. If the budget is exhausted
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* or the last descriptor (last normal descriptor or a following
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* context descriptor) has not been DMA'd yet the current state
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* of the receive processing needs to be saved.
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*/
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unsigned int state_saved;
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struct {
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struct sk_buff* skb;
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unsigned int len;
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unsigned int error;
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} state;
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};
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struct fxgmac_ring {
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/* Per packet related information */
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struct fxgmac_pkt_info pkt_info;
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/* Virtual/DMA addresses of DMA descriptor list and the total count */
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struct fxgmac_dma_desc *dma_desc_head;
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DMA_ADDR_T dma_desc_head_addr;
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unsigned int dma_desc_count;
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/* Array of descriptor data corresponding the DMA descriptor
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* (always use the FXGMAC_GET_DESC_DATA macro to access this data)
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*/
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struct fxgmac_desc_data *desc_data_head;
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/* Page allocation for RX buffers */
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struct fxgmac_page_alloc rx_hdr_pa;
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struct fxgmac_page_alloc rx_buf_pa;
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/* Ring index values
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* cur - Tx: index of descriptor to be used for current transfer
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* Rx: index of descriptor to check for packet availability
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* dirty - Tx: index of descriptor to check for transfer complete
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* Rx: index of descriptor to check for buffer reallocation
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*/
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unsigned int cur;
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unsigned int dirty;
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/* Coalesce frame count used for interrupt bit setting */
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unsigned int coalesce_count;
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struct {
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unsigned int xmit_more;
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unsigned int queue_stopped;
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unsigned short cur_mss;
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unsigned short cur_vlan_ctag;
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} tx;
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} ____cacheline_aligned;
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struct fxgmac_channel {
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char name[16];
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/* Address of private data area for device */
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struct fxgmac_pdata* pdata;
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/* Queue index and base address of queue's DMA registers */
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unsigned int queue_index;
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IOMEM dma_regs;
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/* Per channel interrupt irq number */
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u32 dma_irq;
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FXGMAC_CHANNEL_OF_PLATFORM expansion;
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unsigned int saved_ier;
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unsigned int tx_timer_active;
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struct fxgmac_ring *tx_ring;
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struct fxgmac_ring *rx_ring;
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} ____cacheline_aligned;
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struct fxphy_ag_adv {
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u8 auto_neg_en : 1;
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u8 full_1000m : 1;
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u8 half_1000m : 1;
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u8 full_100m : 1;
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u8 half_100m : 1;
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u8 full_10m : 1;
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u8 half_10m : 1;
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};
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struct fxgmac_desc_ops {
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int (*alloc_channles_and_rings)(struct fxgmac_pdata* pdata);
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void (*free_channels_and_rings)(struct fxgmac_pdata* pdata);
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int (*map_tx_skb)(struct fxgmac_channel* channel,
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struct sk_buff* skb);
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int (*map_rx_buffer)(struct fxgmac_pdata* pdata,
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struct fxgmac_ring* ring,
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struct fxgmac_desc_data* desc_data);
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void (*unmap_desc_data)(struct fxgmac_pdata* pdata,
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struct fxgmac_desc_data* desc_data);
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void (*tx_desc_init)(struct fxgmac_pdata* pdata);
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void (*rx_desc_init)(struct fxgmac_pdata* pdata);
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};
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struct fxgmac_hw_ops {
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int (*init)(struct fxgmac_pdata* pdata);
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int (*exit)(struct fxgmac_pdata* pdata);
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void (*save_nonstick_reg)(struct fxgmac_pdata* pdata);
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void (*restore_nonstick_reg)(struct fxgmac_pdata* pdata);
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#if defined(UEFI) || defined(PXE)
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int (*set_gmac_register)(struct fxgmac_pdata* pdata, u32 address, unsigned int data);
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u32 (*get_gmac_register)(struct fxgmac_pdata* pdata, u32 address);
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#else
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int (*set_gmac_register)(struct fxgmac_pdata* pdata, u8* address, unsigned int data);
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u32 (*get_gmac_register)(struct fxgmac_pdata* pdata, u8* address);
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void (*esd_restore_pcie_cfg)(struct fxgmac_pdata* pdata);
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#endif
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int (*tx_complete)(struct fxgmac_dma_desc* dma_desc);
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void (*enable_tx)(struct fxgmac_pdata* pdata);
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void (*disable_tx)(struct fxgmac_pdata* pdata);
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void (*enable_rx)(struct fxgmac_pdata* pdata);
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void (*disable_rx)(struct fxgmac_pdata* pdata);
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void (*enable_channel_rx)(struct fxgmac_pdata* pdata, unsigned int queue);
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int (*enable_int)(struct fxgmac_channel* channel,
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enum fxgmac_int int_id);
|
|
int (*disable_int)(struct fxgmac_channel* channel,
|
|
enum fxgmac_int int_id);
|
|
void (*set_interrupt_moderation)(struct fxgmac_pdata* pdata);
|
|
void (*enable_msix_rxtxinterrupt)(struct fxgmac_pdata* pdata);
|
|
void (*disable_msix_interrupt)(struct fxgmac_pdata* pdata);
|
|
void (*enable_msix_rxtxphyinterrupt)(struct fxgmac_pdata* pdata);
|
|
void (*enable_msix_one_interrupt)(struct fxgmac_pdata* pdata, u32 intid);
|
|
void (*disable_msix_one_interrupt)(struct fxgmac_pdata* pdata, u32 intid);
|
|
bool (*enable_mgm_interrupt)(struct fxgmac_pdata* pdata);
|
|
bool (*disable_mgm_interrupt)(struct fxgmac_pdata* pdata);
|
|
|
|
void (*dev_xmit)(struct fxgmac_channel* channel);
|
|
int (*dev_read)(struct fxgmac_channel* channel);
|
|
|
|
int (*set_mac_address)(struct fxgmac_pdata* pdata, u8* addr);
|
|
int (*set_mac_hash)(struct fxgmac_pdata* pdata);
|
|
int (*config_rx_mode)(struct fxgmac_pdata* pdata);
|
|
int (*enable_rx_csum)(struct fxgmac_pdata* pdata);
|
|
int (*disable_rx_csum)(struct fxgmac_pdata* pdata);
|
|
void (*config_tso)(struct fxgmac_pdata *pdata);
|
|
|
|
/* For MII speed configuration */
|
|
int (*config_mac_speed)(struct fxgmac_pdata* pdata);
|
|
int (*set_xlgmii_2500_speed)(struct fxgmac_pdata *pdata);
|
|
int (*set_xlgmii_1000_speed)(struct fxgmac_pdata *pdata);
|
|
int (*set_xlgmii_100_speed)(struct fxgmac_pdata *pdata);
|
|
int (*get_xlgmii_phy_status)(struct fxgmac_pdata *pdata, u32 *speed, bool *link_up, bool link_up_wait_to_complete);
|
|
|
|
/* For descriptor related operation */
|
|
void (*tx_desc_init)(struct fxgmac_channel* channel);
|
|
void (*rx_desc_init)(struct fxgmac_channel* channel);
|
|
void (*tx_desc_reset)(struct fxgmac_desc_data* desc_data);
|
|
void (*rx_desc_reset)(struct fxgmac_pdata* pdata,
|
|
struct fxgmac_desc_data* desc_data,
|
|
unsigned int index);
|
|
int (*is_last_desc)(struct fxgmac_dma_desc* dma_desc);
|
|
int (*is_context_desc)(struct fxgmac_dma_desc* dma_desc);
|
|
void (*tx_start_xmit)(struct fxgmac_channel* channel,
|
|
struct fxgmac_ring* ring);
|
|
void (*set_pattern_data)(struct fxgmac_pdata* pdata);
|
|
void (*config_wol)(struct fxgmac_pdata *pdata, int en);
|
|
|
|
/* For Flow Control */
|
|
int (*config_tx_flow_control)(struct fxgmac_pdata* pdata);
|
|
int (*config_rx_flow_control)(struct fxgmac_pdata* pdata);
|
|
|
|
/* For Jumbo Frames */
|
|
int (*config_mtu)(struct fxgmac_pdata* pdata);
|
|
int (*enable_jumbo)(struct fxgmac_pdata* pdata);
|
|
|
|
/* For Vlan related config */
|
|
int (*enable_tx_vlan)(struct fxgmac_pdata* pdata);
|
|
int (*disable_tx_vlan)(struct fxgmac_pdata* pdata);
|
|
int (*enable_rx_vlan_stripping)(struct fxgmac_pdata* pdata);
|
|
int (*disable_rx_vlan_stripping)(struct fxgmac_pdata* pdata);
|
|
int (*enable_rx_vlan_filtering)(struct fxgmac_pdata* pdata);
|
|
int (*disable_rx_vlan_filtering)(struct fxgmac_pdata* pdata);
|
|
int (*update_vlan_hash_table)(struct fxgmac_pdata* pdata);
|
|
|
|
/* For RX coalescing */
|
|
int (*config_rx_coalesce)(struct fxgmac_pdata* pdata);
|
|
int (*config_tx_coalesce)(struct fxgmac_pdata* pdata);
|
|
unsigned int (*usec_to_riwt)(struct fxgmac_pdata* pdata,
|
|
unsigned int usec);
|
|
unsigned int (*riwt_to_usec)(struct fxgmac_pdata* pdata,
|
|
unsigned int riwt);
|
|
|
|
/* For RX and TX threshold config */
|
|
int (*config_rx_threshold)(struct fxgmac_pdata* pdata,
|
|
unsigned int val);
|
|
int (*config_tx_threshold)(struct fxgmac_pdata* pdata,
|
|
unsigned int val);
|
|
|
|
/* For RX and TX Store and Forward Mode config */
|
|
int (*config_rsf_mode)(struct fxgmac_pdata* pdata,
|
|
unsigned int val);
|
|
int (*config_tsf_mode)(struct fxgmac_pdata* pdata,
|
|
unsigned int val);
|
|
|
|
/* For TX DMA Operate on Second Frame config */
|
|
int (*config_osp_mode)(struct fxgmac_pdata* pdata);
|
|
|
|
/* For RX and TX PBL config */
|
|
int (*config_rx_pbl_val)(struct fxgmac_pdata* pdata);
|
|
int (*get_rx_pbl_val)(struct fxgmac_pdata* pdata);
|
|
int (*config_tx_pbl_val)(struct fxgmac_pdata* pdata);
|
|
int (*get_tx_pbl_val)(struct fxgmac_pdata* pdata);
|
|
int (*config_pblx8)(struct fxgmac_pdata* pdata);
|
|
|
|
/* For MMC statistics */
|
|
void (*rx_mmc_int)(struct fxgmac_pdata* pdata);
|
|
void (*tx_mmc_int)(struct fxgmac_pdata* pdata);
|
|
void (*read_mmc_stats)(struct fxgmac_pdata* pdata);
|
|
bool (*update_stats_counters)(struct fxgmac_pdata* pdata, bool ephy_check_en);
|
|
|
|
/* For Receive Side Scaling */
|
|
int (*enable_rss)(struct fxgmac_pdata* pdata);
|
|
int (*disable_rss)(struct fxgmac_pdata* pdata);
|
|
u32(*get_rss_options)(struct fxgmac_pdata* pdata);
|
|
int (*set_rss_options)(struct fxgmac_pdata* pdata);
|
|
int (*set_rss_hash_key)(struct fxgmac_pdata* pdata, const u8* key);
|
|
int (*set_rss_lookup_table)(struct fxgmac_pdata* pdata, const u32* table);
|
|
|
|
/*For Offload*/
|
|
#if defined(LINUX) || defined(_WIN64) || defined(_WIN32)
|
|
void (*set_arp_offload)(struct fxgmac_pdata* pdata, unsigned char* ip_addr);
|
|
int (*enable_arp_offload)(struct fxgmac_pdata* pdata);
|
|
int (*disable_arp_offload)(struct fxgmac_pdata* pdata);
|
|
|
|
/*NS offload*/
|
|
int (*set_ns_offload)(
|
|
struct fxgmac_pdata* pdata,
|
|
unsigned int index,
|
|
unsigned char* remote_addr,
|
|
unsigned char* solicited_addr,
|
|
unsigned char* target_addr1,
|
|
unsigned char* target_addr2,
|
|
unsigned char* mac_addr);
|
|
int (*enable_ns_offload)(struct fxgmac_pdata* pdata);
|
|
int (*disable_ns_offload)(struct fxgmac_pdata* pdata);
|
|
|
|
int (*enable_wake_magic_pattern)(struct fxgmac_pdata* pdata);
|
|
int (*disable_wake_magic_pattern)(struct fxgmac_pdata* pdata);
|
|
|
|
int (*enable_wake_link_change)(struct fxgmac_pdata* pdata);
|
|
int (*disable_wake_link_change)(struct fxgmac_pdata* pdata);
|
|
|
|
int (*check_wake_pattern_fifo_pointer)(struct fxgmac_pdata* pdata);
|
|
int (*set_wake_pattern)(struct fxgmac_pdata* pdata, struct wol_bitmap_pattern* wol_pattern, u32 pattern_cnt);
|
|
int (*enable_wake_pattern)(struct fxgmac_pdata* pdata);//int XlgmacEnableArpload(struct fxgmac_pdata* pdata,unsigned char *ip_addr)
|
|
int (*disable_wake_pattern)(struct fxgmac_pdata* pdata);
|
|
int (*set_wake_pattern_mask)(struct fxgmac_pdata* pdata, u32 filter_index, u8 register_index, u32 Data);
|
|
#if defined(FUXI_PM_WPI_READ_FEATURE_EN) && FUXI_PM_WPI_READ_FEATURE_EN
|
|
void (*get_wake_packet_indication)(struct fxgmac_pdata* pdata, int* wake_reason, u32* wake_pattern_number, u8* wpi_buf, u32 buf_size, u32* packet_size);
|
|
void (*enable_wake_packet_indication)(struct fxgmac_pdata* pdata, int en);
|
|
#endif
|
|
#endif
|
|
|
|
void (*reset_phy)(struct fxgmac_pdata* pdata);
|
|
/*for release phy,phy write and read, and provide clock to GMAC. */
|
|
void (*release_phy)(struct fxgmac_pdata* pdata);
|
|
#if !defined(UEFI)
|
|
void (*enable_phy_check)(struct fxgmac_pdata* pdata);
|
|
void (*disable_phy_check)(struct fxgmac_pdata* pdata);
|
|
void (*setup_cable_loopback)(struct fxgmac_pdata* pdata);
|
|
void (*clean_cable_loopback)(struct fxgmac_pdata* pdata);
|
|
void (*disable_phy_sleep)(struct fxgmac_pdata* pdata);
|
|
void (*enable_phy_sleep)(struct fxgmac_pdata* pdata);
|
|
void (*phy_green_ethernet)(struct fxgmac_pdata* pdata);
|
|
void (*phy_eee_feature)(struct fxgmac_pdata* pdata);
|
|
#endif
|
|
int (*get_ephy_state)(struct fxgmac_pdata* pdata);
|
|
int (*write_ephy_reg)(struct fxgmac_pdata* pdata, u32 val, u32 data);
|
|
int (*read_ephy_reg)(struct fxgmac_pdata* pdata, u32 val, u32 *data);
|
|
int (*set_ephy_autoneg_advertise)(struct fxgmac_pdata* pdata, struct fxphy_ag_adv phy_ag_adv);
|
|
int (*phy_config)(struct fxgmac_pdata* pdata);
|
|
void (*close_phy_led)(struct fxgmac_pdata* pdata);
|
|
void (*led_under_active)(struct fxgmac_pdata* pdata);
|
|
void (*led_under_sleep)(struct fxgmac_pdata* pdata);
|
|
void (*led_under_shutdown)(struct fxgmac_pdata* pdata);
|
|
void (*led_under_disable)(struct fxgmac_pdata* pdata);
|
|
|
|
/* For power management */
|
|
void (*pre_power_down)(struct fxgmac_pdata* pdata, bool phyloopback);
|
|
#if defined(LINUX)
|
|
int (*diag_sanity_check)(struct fxgmac_pdata *pdata);
|
|
int (*write_rss_lookup_table)(struct fxgmac_pdata *pdata);
|
|
int (*get_rss_hash_key)(struct fxgmac_pdata *pdata, u8 *key_buf);
|
|
void (*config_power_down)(struct fxgmac_pdata *pdata, unsigned int wol);
|
|
#else
|
|
void (*config_power_down)(struct fxgmac_pdata* pdata, unsigned int offloadcount, bool magic_en, bool remote_pattern_en);
|
|
#endif
|
|
void (*config_power_up)(struct fxgmac_pdata* pdata);
|
|
unsigned char (*set_suspend_int)(void* pdata);
|
|
void(*set_resume_int)(struct fxgmac_pdata* pdata);
|
|
int (*set_suspend_txrx)(struct fxgmac_pdata* pdata);
|
|
void (*set_pwr_clock_gate)(struct fxgmac_pdata* pdata);
|
|
void (*set_pwr_clock_ungate)(struct fxgmac_pdata* pdata);
|
|
|
|
/* for multicast address list */
|
|
int (*set_all_multicast_mode)(struct fxgmac_pdata* pdata, unsigned int enable);
|
|
void (*config_multicast_mac_hash_table)(struct fxgmac_pdata* pdata, unsigned char* pmc_mac, int b_add);
|
|
|
|
/* for packet filter-promiscuous and broadcast */
|
|
int (*set_promiscuous_mode)(struct fxgmac_pdata* pdata, unsigned int enable);
|
|
int (*enable_rx_broadcast)(struct fxgmac_pdata* pdata, unsigned int enable);
|
|
|
|
/* efuse relevant operation. */
|
|
bool (*read_patch_from_efuse)(struct fxgmac_pdata* pdata, u32 offset, u32* value); /* read patch per index. */
|
|
bool (*read_patch_from_efuse_per_index)(struct fxgmac_pdata* pdata, u8 index, u32* offset, u32* value); /* read patch per index. */
|
|
bool (*write_patch_to_efuse)(struct fxgmac_pdata* pdata, u32 offset, u32 value);
|
|
bool (*write_patch_to_efuse_per_index)(struct fxgmac_pdata* pdata, u8 index, u32 offset, u32 value);
|
|
bool (*read_mac_subsys_from_efuse)(struct fxgmac_pdata* pdata, u8* mac_addr, u32* subsys, u32* revid);
|
|
bool (*write_mac_subsys_to_efuse)(struct fxgmac_pdata* pdata, u8* mac_addr, u32* subsys, u32* revid);
|
|
bool (*read_mac_addr_from_efuse)(struct fxgmac_pdata* pdata, u8* mac_addr);
|
|
bool (*write_mac_addr_to_efuse)(struct fxgmac_pdata* pdata, u8* mac_addr);
|
|
bool (*efuse_load)(struct fxgmac_pdata* pdata);
|
|
bool (*read_efuse_data)(struct fxgmac_pdata* pdata, u32 offset, u32* value);
|
|
bool (*write_oob)(struct fxgmac_pdata* pdata);
|
|
bool (*write_led)(struct fxgmac_pdata* pdata, u32 value);
|
|
bool (*read_led_config)(struct fxgmac_pdata* pdata);
|
|
bool (*write_led_config)(struct fxgmac_pdata* pdata);
|
|
|
|
int (*pcie_init)(struct fxgmac_pdata* pdata, bool ltr_en, bool aspm_l1ss_en, bool aspm_l1_en, bool aspm_l0s_en);
|
|
void (*trigger_pcie)(struct fxgmac_pdata* pdata, u32 code); // To trigger pcie sniffer for analysis.
|
|
#ifdef DPDK
|
|
int (*phy_init)(struct fxgmac_pdata *);
|
|
int (*phy_start)(struct fxgmac_pdata *);
|
|
void (*phy_stop)(struct fxgmac_pdata *);
|
|
void (*phy_status)(struct fxgmac_pdata *);
|
|
void (*an_isr)(struct fxgmac_pdata *); /* phy_if->an_isr For single interrupt support */
|
|
#endif
|
|
};
|
|
|
|
/* This structure contains flags that indicate what hardware features
|
|
* or configurations are present in the device.
|
|
*/
|
|
struct fxgmac_hw_features {
|
|
/* HW Version */
|
|
unsigned int version;
|
|
|
|
/* HW Feature Register0 */
|
|
unsigned int phyifsel; /* PHY interface support */
|
|
unsigned int vlhash; /* VLAN Hash Filter */
|
|
unsigned int sma; /* SMA(MDIO) Interface */
|
|
unsigned int rwk; /* PMT remote wake-up packet */
|
|
unsigned int mgk; /* PMT magic packet */
|
|
unsigned int mmc; /* RMON module */
|
|
unsigned int aoe; /* ARP Offload */
|
|
unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
|
|
unsigned int eee; /* Energy Efficient Ethernet */
|
|
unsigned int tx_coe; /* Tx Checksum Offload */
|
|
unsigned int rx_coe; /* Rx Checksum Offload */
|
|
unsigned int addn_mac; /* Additional MAC Addresses */
|
|
unsigned int ts_src; /* Timestamp Source */
|
|
unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
|
|
|
|
/* HW Feature Register1 */
|
|
unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
|
|
unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
|
|
unsigned int adv_ts_hi; /* Advance Timestamping High Word */
|
|
unsigned int dma_width; /* DMA width */
|
|
unsigned int dcb; /* DCB Feature */
|
|
unsigned int sph; /* Split Header Feature */
|
|
unsigned int tso; /* TCP Segmentation Offload */
|
|
unsigned int dma_debug; /* DMA Debug Registers */
|
|
unsigned int rss; /* Receive Side Scaling */
|
|
unsigned int tc_cnt; /* Number of Traffic Classes */
|
|
unsigned int avsel; /* AV Feature Enable */
|
|
unsigned int ravsel; /* Rx Side Only AV Feature Enable */
|
|
unsigned int hash_table_size; /* Hash Table Size */
|
|
unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
|
|
|
|
/* HW Feature Register2 */
|
|
unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
|
|
unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
|
|
unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
|
|
unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
|
|
unsigned int pps_out_num; /* Number of PPS outputs */
|
|
unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
|
|
|
|
/* HW Feature Register3 */
|
|
u32 hwfr3;
|
|
};
|
|
|
|
struct fxgmac_resources {
|
|
IOMEM addr;
|
|
int irq;
|
|
};
|
|
|
|
struct fxgmac_pdata {
|
|
struct net_device *netdev;
|
|
struct device *dev;
|
|
PCI_DEV *pdev;
|
|
void *pAdapter;
|
|
|
|
struct fxgmac_hw_ops hw_ops;
|
|
struct fxgmac_desc_ops desc_ops;
|
|
|
|
/* Device statistics */
|
|
struct fxgmac_stats stats;
|
|
|
|
u32 msg_enable;
|
|
u32 reg_nonstick[0x300 >> 2];
|
|
|
|
/* MAC registers base */
|
|
IOMEM mac_regs;
|
|
IOMEM base_mem;
|
|
|
|
/* Hardware features of the device */
|
|
struct fxgmac_hw_features hw_feat;
|
|
|
|
/* Rings for Tx/Rx on a DMA channel */
|
|
struct fxgmac_channel *channel_head;
|
|
unsigned int channel_count;
|
|
unsigned int tx_ring_count;
|
|
unsigned int rx_ring_count;
|
|
unsigned int tx_desc_count;
|
|
unsigned int rx_desc_count;
|
|
unsigned int tx_q_count;
|
|
unsigned int rx_q_count;
|
|
|
|
/* Tx/Rx common settings */
|
|
unsigned int pblx8;
|
|
|
|
/* Tx settings */
|
|
unsigned int tx_sf_mode;
|
|
unsigned int tx_threshold;
|
|
unsigned int tx_pbl;
|
|
unsigned int tx_osp_mode;
|
|
#if FXGMAC_TX_HANG_TIMER_EN
|
|
/* for tx hang checking. 20211227 */
|
|
unsigned int tx_hang_restart_queuing;
|
|
#endif
|
|
|
|
/* Rx settings */
|
|
unsigned int rx_sf_mode;
|
|
unsigned int rx_threshold;
|
|
unsigned int rx_pbl;
|
|
|
|
/* Tx coalescing settings */
|
|
unsigned int tx_usecs;
|
|
unsigned int tx_frames;
|
|
|
|
/* Rx coalescing settings */
|
|
unsigned int rx_riwt;
|
|
unsigned int rx_usecs;
|
|
unsigned int rx_frames;
|
|
|
|
/* Current Rx buffer size */
|
|
unsigned int rx_buf_size;
|
|
|
|
/* Flow control settings */
|
|
unsigned int tx_pause;
|
|
unsigned int rx_pause;
|
|
|
|
/* Jumbo frames */
|
|
unsigned int mtu;
|
|
unsigned int jumbo;
|
|
|
|
/* CRC checking */
|
|
unsigned int crc_check;
|
|
|
|
/* MSIX */
|
|
unsigned int msix;
|
|
|
|
/* RSS */
|
|
unsigned int rss;
|
|
|
|
/* VlanID */
|
|
unsigned int vlan;
|
|
unsigned int vlan_exist;
|
|
unsigned int vlan_filter;
|
|
unsigned int vlan_strip;
|
|
|
|
/* Interrupt Moderation */
|
|
unsigned int intr_mod;
|
|
unsigned int intr_mod_timer;
|
|
|
|
/* Device interrupt number */
|
|
int dev_irq;
|
|
unsigned int per_channel_irq;
|
|
u32 channel_irq[FXGMAC_MAX_DMA_CHANNELS_PLUS_1TX]; // change type from int to u32 to match MSIx, p_msix_entry.vector;
|
|
|
|
/* Netdev related settings */
|
|
unsigned char mac_addr[ETH_ALEN];
|
|
|
|
/* Filtering support */
|
|
#if FXGMAC_FILTER_MULTIPLE_VLAN_ENABLED
|
|
unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
|
|
#endif
|
|
|
|
/* Device clocks */
|
|
unsigned long sysclk_rate;
|
|
|
|
/* Receive Side Scaling settings */
|
|
u8 rss_key[FXGMAC_RSS_HASH_KEY_SIZE];
|
|
u32 rss_table[FXGMAC_RSS_MAX_TABLE_SIZE];
|
|
u32 rss_options;
|
|
|
|
int phy_speed;
|
|
int phy_duplex;
|
|
int phy_autoeng;
|
|
|
|
char drv_name[32];
|
|
char drv_ver[32];
|
|
|
|
struct wol_bitmap_pattern pattern[MAX_PATTERN_COUNT];
|
|
|
|
struct led_setting led;
|
|
struct led_setting ledconfig;
|
|
|
|
FXGMAC_PDATA_OF_PLATFORM expansion;
|
|
|
|
u32 pcie_link_status;
|
|
};
|
|
|
|
//#ifdef CONFIG_PCI_MSI
|
|
#if 1
|
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#define FXGMAC_FLAG_MSI_CAPABLE (u32)(1 << 0) // bit0
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#define FXGMAC_FLAG_MSI_ENABLED (u32)(1 << 1) // bit1
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#define FXGMAC_FLAG_MSIX_CAPABLE (u32)(1 << 2) // bit2
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#define FXGMAC_FLAG_MSIX_ENABLED (u32)(1 << 3) // bit3
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#define FXGMAC_FLAG_LEGACY_ENABLED (u32)(1 << 4) // bit4
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#define FXGMAC_FLAG_INTERRUPT_POS 0
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#define FXGMAC_FLAG_INTERRUPT_LEN 5
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#define FXGMAC_FLAG_MSI_POS 1
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#define FXGMAC_FLAG_MSI_LEN 1
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#define FXGMAC_FLAG_MSIX_POS 3
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#define FXGMAC_FLAG_MSIX_LEN 1
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#define FXGMAC_FLAG_LEGACY_POS 4
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#define FXGMAC_FLAG_LEGACY_LEN 1
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#define FXGMAC_FLAG_LEGACY_IRQ_FREE_POS 31 //bit31
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#define FXGMAC_FLAG_LEGACY_IRQ_FREE_LEN 1
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#define FXGMAC_FLAG_LEGACY_NAPI_FREE_POS 30 //bit30
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#define FXGMAC_FLAG_LEGACY_NAPI_FREE_LEN 1
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#endif
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void fxgmac_init_desc_ops(struct fxgmac_desc_ops *desc_ops);
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void fxgmac_init_hw_ops(struct fxgmac_hw_ops *hw_ops);
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const struct net_device_ops *fxgmac_get_netdev_ops(void);
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const struct ethtool_ops *fxgmac_get_ethtool_ops(void);
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void fxgmac_dump_tx_desc(struct fxgmac_pdata *pdata,
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struct fxgmac_ring *ring,
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unsigned int idx,
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unsigned int count,
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unsigned int flag);
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void fxgmac_dump_rx_desc(struct fxgmac_pdata *pdata,
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struct fxgmac_ring *ring,
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unsigned int idx);
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void fxgmac_dbg_pkt(struct net_device *netdev,
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struct sk_buff *skb, bool tx_rx);
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void fxgmac_get_all_hw_features(struct fxgmac_pdata *pdata);
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void fxgmac_print_all_hw_features(struct fxgmac_pdata *pdata);
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int fxgmac_drv_probe(struct device *dev,
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struct fxgmac_resources *res);
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int fxgmac_drv_remove(struct device *dev);
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#endif /* __FUXI_GMAC_H__ */
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