542 lines
12 KiB
C
542 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*
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* Author: Zhang Yubing <yubing.zhang@rock-chips.com>
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*/
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#ifndef __X120_REG_H
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#define __X120_REG_H
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#include <linux/bits.h>
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#define HIWORD_MASK(h, l) (GENMASK(h, l) | GENMASK(h, l) << 16)
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#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
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#define HIWORD_UPDATE(v, m, l) (((v) << (l)) | (m << 16))
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/************** RKX120 DES RX ***************/
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#define RKX120_DES_CRU_BASE 0x01000000
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#define RKX120_DES_GRF_BASE 0x01010000
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#define GRF_REG(x) ((x) + RKX120_DES_GRF_BASE)
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#define DES_GRF_GPIO0A_IOMUX_L GRF_REG(0x0)
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#define DES_GRF_GPIO0A_IOMUX_H GRF_REG(0x4)
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#define DES_GRF_GPIO0B_IOMUX_L GRF_REG(0x8)
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#define DES_GRF_GPIO0B_IOMUX_H GRF_REG(0xC)
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#define DES_GRF_GPIO0C_IOMUX_L GRF_REG(0x10)
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#define DES_GRF_GPIO0C_IOMUX_H GRF_REG(0x14)
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#define DES_GRF_GPIO0A_PULL_EN GRF_REG(0x20)
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#define DES_GRF_GPIO0B_PULL_EN GRF_REG(0x24)
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#define DES_GRF_GPIO0C_PULL_EN GRF_REG(0x28)
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#define DES_GRF_GPIO1A_IOMUX GRF_REG(0x80)
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#define DES_GRF_GPIO1B_IOMUX GRF_REG(0x84)
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#define DES_GRF_GPIO1C_IOMUX GRF_REG(0x88)
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#define DES_GRF_GPIO1A_PULL_CFG GRF_REG(0x90)
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#define DES_GRF_GPIO1B_PULL_CFG GRF_REG(0x94)
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#define DES_GRF_GPIO1C_PULL_CFG GRF_REG(0x98)
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#define DES_GRF_SOC_CON2 GRF_REG(0x108)
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#define DES_GRF_SOC_STATUS0 GRF_REG(0x160)
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enum {
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/* GPIO0A_IOMUX_H */
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GPIO0A7_SHIFT = 12,
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GPIO0A7_MASK = GENMASK(14, 12),
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GPIO0A7_GPIO = 0,
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GPIO0A7_SPI_MISO_M,
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GPIO0A7_SPI_MISO_S,
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GPIO0A7_UART1_TX_M,
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GPIO0A7_UART1_TX_S,
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GPIO0A7_GPO_2,
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GPIO0A7_GPI_2,
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GPIO0A7_PWM_0,
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GPIO0A6_SHIFT = 8,
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GPIO0A6_MASK = GENMASK(10, 8),
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GPIO0A6_GPIO = 0,
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GPIO0A6_SPI_MOSI_M,
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GPIO0A6_SPI_MOSI_S,
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GPIO0A6_UART0_RX_M,
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GPIO0A6_UART0_RX_S,
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GPIO0A6_GPO_1,
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GPIO0A6_GPI_1,
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GPIO0A6_I2C_DEBUG_SDA,
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GPIO0A5_SHIFT = 4,
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GPIO0A5_MASK = GENMASK(6, 4),
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GPIO0A5_GPIO = 0,
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GPIO0A5_SPI_CLK_M,
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GPIO0A5_SPI_CLK_S,
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GPIO0A5_UART0_TX_M,
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GPIO0A5_UART0_TX_S,
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GPIO0A5_GPO_0,
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GPIO0A5_GPI_0,
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GPIO0A5_I2C_DEBUG_SCL,
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GPIO0A4_SHIFT = 0,
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GPIO0A4_MASK = GENMASK(2, 0),
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GPIO0A4_GPIO = 0,
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GPIO0A4_INT_RX,
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GPIO0A4_INT_TX,
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/* GPIO0B_IOMUX_L */
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GPIO0B3_SHIFT = 12,
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GPIO0B3_MASK = GENMASK(14, 12),
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GPIO0B3_GPIO = 0,
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GPIO0B3_I2S_SDO0,
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GPIO0B3_GPI_4,
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GPIO0B3_GPO_4,
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GPIO0B3_TP2,
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GPIO0B2_SHIFT = 8,
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GPIO0B2_MASK = GENMASK(10, 8),
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GPIO0B2_GPIO = 0,
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GPIO0B2_I2S_LRCK_M,
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GPIO0B2_I2S_LRCK_S,
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GPIO0B2_TP1,
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GPIO0B1_SHIFT = 4,
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GPIO0B1_MASK = GENMASK(6, 4),
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GPIO0B1_GPIO = 0,
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GPIO0B1_I2S_SCLK_M,
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GPIO0B1_I2S_SCLK_S,
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GPIO0B1_TP0,
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GPIO0B0_SHIFT = 0,
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GPIO0B0_MASK = GENMASK(2, 0),
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GPIO0B0_GPIO = 0,
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GPIO0B0_SPI_CSN_M,
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GPIO0B0_SPI_CSN_S,
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GPIO0B0_UART1_RX_M,
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GPIO0B0_UART1_RX_S,
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GPIO0B0_GPO_3,
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GPIO0B0_GPI_3,
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GPIO0B0_PWM_1,
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/* GPIO0B_IOMUX_H */
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GPIO0B7_SHIFT = 12,
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GPIO0B7_MASK = GENMASK(14, 12),
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GPIO0B7_GPIO = 0,
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GPIO0B7_I2S_MCLK,
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GPIO0B7_TEST_CLK_OUT,
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GPIO0B7_TP6,
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GPIO0B6_SHIFT = 8,
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GPIO0B6_MASK = GENMASK(10, 8),
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GPIO0B6_GPIO = 0,
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GPIO0B6_I2S_SDO3,
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GPIO0B6_I2S_SDI0,
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GPIO0B6_TP5,
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GPIO0B5_SHIFT = 4,
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GPIO0B5_MASK = GENMASK(6, 4),
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GPIO0B5_GPIO = 0,
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GPIO0B5_I2S_SDO2,
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GPIO0B5_GPI_6,
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GPIO0B5_GPO_6,
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GPIO0B5_I2C1_SDA_M,
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GPIO0B5_I2C1_SDA_S,
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GPIO0B5_TP4,
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GPIO0B4_SHIFT = 0,
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GPIO0B4_MASK = GENMASK(2, 0),
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GPIO0B4_GPIO = 0,
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GPIO0B5_I2S_SDO1,
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GPIO0B5_GPI_5,
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GPIO0B5_GPO_5,
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GPIO0B5_I2C1_SCL_M,
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GPIO0B5_I2C1_SCL_S,
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GPIO0B5_PWM2,
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GPIO0B5_TP3,
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/* GPIO0C_IOMUX_L */
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GPIO0C4_SHIFT = 12,
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GPIO0C4_MASK = GENMASK(14, 12),
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GPIO0C4_GPIO = 0,
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GPIO0C4_LCDC_D0,
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GPIO0C4_CIF_D0,
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GPIO0C4_TP11,
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GPIO0C3_SHIFT = 9,
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GPIO0C3_MASK = GENMASK(11, 9),
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GPIO0C3_GPIO = 0,
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GPIO0C3_LCDC_DEN,
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GPIO0C3_TP10,
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GPIO0C2_SHIFT = 6,
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GPIO0C2_MASK = GENMASK(8, 6),
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GPIO0C2_GPIO = 0,
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GPIO0C2_LCDC_HSYNC,
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GPIO0C2_CIF_HSYNC,
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GPIO0C2_TP9,
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GPIO0C1_SHIFT = 3,
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GPIO0C1_MASK = GENMASK(5, 3),
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GPIO0C1_GPIO = 0,
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GPIO0C1_LCDC_VSYNC,
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GPIO0C1_CIF_VSYNC,
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GPIO0C1_TP8,
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GPIO0C0_SHIFT = 0,
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GPIO0C0_MASK = GENMASK(2, 0),
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GPIO0C0_GPIO = 0,
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GPIO0C0_LCDC_CLK,
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GPIO0C0_CIF_CLK,
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GPIO0C0_TP7,
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/* GPIO0C_IOMUX_H */
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GPIO0C7_SHIFT = 6,
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GPIO0C7_MASK = GENMASK(8, 6),
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GPIO0C7_GPIO = 0,
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GPIO0C7_LCDC_D3,
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GPIO0C7_CIF_D3,
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GPIO0C7_TP14,
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GPIO0C6_SHIFT = 3,
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GPIO0C6_MASK = GENMASK(5, 3),
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GPIO0C6_GPIO = 0,
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GPIO0C6_LCDC_D2,
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GPIO0C6_CIF_D2,
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GPIO0C6_TP13,
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GPIO0C5_SHIFT = 0,
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GPIO0C5_MASK = GENMASK(2, 0),
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GPIO0C5_GPIO = 0,
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GPIO0C5_LCDC_D1,
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GPIO0C5_CIF_D1,
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GPIO0C5_TP12,
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/* GPIO1A_IOMUX */
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GPIO1A7_SHIFT = 14,
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GPIO1A7_MASK = GENMASK(15, 14),
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GPIO1A7_GPIO = 0,
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GPIO1A7_LCDC_D11,
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GPIO1A7_CIF_D11,
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GPIO1A6_SHIFT = 12,
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GPIO1A6_MASK = GENMASK(13, 12),
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GPIO1A6_GPIO = 0,
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GPIO1A6_LCDC_D10,
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GPIO1A6_CIF_D10,
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GPIO1A5_SHIFT = 10,
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GPIO1A5_MASK = GENMASK(11, 10),
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GPIO1A5_GPIO = 0,
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GPIO1A5_LCDC_D9,
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GPIO1A5_CIF_D9,
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GPIO1A4_SHIFT = 8,
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GPIO1A4_MASK = GENMASK(9, 8),
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GPIO1A4_GPIO = 0,
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GPIO1A4_LCDC_D8,
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GPIO1A4_CIF_D8,
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GPIO1A3_SHIFT = 6,
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GPIO1A3_MASK = GENMASK(7, 6),
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GPIO1A3_GPIO = 0,
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GPIO1A3_LCDC_D7,
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GPIO1A3_CIF_D7,
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GPIO1A2_SHIFT = 4,
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GPIO1A2_MASK = GENMASK(5, 4),
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GPIO1A2_GPIO = 0,
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GPIO1A2_LCDC_D6,
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GPIO1A2_CIF_D6,
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GPIO1A1_SHIFT = 2,
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GPIO1A1_MASK = GENMASK(3, 2),
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GPIO1A1_GPIO = 0,
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GPIO1A1_LCDC_D5,
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GPIO1A1_CIF_D5,
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GPIO1A0_SHIFT = 0,
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GPIO1A0_MASK = GENMASK(1, 0),
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GPIO1A0_GPIO = 0,
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GPIO1A0_LCDC_D4,
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GPIO1A0_CIF_D4,
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/* GPIO1B_IOMUX */
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GPIO1B7_SHIFT = 14,
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GPIO1B7_MASK = GENMASK(15, 14),
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GPIO1B7_GPIO = 0,
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GPIO1B7_LCDC_D19,
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GPIO1B6_SHIFT = 12,
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GPIO1B6_MASK = GENMASK(13, 12),
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GPIO1B6_GPIO = 0,
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GPIO1B6_LCDC_D18,
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GPIO1B5_SHIFT = 10,
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GPIO1B5_MASK = GENMASK(11, 10),
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GPIO1B5_GPIO = 0,
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GPIO1B5_LCDC_D17,
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GPIO1B4_SHIFT = 8,
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GPIO1B4_MASK = GENMASK(9, 8),
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GPIO1B4_GPIO = 0,
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GPIO1B4_LCDC_D16,
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GPIO1B3_SHIFT = 6,
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GPIO1B3_MASK = GENMASK(7, 6),
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GPIO1B3_GPIO = 0,
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GPIO1B3_LCDC_D15,
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GPIO1B3_CIF_D15,
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GPIO1B2_SHIFT = 4,
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GPIO1B2_MASK = GENMASK(5, 4),
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GPIO1B2_GPIO = 0,
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GPIO1B2_LCDC_D14,
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GPIO1B2_CIF_D14,
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GPIO1B1_SHIFT = 2,
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GPIO1B1_MASK = GENMASK(3, 2),
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GPIO1B1_GPIO = 0,
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GPIO1B1_LCDC_D13,
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GPIO1B1_CIF_D13,
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GPIO1B0_SHIFT = 0,
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GPIO1B0_MASK = GENMASK(1, 0),
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GPIO1B0_GPIO = 0,
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GPIO1B0_LCDC_D12,
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GPIO1B0_CIF_D12,
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/* GPIO1C_IOMUX */
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GPIO1C3_SHIFT = 6,
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GPIO1C3_MASK = GENMASK(7, 6),
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GPIO1C3_GPIO = 0,
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GPIO1C3_LCDC_D23,
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GPIO1C2_SHIFT = 4,
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GPIO1C2_MASK = GENMASK(5, 4),
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GPIO1C2_GPIO = 0,
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GPIO1C2_LCDC_D22,
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GPIO1C1_SHIFT = 2,
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GPIO1C1_MASK = GENMASK(3, 2),
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GPIO1C1_GPIO = 0,
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GPIO1C1_LCDC_D21,
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GPIO1C0_SHIFT = 0,
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GPIO1C0_MASK = GENMASK(1, 0),
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GPIO1C0_GPIO = 0,
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GPIO1C0_LCDC_D20,
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};
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#define DES_GRF_SOC_CON0 GRF_REG(0x100)
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#define DES_GRF_SOC_CON1 GRF_REG(0x104)
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#define DES_GRF_SOC_CON2 GRF_REG(0x108)
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#define DES_GRF_SOC_CON3 GRF_REG(0x10C)
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#define DES_GRF_SOC_CON4 GRF_REG(0x110)
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#define DES_GRF_SOC_CON5 GRF_REG(0x114)
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#define DES_GRF_SOC_CON6 GRF_REG(0x118)
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#define DES_GRF_SOC_CON7 GRF_REG(0x11C)
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#define DES_GRF_IRQ_EN GRF_REG(0x140)
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#define DES_GRF_IRQ_STATUS GRF_REG(0x150)
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enum {
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/* SOC_CON0 */
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LVDS_ALIGN_EN_SHIFT = 14,
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LVDS_ALIGN_EN_MASK = GENMASK(15, 14),
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LVDS_ALIGN_DISABLE = 0,
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LVDS_ALIGN_EN,
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/* SOC_CON2 */
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LVDS1_LINK_SEL_SHIFT = 14,
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LVDS1_LINK_SEL_MASK = GENMASK(14, 14),
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/* enable lvds source from pattern generation */
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LINK_SEL_PG_DISABLE = 0,
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LINK_SEL_PG_EN = 1,
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LVDS0_LINK_SEL_SHIFT = 13,
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LVDS0_LINK_SEL_MASK = GENMASK(13, 13),
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DSI0_LINK_SEL_SHIFT = 12,
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DSI0_LINK_SEL_MASK = GENMASK(12, 12),
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LVDS1_MSB_SHIFT = 5,
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LVDS1_MSB_MASK = GENMASK(5, 5),
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LVDS_LSB = 0,
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LVDS_MSB,
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LVDS1_FORMAT_SHIFT = 4,
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LVDS1_FORMAT_MASK = GENMASK(4, 3),
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LVDS_FORMAT_VESA_24BIT = 0,
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LVDS_FORMAT_JEIDA_24BIT,
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LVDS_FORMAT_JEIDA_18BIT,
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LVDS_FORMAT_VESA_18BIT,
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LVDS0_MSB_SHIFT = 2,
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LVDS0_MSB_MASK = GENMASK(2, 2),
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LVDS0_FORMAT_SHIFT = 0,
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LVDS0_FORMAT_MASK = GENMASK(1, 0),
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/* SOC_CON3 */
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/* SOC_CON4 */
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PMA1_EN_SHIFT = 11,
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PMA1_EN_MASK = HIWORD_MASK(11, 11),
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PMA1_EN = HIWORD_UPDATE(1, BIT(11), 11),
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PMA1_DISABLE = HIWORD_UPDATE(0, BIT(11), 11),
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PMA0_EN_SHIFT = 10,
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PMA0_EN_MASK = HIWORD_MASK(10, 10),
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PMA0_EN = HIWORD_UPDATE(1, BIT(10), 10),
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PMA0_DISABLE = HIWORD_UPDATE(0, BIT(10), 10),
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RGB_DCLK_BYPASS_SHIFT = 9,
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RGB_DCLK_BYPASS_MASK = GENMASK(9, 9),
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RGB_DCLK_DCLK_DLY_SHIFT = 1,
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RGB_DCLK_DCLK_DLY_MASK = GENMASK(8, 1),
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RGB_DCLK_INV_SHIFT = 0,
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RGB_DCLK_INV_MASK = GENMASK(0, 0),
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/* SOC_CON5 */
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MIPI_PHY0_MODE_SEL_SHIFT = 4,
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MIPI_PHY0_MODE_SEL_MASK = GENMASK(7, 4),
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MIPI_PHY0_MODE_DSI = 0,
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MIPI_PHY0_MODE_CSI,
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/* SOC_CON6 */
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LVDS0_CLK_SOURCE_SHIFT = 0,
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LVDS0_CLK_SOURCE_MASK = GENMASK(3, 0),
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/* SOC_CON7 */
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LVDS1_CLK_SOURCE_SHIFT = 4,
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LVDS1_CLK_SOURCE_MASK = GENMASK(15, 4),
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DSI0_DPI_UPDATE_CFG_SHIFT = 2,
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DSI0_DPI_UPDATE_CFG_MASK = GENMASK(2, 2),
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DSI0_DPI_REDUCED_COLOR_SHIFT = 1,
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DSI0_DPI_REDUCED_COLOR_MASK = GENMASK(1, 1),
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DSI0_DPI_DISABLE_SHIFT = 0,
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DSI0_DPI_DISABLE_MASK = GENMASK(0, 0),
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/* SOC_CON8 */
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LDO_PLC_SEL_SHIFT = 8,
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LDO_PLC_SEL_MASK = GENMASK(8, 8),
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LDO_PLC_170 = 0,
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LDO_PLC_270,
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LDO_VOL_SEL_SHIFT = 4,
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LDO_VOL_SEL_MASK = GENMASK(7, 4),
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LDO_VOL_110 = 0,
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LDO_PLC_115,
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LDO_BG_TRIM_SHIFT = 4,
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LDO_BG_TRIM_MASK = GENMASK(7, 4),
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LDO_BG_TRIM_OUT = 0,
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LDO_BG_TRIM_OUT_55_N = 0,
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LDO_BG_TRIM_OUT_110_N,
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/* SOC_CON9 */
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/* DES_GRF_IRQ_EN */
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DES_IRQ_OTHER_LANE_EN = HIWORD_UPDATE(1, BIT(15), 15),
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DES_IRQ_OTHER_LANE_DIS = HIWORD_UPDATE(0, BIT(15), 15),
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DES_IRQ_EXT_EN = HIWORD_UPDATE(1, BIT(14), 14),
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DES_IRQ_EXT_DIS = HIWORD_UPDATE(0, BIT(14), 14),
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DES_IRQ_LINK_EN = HIWORD_UPDATE(1, BIT(13), 13),
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DES_IRQ_LINK_DIS = HIWORD_UPDATE(0, BIT(13), 13),
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DES_IRQ_DVP_TX_EN = HIWORD_UPDATE(1, BIT(12), 12),
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DES_IRQ_DVP_TX_DIS = HIWORD_UPDATE(0, BIT(12), 12),
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DES_IRQ_PWM_EN = HIWORD_UPDATE(1, BIT(11), 11),
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DES_IRQ_PWM_DIS = HIWORD_UPDATE(0, BIT(11), 11),
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DES_IRQ_REMOTE_EN = HIWORD_UPDATE(1, BIT(10), 10),
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DES_IRQ_REMOTE_DIS = HIWORD_UPDATE(0, BIT(10), 10),
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DES_IRQ_PMA_ADAPT1_EN = HIWORD_UPDATE(1, BIT(9), 9),
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DES_IRQ_PMA_ADAPT1_DIS = HIWORD_UPDATE(0, BIT(9), 9),
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DES_IRQ_PMA_ADAPT0_EN = HIWORD_UPDATE(1, BIT(8), 8),
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DES_IRQ_PMA_ADAPT0_DIS = HIWORD_UPDATE(0, BIT(8), 8),
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DES_IRQ_MIPI_DSI_HOST_EN = HIWORD_UPDATE(1, BIT(7), 7),
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DES_IRQ_MIPI_DSI_HOST_DIS = HIWORD_UPDATE(0, BIT(7), 7),
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DES_IRQ_CSITX1_EN = HIWORD_UPDATE(1, BIT(6), 6),
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DES_IRQ_CSITX1_DIS = HIWORD_UPDATE(0, BIT(6), 6),
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DES_IRQ_CSITX0_EN = HIWORD_UPDATE(1, BIT(5), 5),
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DES_IRQ_CSITX0_DIS = HIWORD_UPDATE(0, BIT(5), 5),
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DES_IRQ_GPIO1_EN = HIWORD_UPDATE(1, BIT(4), 4),
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DES_IRQ_GPIO1_DIS = HIWORD_UPDATE(0, BIT(4), 4),
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DES_IRQ_GPIO0_EN = HIWORD_UPDATE(1, BIT(3), 3),
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DES_IRQ_GPIO0_DIS = HIWORD_UPDATE(0, BIT(3), 3),
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DES_IRQ_EFUSE_EN = HIWORD_UPDATE(1, BIT(2), 2),
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DES_IRQ_EFUSE_DIS = HIWORD_UPDATE(0, BIT(2), 2),
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DES_IRQ_PCS1_EN = HIWORD_UPDATE(1, BIT(1), 1),
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DES_IRQ_PCS1_DIS = HIWORD_UPDATE(0, BIT(1), 1),
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DES_IRQ_PCS0_EN = HIWORD_UPDATE(1, BIT(0), 0),
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DES_IRQ_PCS0_DIS = HIWORD_UPDATE(0, BIT(0), 0),
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/* DES_GRF_IRQ_STATUS */
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DES_IRQ_PCS0 = BIT(0),
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DES_IRQ_PCS1 = BIT(1),
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DES_IRQ_EFUSE = BIT(2),
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DES_IRQ_GPIO0 = BIT(3),
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DES_IRQ_GPIO1 = BIT(4),
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DES_IRQ_CSITX0 = BIT(5),
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DES_IRQ_CSITX1 = BIT(6),
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DES_IRQ_MIPI_DSI_HOST = BIT(7),
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DES_IRQ_PMA_ADAPT0 = BIT(8),
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DES_IRQ_PMA_ADAPT1 = BIT(9),
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DES_IRQ_REMOTE = BIT(10),
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DES_IRQ_PWM = BIT(11),
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DES_IRQ_DVP_TX = BIT(12),
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DES_IRQ_LINK = BIT(13),
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DES_IRQ_EXT = BIT(14),
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DES_IRQ_OTHER_LANE = BIT(15),
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/* DES_GRF_SOC_STATUS0 */
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DES_PCS1_READY = BIT(1),
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DES_PCS0_READY = BIT(0),
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};
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#define RKX120_DVP_TX_BASE 0x01020000
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#define RKX120_DSI_TX_BASE 0x01030000
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#define RKX120_CSI_TX0_BASE 0x01040000
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#define RKX120_CSI_TX1_BASE 0x01050000
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#define RKX120_GPIO0_TX_BASE 0x01060000
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#define RKX120_GPIO1_TX_BASE 0x01068000
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#define RKX120_DES_RKLINK_BASE 0x01070000
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#define RKX120_DES_PCS0_BASE 0x01074000
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#define RKX120_DES_PCS1_BASE 0x01075000
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#define RKX120_DES_PCS_OFFSET 0x00001000
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#define RKX120_PWM_BASE 0x01080000
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#define PWM_REG(x) ((x) + RKX120_PWM_BASE)
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#define PWM_CNT(ch) (PWM_REG(0x0000) + 0x10 * ch)
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#define PWM_PERIOD_HPR(ch) (PWM_REG(0x0004) + 0x10 * ch)
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#define PWM_DUTY_LPR(ch) (PWM_REG(0x0008) + 0x10 * ch)
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#define PWM_CTRL(ch) (PWM_REG(0x000C) + 0x10 * ch)
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#define RKX120_EFUSE_BASE 0x01090000
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#define RKX120_MIPI_LVDS_TX_PHY0_BASE 0x010A0000
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#define RKX120_MIPI_LVDS_TX_PHY1_BASE 0x010B0000
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#define RKX120_GRF_MIPI0_BASE 0x010C0000
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#define RKX120_GRF_MIPI1_BASE 0x010D0000
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#define RKX120_DES_PMA0_BASE 0x010E0000
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#define RKX120_DES_PMA1_BASE 0x010F0000
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#define RKX120_DES_PMA_OFFSET 0x00010000
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#define RKX120_PATTERN_GEN_DSI_BASE 0x01100000
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#define RKX120_PATTERN_GEN_LVDS0_BASE 0x01110000
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#define RKX120_PATTERN_GEN_LVDS1_BASE 0x01120000
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#endif
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