1189 lines
60 KiB
C
1189 lines
60 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2023 Rockchip Electronics Co., Ltd. */
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#ifndef _RKVPSS_REGS_H
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#define _RKVPSS_REGS_H
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#define RKVPSS_VPSS_BASE 0x0000
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#define RKVPSS_VPSS_CTRL (RKVPSS_VPSS_BASE + 0x0000)
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#define RKVPSS_VPSS_ONLINE (RKVPSS_VPSS_BASE + 0x0004)
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#define RKVPSS_VPSS_ONLINE2_SIZE (RKVPSS_VPSS_BASE + 0x0008)
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#define RKVPSS_VPSS_VERSION (RKVPSS_VPSS_BASE + 0x000c)
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#define RKVPSS_VPSS_UPDATE (RKVPSS_VPSS_BASE + 0x0010)
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#define RKVPSS_VPSS_CLK_EN (RKVPSS_VPSS_BASE + 0x0014)
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#define RKVPSS_VPSS_CLK_GATE (RKVPSS_VPSS_BASE + 0x0018)
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#define RKVPSS_VPSS_RESET (RKVPSS_VPSS_BASE + 0x001c)
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#define RKVPSS_VPSS_SLICE_CTRL (RKVPSS_VPSS_BASE + 0x0020)
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#define RKVPSS_VPSS_IRQ_CFG (RKVPSS_VPSS_BASE + 0x0050)
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#define RKVPSS_VPSS_IMSC (RKVPSS_VPSS_BASE + 0x0070)
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#define RKVPSS_VPSS_RIS (RKVPSS_VPSS_BASE + 0x0074)
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#define RKVPSS_VPSS_MIS (RKVPSS_VPSS_BASE + 0x0078)
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#define RKVPSS_VPSS_ICR (RKVPSS_VPSS_BASE + 0x007c)
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#define RKVPSS_VPSS_ISR (RKVPSS_VPSS_BASE + 0x0080)
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#define RKVPSS_VPSS_CTRL_SHD (RKVPSS_VPSS_BASE + 0x0090)
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#define RKVPSS_VPSS_ONLINE_SHD (RKVPSS_VPSS_BASE + 0x0094)
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#define RKVPSS_VPSS_ONLINE2_SIZE_SHD (RKVPSS_VPSS_BASE + 0x0098)
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#define RKVPSS_VPSS_WORK (RKVPSS_VPSS_BASE + 0x00a0)
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#define RKVPSS_VPSS_PIPE_ACK0 (RKVPSS_VPSS_BASE + 0x00b0)
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#define RKVPSS_VPSS_PIPE_ACK1 (RKVPSS_VPSS_BASE + 0x00b4)
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#define RKVPSS_VPSS_LINE_CNT0 (RKVPSS_VPSS_BASE + 0x00c0)
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#define RKVPSS_VPSS_LINE_CNT1 (RKVPSS_VPSS_BASE + 0x00c4)
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#define RKVPSS_VPSS_Y2R_COE00 (RKVPSS_VPSS_BASE + 0x00d0)
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#define RKVPSS_VPSS_Y2R_COE01 (RKVPSS_VPSS_BASE + 0x00d4)
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#define RKVPSS_VPSS_Y2R_COE02 (RKVPSS_VPSS_BASE + 0x00d8)
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#define RKVPSS_VPSS_Y2R_OFF0 (RKVPSS_VPSS_BASE + 0x00dc)
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#define RKVPSS_VPSS_Y2R_COE10 (RKVPSS_VPSS_BASE + 0x00e0)
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#define RKVPSS_VPSS_Y2R_COE11 (RKVPSS_VPSS_BASE + 0x00e4)
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#define RKVPSS_VPSS_Y2R_COE12 (RKVPSS_VPSS_BASE + 0x00e8)
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#define RKVPSS_VPSS_Y2R_OFF1 (RKVPSS_VPSS_BASE + 0x00ec)
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#define RKVPSS_VPSS_Y2R_COE20 (RKVPSS_VPSS_BASE + 0x00f0)
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#define RKVPSS_VPSS_Y2R_COE21 (RKVPSS_VPSS_BASE + 0x00f4)
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#define RKVPSS_VPSS_Y2R_COE22 (RKVPSS_VPSS_BASE + 0x00f8)
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#define RKVPSS_VPSS_Y2R_OFF2 (RKVPSS_VPSS_BASE + 0x00fc)
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#define RKVPSS_CMSC_BASE 0x0500
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#define RKVPSS_CMSC_CTRL (RKVPSS_CMSC_BASE + 0x0000)
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#define RKVPSS_CMSC_UPDATE (RKVPSS_CMSC_BASE + 0x0004)
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#define RKVPSS_CMSC_INTSCT_CORR (RKVPSS_CMSC_BASE + 0x0008)
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#define RKVPSS_CMSC_CHN0_WIN (RKVPSS_CMSC_BASE + 0x0010)
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#define RKVPSS_CMSC_CHN1_WIN (RKVPSS_CMSC_BASE + 0x0014)
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#define RKVPSS_CMSC_CHN2_WIN (RKVPSS_CMSC_BASE + 0x0018)
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#define RKVPSS_CMSC_CHN3_WIN (RKVPSS_CMSC_BASE + 0x001c)
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#define RKVPSS_CMSC_CHN0_MODE (RKVPSS_CMSC_BASE + 0x0020)
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#define RKVPSS_CMSC_CHN1_MODE (RKVPSS_CMSC_BASE + 0x0024)
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#define RKVPSS_CMSC_CHN2_MODE (RKVPSS_CMSC_BASE + 0x0028)
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#define RKVPSS_CMSC_CHN3_MODE (RKVPSS_CMSC_BASE + 0x002c)
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#define RKVPSS_CMSC_WIN0_PARA (RKVPSS_CMSC_BASE + 0x0030)
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#define RKVPSS_CMSC_WIN1_PARA (RKVPSS_CMSC_BASE + 0x0034)
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#define RKVPSS_CMSC_WIN2_PARA (RKVPSS_CMSC_BASE + 0x0038)
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#define RKVPSS_CMSC_WIN3_PARA (RKVPSS_CMSC_BASE + 0x003c)
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#define RKVPSS_CMSC_WIN4_PARA (RKVPSS_CMSC_BASE + 0x0040)
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#define RKVPSS_CMSC_WIN5_PARA (RKVPSS_CMSC_BASE + 0x0044)
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#define RKVPSS_CMSC_WIN6_PARA (RKVPSS_CMSC_BASE + 0x0048)
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#define RKVPSS_CMSC_WIN7_PARA (RKVPSS_CMSC_BASE + 0x004c)
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#define RKVPSS_CMSC_WIN0_L0_VTX (RKVPSS_CMSC_BASE + 0x0050)
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#define RKVPSS_CMSC_WIN0_L0_SLP (RKVPSS_CMSC_BASE + 0x0054)
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#define RKVPSS_CMSC_WIN0_L1_VTX (RKVPSS_CMSC_BASE + 0x0058)
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#define RKVPSS_CMSC_WIN0_L1_SLP (RKVPSS_CMSC_BASE + 0x005c)
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#define RKVPSS_CMSC_WIN0_L2_VTX (RKVPSS_CMSC_BASE + 0x0060)
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#define RKVPSS_CMSC_WIN0_L2_SLP (RKVPSS_CMSC_BASE + 0x0064)
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#define RKVPSS_CMSC_WIN0_L3_VTX (RKVPSS_CMSC_BASE + 0x0068)
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#define RKVPSS_CMSC_WIN0_L3_SLP (RKVPSS_CMSC_BASE + 0x006c)
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#define RKVPSS_CMSC_WIN1_L0_VTX (RKVPSS_CMSC_BASE + 0x0070)
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#define RKVPSS_CMSC_WIN1_L0_SLP (RKVPSS_CMSC_BASE + 0x0074)
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#define RKVPSS_CMSC_WIN1_L1_VTX (RKVPSS_CMSC_BASE + 0x0078)
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#define RKVPSS_CMSC_WIN1_L1_SLP (RKVPSS_CMSC_BASE + 0x007c)
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#define RKVPSS_CMSC_WIN1_L2_VTX (RKVPSS_CMSC_BASE + 0x0080)
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#define RKVPSS_CMSC_WIN1_L2_SLP (RKVPSS_CMSC_BASE + 0x0084)
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#define RKVPSS_CMSC_WIN1_L3_VTX (RKVPSS_CMSC_BASE + 0x0088)
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#define RKVPSS_CMSC_WIN1_L3_SLP (RKVPSS_CMSC_BASE + 0x008c)
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#define RKVPSS_CMSC_WIN2_L0_VTX (RKVPSS_CMSC_BASE + 0x0090)
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#define RKVPSS_CMSC_WIN2_L0_SLP (RKVPSS_CMSC_BASE + 0x0094)
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#define RKVPSS_CMSC_WIN2_L1_VTX (RKVPSS_CMSC_BASE + 0x0098)
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#define RKVPSS_CMSC_WIN2_L1_SLP (RKVPSS_CMSC_BASE + 0x009c)
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#define RKVPSS_CMSC_WIN2_L2_VTX (RKVPSS_CMSC_BASE + 0x00a0)
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#define RKVPSS_CMSC_WIN2_L2_SLP (RKVPSS_CMSC_BASE + 0x00a4)
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#define RKVPSS_CMSC_WIN2_L3_VTX (RKVPSS_CMSC_BASE + 0x00a8)
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#define RKVPSS_CMSC_WIN2_L3_SLP (RKVPSS_CMSC_BASE + 0x00ac)
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#define RKVPSS_CMSC_WIN3_L0_VTX (RKVPSS_CMSC_BASE + 0x00b0)
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#define RKVPSS_CMSC_WIN3_L0_SLP (RKVPSS_CMSC_BASE + 0x00b4)
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#define RKVPSS_CMSC_WIN3_L1_VTX (RKVPSS_CMSC_BASE + 0x00b8)
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#define RKVPSS_CMSC_WIN3_L1_SLP (RKVPSS_CMSC_BASE + 0x00bc)
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#define RKVPSS_CMSC_WIN3_L2_VTX (RKVPSS_CMSC_BASE + 0x00c0)
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#define RKVPSS_CMSC_WIN3_L2_SLP (RKVPSS_CMSC_BASE + 0x00c4)
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#define RKVPSS_CMSC_WIN3_L3_VTX (RKVPSS_CMSC_BASE + 0x00c8)
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#define RKVPSS_CMSC_WIN3_L3_SLP (RKVPSS_CMSC_BASE + 0x00cc)
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#define RKVPSS_CMSC_WIN4_L0_VTX (RKVPSS_CMSC_BASE + 0x00d0)
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#define RKVPSS_CMSC_WIN4_L0_SLP (RKVPSS_CMSC_BASE + 0x00d4)
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#define RKVPSS_CMSC_WIN4_L1_VTX (RKVPSS_CMSC_BASE + 0x00d8)
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#define RKVPSS_CMSC_WIN4_L1_SLP (RKVPSS_CMSC_BASE + 0x00dc)
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#define RKVPSS_CMSC_WIN4_L2_VTX (RKVPSS_CMSC_BASE + 0x00e0)
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#define RKVPSS_CMSC_WIN4_L2_SLP (RKVPSS_CMSC_BASE + 0x00e4)
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#define RKVPSS_CMSC_WIN4_L3_VTX (RKVPSS_CMSC_BASE + 0x00e8)
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#define RKVPSS_CMSC_WIN4_L3_SLP (RKVPSS_CMSC_BASE + 0x00ec)
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#define RKVPSS_CMSC_WIN5_L0_VTX (RKVPSS_CMSC_BASE + 0x00f0)
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#define RKVPSS_CMSC_WIN5_L0_SLP (RKVPSS_CMSC_BASE + 0x00f4)
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#define RKVPSS_CMSC_WIN5_L1_VTX (RKVPSS_CMSC_BASE + 0x00f8)
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#define RKVPSS_CMSC_WIN5_L1_SLP (RKVPSS_CMSC_BASE + 0x00fc)
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#define RKVPSS_CMSC_WIN5_L2_VTX (RKVPSS_CMSC_BASE + 0x0100)
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#define RKVPSS_CMSC_WIN5_L2_SLP (RKVPSS_CMSC_BASE + 0x0104)
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#define RKVPSS_CMSC_WIN5_L3_VTX (RKVPSS_CMSC_BASE + 0x0108)
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#define RKVPSS_CMSC_WIN5_L3_SLP (RKVPSS_CMSC_BASE + 0x010c)
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#define RKVPSS_CMSC_WIN6_L0_VTX (RKVPSS_CMSC_BASE + 0x0110)
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#define RKVPSS_CMSC_WIN6_L0_SLP (RKVPSS_CMSC_BASE + 0x0114)
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#define RKVPSS_CMSC_WIN6_L1_VTX (RKVPSS_CMSC_BASE + 0x0118)
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#define RKVPSS_CMSC_WIN6_L1_SLP (RKVPSS_CMSC_BASE + 0x011c)
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#define RKVPSS_CMSC_WIN6_L2_VTX (RKVPSS_CMSC_BASE + 0x0120)
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#define RKVPSS_CMSC_WIN6_L2_SLP (RKVPSS_CMSC_BASE + 0x0124)
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#define RKVPSS_CMSC_WIN6_L3_VTX (RKVPSS_CMSC_BASE + 0x0128)
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#define RKVPSS_CMSC_WIN6_L3_SLP (RKVPSS_CMSC_BASE + 0x012c)
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#define RKVPSS_CMSC_WIN7_L0_VTX (RKVPSS_CMSC_BASE + 0x0130)
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#define RKVPSS_CMSC_WIN7_L0_SLP (RKVPSS_CMSC_BASE + 0x0134)
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#define RKVPSS_CMSC_WIN7_L1_VTX (RKVPSS_CMSC_BASE + 0x0138)
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#define RKVPSS_CMSC_WIN7_L1_SLP (RKVPSS_CMSC_BASE + 0x013c)
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#define RKVPSS_CMSC_WIN7_L2_VTX (RKVPSS_CMSC_BASE + 0x0140)
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#define RKVPSS_CMSC_WIN7_L2_SLP (RKVPSS_CMSC_BASE + 0x0144)
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#define RKVPSS_CMSC_WIN7_L3_VTX (RKVPSS_CMSC_BASE + 0x0148)
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#define RKVPSS_CMSC_WIN7_L3_SLP (RKVPSS_CMSC_BASE + 0x014c)
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#define RKVPSS_CROP0_BASE 0x0700
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#define RKVPSS_CROP0_CTRL (RKVPSS_CROP0_BASE + 0x0000)
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#define RKVPSS_CROP0_UPDATE (RKVPSS_CROP0_BASE + 0x0004)
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#define RKVPSS_CROP0_0_H_OFFS (RKVPSS_CROP0_BASE + 0x0010)
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#define RKVPSS_CROP0_0_V_OFFS (RKVPSS_CROP0_BASE + 0x0014)
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#define RKVPSS_CROP0_0_H_SIZE (RKVPSS_CROP0_BASE + 0x0018)
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#define RKVPSS_CROP0_0_V_SIZE (RKVPSS_CROP0_BASE + 0x001c)
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#define RKVPSS_CROP0_1_H_OFFS (RKVPSS_CROP0_BASE + 0x0020)
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#define RKVPSS_CROP0_1_V_OFFS (RKVPSS_CROP0_BASE + 0x0024)
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#define RKVPSS_CROP0_1_H_SIZE (RKVPSS_CROP0_BASE + 0x0028)
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#define RKVPSS_CROP0_1_V_SIZE (RKVPSS_CROP0_BASE + 0x002c)
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#define RKVPSS_CROP0_2_H_OFFS (RKVPSS_CROP0_BASE + 0x0030)
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#define RKVPSS_CROP0_2_V_OFFS (RKVPSS_CROP0_BASE + 0x0034)
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#define RKVPSS_CROP0_2_H_SIZE (RKVPSS_CROP0_BASE + 0x0038)
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#define RKVPSS_CROP0_2_V_SIZE (RKVPSS_CROP0_BASE + 0x003c)
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#define RKVPSS_CROP0_3_H_OFFS (RKVPSS_CROP0_BASE + 0x0040)
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#define RKVPSS_CROP0_3_V_OFFS (RKVPSS_CROP0_BASE + 0x0044)
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#define RKVPSS_CROP0_3_H_SIZE (RKVPSS_CROP0_BASE + 0x0048)
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#define RKVPSS_CROP0_3_V_SIZE (RKVPSS_CROP0_BASE + 0x004c)
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#define RKVPSS_CROP0_CTRL_SHD (RKVPSS_CROP0_BASE + 0x0060)
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#define RKVPSS_CROP0_0_H_OFFS_SHD (RKVPSS_CROP0_BASE + 0x0070)
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#define RKVPSS_CROP0_0_V_OFFS_SHD (RKVPSS_CROP0_BASE + 0x0074)
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#define RKVPSS_CROP0_0_H_SIZE_SHD (RKVPSS_CROP0_BASE + 0x0078)
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#define RKVPSS_CROP0_0_V_SIZE_SHD (RKVPSS_CROP0_BASE + 0x007c)
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#define RKVPSS_CROP0_1_H_OFFS_SHD (RKVPSS_CROP0_BASE + 0x0080)
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#define RKVPSS_CROP0_1_V_OFFS_SHD (RKVPSS_CROP0_BASE + 0x0084)
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#define RKVPSS_CROP0_1_H_SIZE_SHD (RKVPSS_CROP0_BASE + 0x0088)
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#define RKVPSS_CROP0_1_V_SIZE_SHD (RKVPSS_CROP0_BASE + 0x008c)
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#define RKVPSS_CROP0_2_H_OFFS_SHD (RKVPSS_CROP0_BASE + 0x0090)
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#define RKVPSS_CROP0_2_V_OFFS_SHD (RKVPSS_CROP0_BASE + 0x0094)
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#define RKVPSS_CROP0_2_H_SIZE_SHD (RKVPSS_CROP0_BASE + 0x0098)
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#define RKVPSS_CROP0_2_V_SIZE_SHD (RKVPSS_CROP0_BASE + 0x009c)
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#define RKVPSS_CROP0_3_H_OFFS_SHD (RKVPSS_CROP0_BASE + 0x00a0)
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#define RKVPSS_CROP0_3_V_OFFS_SHD (RKVPSS_CROP0_BASE + 0x00a4)
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#define RKVPSS_CROP0_3_H_SIZE_SHD (RKVPSS_CROP0_BASE + 0x00a8)
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#define RKVPSS_CROP0_3_V_SIZE_SHD (RKVPSS_CROP0_BASE + 0x00ac)
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#define RKVPSS_CROP1_BASE 0x0800
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#define RKVPSS_CROP1_CTRL (RKVPSS_CROP1_BASE + 0x0000)
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#define RKVPSS_CROP1_UPDATE (RKVPSS_CROP1_BASE + 0x0004)
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#define RKVPSS_CROP1_0_H_OFFS (RKVPSS_CROP1_BASE + 0x0010)
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#define RKVPSS_CROP1_0_V_OFFS (RKVPSS_CROP1_BASE + 0x0014)
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#define RKVPSS_CROP1_0_H_SIZE (RKVPSS_CROP1_BASE + 0x0018)
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#define RKVPSS_CROP1_0_V_SIZE (RKVPSS_CROP1_BASE + 0x001c)
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#define RKVPSS_CROP1_1_H_OFFS (RKVPSS_CROP1_BASE + 0x0020)
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#define RKVPSS_CROP1_1_V_OFFS (RKVPSS_CROP1_BASE + 0x0024)
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#define RKVPSS_CROP1_1_H_SIZE (RKVPSS_CROP1_BASE + 0x0028)
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#define RKVPSS_CROP1_1_V_SIZE (RKVPSS_CROP1_BASE + 0x002c)
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#define RKVPSS_CROP1_2_H_OFFS (RKVPSS_CROP1_BASE + 0x0030)
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#define RKVPSS_CROP1_2_V_OFFS (RKVPSS_CROP1_BASE + 0x0034)
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#define RKVPSS_CROP1_2_H_SIZE (RKVPSS_CROP1_BASE + 0x0038)
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#define RKVPSS_CROP1_2_V_SIZE (RKVPSS_CROP1_BASE + 0x003c)
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#define RKVPSS_CROP1_3_H_OFFS (RKVPSS_CROP1_BASE + 0x0040)
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#define RKVPSS_CROP1_3_V_OFFS (RKVPSS_CROP1_BASE + 0x0044)
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#define RKVPSS_CROP1_3_H_SIZE (RKVPSS_CROP1_BASE + 0x0048)
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#define RKVPSS_CROP1_3_V_SIZE (RKVPSS_CROP1_BASE + 0x004c)
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#define RKVPSS_CROP1_CTRL_SHD (RKVPSS_CROP1_BASE + 0x0060)
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#define RKVPSS_CROP1_0_H_OFFS_SHD (RKVPSS_CROP1_BASE + 0x0070)
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#define RKVPSS_CROP1_0_V_OFFS_SHD (RKVPSS_CROP1_BASE + 0x0074)
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#define RKVPSS_CROP1_0_H_SIZE_SHD (RKVPSS_CROP1_BASE + 0x0078)
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#define RKVPSS_CROP1_0_V_SIZE_SHD (RKVPSS_CROP1_BASE + 0x007c)
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#define RKVPSS_CROP1_1_H_OFFS_SHD (RKVPSS_CROP1_BASE + 0x0080)
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#define RKVPSS_CROP1_1_V_OFFS_SHD (RKVPSS_CROP1_BASE + 0x0084)
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#define RKVPSS_CROP1_1_H_SIZE_SHD (RKVPSS_CROP1_BASE + 0x0088)
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#define RKVPSS_CROP1_1_V_SIZE_SHD (RKVPSS_CROP1_BASE + 0x008c)
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#define RKVPSS_CROP1_2_H_OFFS_SHD (RKVPSS_CROP1_BASE + 0x0090)
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#define RKVPSS_CROP1_2_V_OFFS_SHD (RKVPSS_CROP1_BASE + 0x0094)
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#define RKVPSS_CROP1_2_H_SIZE_SHD (RKVPSS_CROP1_BASE + 0x0098)
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#define RKVPSS_CROP1_2_V_SIZE_SHD (RKVPSS_CROP1_BASE + 0x009c)
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#define RKVPSS_CROP1_3_H_OFFS_SHD (RKVPSS_CROP1_BASE + 0x00a0)
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#define RKVPSS_CROP1_3_V_OFFS_SHD (RKVPSS_CROP1_BASE + 0x00a4)
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#define RKVPSS_CROP1_3_H_SIZE_SHD (RKVPSS_CROP1_BASE + 0x00a8)
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#define RKVPSS_CROP1_3_V_SIZE_SHD (RKVPSS_CROP1_BASE + 0x00ac)
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#define RKVPSS_ZME_BASE 0x1000
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#define RKVPSS_ZME_Y_HOR_COE0_10 (RKVPSS_ZME_BASE + 0x0000)
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#define RKVPSS_ZME_Y_HOR_COE0_32 (RKVPSS_ZME_BASE + 0x0004)
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#define RKVPSS_ZME_Y_HOR_COE0_54 (RKVPSS_ZME_BASE + 0x0008)
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#define RKVPSS_ZME_Y_HOR_COE0_76 (RKVPSS_ZME_BASE + 0x000c)
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#define RKVPSS_ZME_Y_HOR_COE1_10 (RKVPSS_ZME_BASE + 0x0010)
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#define RKVPSS_ZME_Y_HOR_COE1_32 (RKVPSS_ZME_BASE + 0x0014)
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#define RKVPSS_ZME_Y_HOR_COE1_54 (RKVPSS_ZME_BASE + 0x0018)
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#define RKVPSS_ZME_Y_HOR_COE1_76 (RKVPSS_ZME_BASE + 0x001c)
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#define RKVPSS_ZME_Y_HOR_COE2_10 (RKVPSS_ZME_BASE + 0x0020)
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#define RKVPSS_ZME_Y_HOR_COE2_32 (RKVPSS_ZME_BASE + 0x0024)
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#define RKVPSS_ZME_Y_HOR_COE2_54 (RKVPSS_ZME_BASE + 0x0028)
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#define RKVPSS_ZME_Y_HOR_COE2_76 (RKVPSS_ZME_BASE + 0x002c)
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#define RKVPSS_ZME_Y_HOR_COE3_10 (RKVPSS_ZME_BASE + 0x0030)
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#define RKVPSS_ZME_Y_HOR_COE3_32 (RKVPSS_ZME_BASE + 0x0034)
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#define RKVPSS_ZME_Y_HOR_COE3_54 (RKVPSS_ZME_BASE + 0x0038)
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#define RKVPSS_ZME_Y_HOR_COE3_76 (RKVPSS_ZME_BASE + 0x003c)
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#define RKVPSS_ZME_Y_HOR_COE4_10 (RKVPSS_ZME_BASE + 0x0040)
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#define RKVPSS_ZME_Y_HOR_COE4_32 (RKVPSS_ZME_BASE + 0x0044)
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#define RKVPSS_ZME_Y_HOR_COE4_54 (RKVPSS_ZME_BASE + 0x0048)
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#define RKVPSS_ZME_Y_HOR_COE4_76 (RKVPSS_ZME_BASE + 0x004c)
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#define RKVPSS_ZME_Y_HOR_COE5_10 (RKVPSS_ZME_BASE + 0x0050)
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#define RKVPSS_ZME_Y_HOR_COE5_32 (RKVPSS_ZME_BASE + 0x0054)
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#define RKVPSS_ZME_Y_HOR_COE5_54 (RKVPSS_ZME_BASE + 0x0058)
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#define RKVPSS_ZME_Y_HOR_COE5_76 (RKVPSS_ZME_BASE + 0x005c)
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#define RKVPSS_ZME_Y_HOR_COE6_10 (RKVPSS_ZME_BASE + 0x0060)
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#define RKVPSS_ZME_Y_HOR_COE6_32 (RKVPSS_ZME_BASE + 0x0064)
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#define RKVPSS_ZME_Y_HOR_COE6_54 (RKVPSS_ZME_BASE + 0x0068)
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#define RKVPSS_ZME_Y_HOR_COE6_76 (RKVPSS_ZME_BASE + 0x006c)
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#define RKVPSS_ZME_Y_HOR_COE7_10 (RKVPSS_ZME_BASE + 0x0070)
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#define RKVPSS_ZME_Y_HOR_COE7_32 (RKVPSS_ZME_BASE + 0x0074)
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#define RKVPSS_ZME_Y_HOR_COE7_54 (RKVPSS_ZME_BASE + 0x0078)
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#define RKVPSS_ZME_Y_HOR_COE7_76 (RKVPSS_ZME_BASE + 0x007c)
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#define RKVPSS_ZME_Y_HOR_COE8_10 (RKVPSS_ZME_BASE + 0x0080)
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#define RKVPSS_ZME_Y_HOR_COE8_32 (RKVPSS_ZME_BASE + 0x0084)
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#define RKVPSS_ZME_Y_HOR_COE8_54 (RKVPSS_ZME_BASE + 0x0088)
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#define RKVPSS_ZME_Y_HOR_COE8_76 (RKVPSS_ZME_BASE + 0x008c)
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#define RKVPSS_ZME_Y_HOR_COE9_10 (RKVPSS_ZME_BASE + 0x0090)
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#define RKVPSS_ZME_Y_HOR_COE9_32 (RKVPSS_ZME_BASE + 0x0094)
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#define RKVPSS_ZME_Y_HOR_COE9_54 (RKVPSS_ZME_BASE + 0x0098)
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#define RKVPSS_ZME_Y_HOR_COE9_76 (RKVPSS_ZME_BASE + 0x009c)
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#define RKVPSS_ZME_Y_HOR_COE10_10 (RKVPSS_ZME_BASE + 0x00a0)
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#define RKVPSS_ZME_Y_HOR_COE10_32 (RKVPSS_ZME_BASE + 0x00a4)
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#define RKVPSS_ZME_Y_HOR_COE10_54 (RKVPSS_ZME_BASE + 0x00a8)
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#define RKVPSS_ZME_Y_HOR_COE10_76 (RKVPSS_ZME_BASE + 0x00ac)
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#define RKVPSS_ZME_Y_HOR_COE11_10 (RKVPSS_ZME_BASE + 0x00b0)
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#define RKVPSS_ZME_Y_HOR_COE11_32 (RKVPSS_ZME_BASE + 0x00b4)
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#define RKVPSS_ZME_Y_HOR_COE11_54 (RKVPSS_ZME_BASE + 0x00b8)
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#define RKVPSS_ZME_Y_HOR_COE11_76 (RKVPSS_ZME_BASE + 0x00bc)
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#define RKVPSS_ZME_Y_HOR_COE12_10 (RKVPSS_ZME_BASE + 0x00c0)
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#define RKVPSS_ZME_Y_HOR_COE12_32 (RKVPSS_ZME_BASE + 0x00c4)
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#define RKVPSS_ZME_Y_HOR_COE12_54 (RKVPSS_ZME_BASE + 0x00c8)
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#define RKVPSS_ZME_Y_HOR_COE12_76 (RKVPSS_ZME_BASE + 0x00cc)
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#define RKVPSS_ZME_Y_HOR_COE13_10 (RKVPSS_ZME_BASE + 0x00d0)
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#define RKVPSS_ZME_Y_HOR_COE13_32 (RKVPSS_ZME_BASE + 0x00d4)
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#define RKVPSS_ZME_Y_HOR_COE13_54 (RKVPSS_ZME_BASE + 0x00d8)
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#define RKVPSS_ZME_Y_HOR_COE13_76 (RKVPSS_ZME_BASE + 0x00dc)
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#define RKVPSS_ZME_Y_HOR_COE14_10 (RKVPSS_ZME_BASE + 0x00e0)
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#define RKVPSS_ZME_Y_HOR_COE14_32 (RKVPSS_ZME_BASE + 0x00e4)
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#define RKVPSS_ZME_Y_HOR_COE14_54 (RKVPSS_ZME_BASE + 0x00e8)
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#define RKVPSS_ZME_Y_HOR_COE14_76 (RKVPSS_ZME_BASE + 0x00ec)
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#define RKVPSS_ZME_Y_HOR_COE15_10 (RKVPSS_ZME_BASE + 0x00f0)
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#define RKVPSS_ZME_Y_HOR_COE15_32 (RKVPSS_ZME_BASE + 0x00f4)
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#define RKVPSS_ZME_Y_HOR_COE15_54 (RKVPSS_ZME_BASE + 0x00f8)
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#define RKVPSS_ZME_Y_HOR_COE15_76 (RKVPSS_ZME_BASE + 0x00fc)
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#define RKVPSS_ZME_Y_HOR_COE16_10 (RKVPSS_ZME_BASE + 0x0100)
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#define RKVPSS_ZME_Y_HOR_COE16_32 (RKVPSS_ZME_BASE + 0x0104)
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#define RKVPSS_ZME_Y_HOR_COE16_54 (RKVPSS_ZME_BASE + 0x0108)
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#define RKVPSS_ZME_Y_HOR_COE16_76 (RKVPSS_ZME_BASE + 0x010c)
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#define RKVPSS_ZME_Y_VER_COE0_10 (RKVPSS_ZME_BASE + 0x0200)
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#define RKVPSS_ZME_Y_VER_COE0_32 (RKVPSS_ZME_BASE + 0x0204)
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#define RKVPSS_ZME_Y_VER_COE0_54 (RKVPSS_ZME_BASE + 0x0208)
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#define RKVPSS_ZME_Y_VER_COE0_76 (RKVPSS_ZME_BASE + 0x020c)
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#define RKVPSS_ZME_Y_VER_COE1_10 (RKVPSS_ZME_BASE + 0x0210)
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#define RKVPSS_ZME_Y_VER_COE1_32 (RKVPSS_ZME_BASE + 0x0214)
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#define RKVPSS_ZME_Y_VER_COE1_54 (RKVPSS_ZME_BASE + 0x0218)
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#define RKVPSS_ZME_Y_VER_COE1_76 (RKVPSS_ZME_BASE + 0x021c)
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#define RKVPSS_ZME_Y_VER_COE2_10 (RKVPSS_ZME_BASE + 0x0220)
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#define RKVPSS_ZME_Y_VER_COE2_32 (RKVPSS_ZME_BASE + 0x0224)
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#define RKVPSS_ZME_Y_VER_COE2_54 (RKVPSS_ZME_BASE + 0x0228)
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#define RKVPSS_ZME_Y_VER_COE2_76 (RKVPSS_ZME_BASE + 0x022c)
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#define RKVPSS_ZME_Y_VER_COE3_10 (RKVPSS_ZME_BASE + 0x0230)
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#define RKVPSS_ZME_Y_VER_COE3_32 (RKVPSS_ZME_BASE + 0x0234)
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#define RKVPSS_ZME_Y_VER_COE3_54 (RKVPSS_ZME_BASE + 0x0238)
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#define RKVPSS_ZME_Y_VER_COE3_76 (RKVPSS_ZME_BASE + 0x023c)
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#define RKVPSS_ZME_Y_VER_COE4_10 (RKVPSS_ZME_BASE + 0x0240)
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#define RKVPSS_ZME_Y_VER_COE4_32 (RKVPSS_ZME_BASE + 0x0244)
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#define RKVPSS_ZME_Y_VER_COE4_54 (RKVPSS_ZME_BASE + 0x0248)
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#define RKVPSS_ZME_Y_VER_COE4_76 (RKVPSS_ZME_BASE + 0x024c)
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#define RKVPSS_ZME_Y_VER_COE5_10 (RKVPSS_ZME_BASE + 0x0250)
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#define RKVPSS_ZME_Y_VER_COE5_32 (RKVPSS_ZME_BASE + 0x0254)
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#define RKVPSS_ZME_Y_VER_COE5_54 (RKVPSS_ZME_BASE + 0x0258)
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#define RKVPSS_ZME_Y_VER_COE5_76 (RKVPSS_ZME_BASE + 0x025c)
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#define RKVPSS_ZME_Y_VER_COE6_10 (RKVPSS_ZME_BASE + 0x0260)
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#define RKVPSS_ZME_Y_VER_COE6_32 (RKVPSS_ZME_BASE + 0x0264)
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#define RKVPSS_ZME_Y_VER_COE6_54 (RKVPSS_ZME_BASE + 0x0268)
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#define RKVPSS_ZME_Y_VER_COE6_76 (RKVPSS_ZME_BASE + 0x026c)
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#define RKVPSS_ZME_Y_VER_COE7_10 (RKVPSS_ZME_BASE + 0x0270)
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#define RKVPSS_ZME_Y_VER_COE7_32 (RKVPSS_ZME_BASE + 0x0274)
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#define RKVPSS_ZME_Y_VER_COE7_54 (RKVPSS_ZME_BASE + 0x0278)
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#define RKVPSS_ZME_Y_VER_COE7_76 (RKVPSS_ZME_BASE + 0x027c)
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#define RKVPSS_ZME_Y_VER_COE8_10 (RKVPSS_ZME_BASE + 0x0280)
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#define RKVPSS_ZME_Y_VER_COE8_32 (RKVPSS_ZME_BASE + 0x0284)
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#define RKVPSS_ZME_Y_VER_COE8_54 (RKVPSS_ZME_BASE + 0x0288)
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#define RKVPSS_ZME_Y_VER_COE8_76 (RKVPSS_ZME_BASE + 0x028c)
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#define RKVPSS_ZME_Y_VER_COE9_10 (RKVPSS_ZME_BASE + 0x0290)
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#define RKVPSS_ZME_Y_VER_COE9_32 (RKVPSS_ZME_BASE + 0x0294)
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#define RKVPSS_ZME_Y_VER_COE9_54 (RKVPSS_ZME_BASE + 0x0298)
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#define RKVPSS_ZME_Y_VER_COE9_76 (RKVPSS_ZME_BASE + 0x029c)
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#define RKVPSS_ZME_Y_VER_COE10_10 (RKVPSS_ZME_BASE + 0x02a0)
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#define RKVPSS_ZME_Y_VER_COE10_32 (RKVPSS_ZME_BASE + 0x02a4)
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#define RKVPSS_ZME_Y_VER_COE10_54 (RKVPSS_ZME_BASE + 0x02a8)
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#define RKVPSS_ZME_Y_VER_COE10_76 (RKVPSS_ZME_BASE + 0x02ac)
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#define RKVPSS_ZME_Y_VER_COE11_10 (RKVPSS_ZME_BASE + 0x02b0)
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#define RKVPSS_ZME_Y_VER_COE11_32 (RKVPSS_ZME_BASE + 0x02b4)
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#define RKVPSS_ZME_Y_VER_COE11_54 (RKVPSS_ZME_BASE + 0x02b8)
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#define RKVPSS_ZME_Y_VER_COE11_76 (RKVPSS_ZME_BASE + 0x02bc)
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#define RKVPSS_ZME_Y_VER_COE12_10 (RKVPSS_ZME_BASE + 0x02c0)
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#define RKVPSS_ZME_Y_VER_COE12_32 (RKVPSS_ZME_BASE + 0x02c4)
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#define RKVPSS_ZME_Y_VER_COE12_54 (RKVPSS_ZME_BASE + 0x02c8)
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#define RKVPSS_ZME_Y_VER_COE12_76 (RKVPSS_ZME_BASE + 0x02cc)
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#define RKVPSS_ZME_Y_VER_COE13_10 (RKVPSS_ZME_BASE + 0x02d0)
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#define RKVPSS_ZME_Y_VER_COE13_32 (RKVPSS_ZME_BASE + 0x02d4)
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#define RKVPSS_ZME_Y_VER_COE13_54 (RKVPSS_ZME_BASE + 0x02d8)
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#define RKVPSS_ZME_Y_VER_COE13_76 (RKVPSS_ZME_BASE + 0x02dc)
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#define RKVPSS_ZME_Y_VER_COE14_10 (RKVPSS_ZME_BASE + 0x02e0)
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#define RKVPSS_ZME_Y_VER_COE14_32 (RKVPSS_ZME_BASE + 0x02e4)
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#define RKVPSS_ZME_Y_VER_COE14_54 (RKVPSS_ZME_BASE + 0x02e8)
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#define RKVPSS_ZME_Y_VER_COE14_76 (RKVPSS_ZME_BASE + 0x02ec)
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#define RKVPSS_ZME_Y_VER_COE15_10 (RKVPSS_ZME_BASE + 0x02f0)
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#define RKVPSS_ZME_Y_VER_COE15_32 (RKVPSS_ZME_BASE + 0x02f4)
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#define RKVPSS_ZME_Y_VER_COE15_54 (RKVPSS_ZME_BASE + 0x02f8)
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#define RKVPSS_ZME_Y_VER_COE15_76 (RKVPSS_ZME_BASE + 0x02fc)
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#define RKVPSS_ZME_Y_VER_COE16_10 (RKVPSS_ZME_BASE + 0x0300)
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#define RKVPSS_ZME_Y_VER_COE16_32 (RKVPSS_ZME_BASE + 0x0304)
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#define RKVPSS_ZME_Y_VER_COE16_54 (RKVPSS_ZME_BASE + 0x0308)
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#define RKVPSS_ZME_Y_VER_COE16_76 (RKVPSS_ZME_BASE + 0x030c)
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#define RKVPSS_ZME_UV_HOR_COE0_10 (RKVPSS_ZME_BASE + 0x0400)
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#define RKVPSS_ZME_UV_HOR_COE0_32 (RKVPSS_ZME_BASE + 0x0404)
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#define RKVPSS_ZME_UV_HOR_COE0_54 (RKVPSS_ZME_BASE + 0x0408)
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#define RKVPSS_ZME_UV_HOR_COE0_76 (RKVPSS_ZME_BASE + 0x040c)
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#define RKVPSS_ZME_UV_HOR_COE1_10 (RKVPSS_ZME_BASE + 0x0410)
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#define RKVPSS_ZME_UV_HOR_COE1_32 (RKVPSS_ZME_BASE + 0x0414)
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#define RKVPSS_ZME_UV_HOR_COE1_54 (RKVPSS_ZME_BASE + 0x0418)
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#define RKVPSS_ZME_UV_HOR_COE1_76 (RKVPSS_ZME_BASE + 0x041c)
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#define RKVPSS_ZME_UV_HOR_COE2_10 (RKVPSS_ZME_BASE + 0x0420)
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#define RKVPSS_ZME_UV_HOR_COE2_32 (RKVPSS_ZME_BASE + 0x0424)
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#define RKVPSS_ZME_UV_HOR_COE2_54 (RKVPSS_ZME_BASE + 0x0428)
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#define RKVPSS_ZME_UV_HOR_COE2_76 (RKVPSS_ZME_BASE + 0x042c)
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#define RKVPSS_ZME_UV_HOR_COE3_10 (RKVPSS_ZME_BASE + 0x0430)
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#define RKVPSS_ZME_UV_HOR_COE3_32 (RKVPSS_ZME_BASE + 0x0434)
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#define RKVPSS_ZME_UV_HOR_COE3_54 (RKVPSS_ZME_BASE + 0x0438)
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#define RKVPSS_ZME_UV_HOR_COE3_76 (RKVPSS_ZME_BASE + 0x043c)
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#define RKVPSS_ZME_UV_HOR_COE4_10 (RKVPSS_ZME_BASE + 0x0440)
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#define RKVPSS_ZME_UV_HOR_COE4_32 (RKVPSS_ZME_BASE + 0x0444)
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#define RKVPSS_ZME_UV_HOR_COE4_54 (RKVPSS_ZME_BASE + 0x0448)
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#define RKVPSS_ZME_UV_HOR_COE4_76 (RKVPSS_ZME_BASE + 0x044c)
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#define RKVPSS_ZME_UV_HOR_COE5_10 (RKVPSS_ZME_BASE + 0x0450)
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#define RKVPSS_ZME_UV_HOR_COE5_32 (RKVPSS_ZME_BASE + 0x0454)
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#define RKVPSS_ZME_UV_HOR_COE5_54 (RKVPSS_ZME_BASE + 0x0458)
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#define RKVPSS_ZME_UV_HOR_COE5_76 (RKVPSS_ZME_BASE + 0x045c)
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#define RKVPSS_ZME_UV_HOR_COE6_10 (RKVPSS_ZME_BASE + 0x0460)
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#define RKVPSS_ZME_UV_HOR_COE6_32 (RKVPSS_ZME_BASE + 0x0464)
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#define RKVPSS_ZME_UV_HOR_COE6_54 (RKVPSS_ZME_BASE + 0x0468)
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#define RKVPSS_ZME_UV_HOR_COE6_76 (RKVPSS_ZME_BASE + 0x046c)
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#define RKVPSS_ZME_UV_HOR_COE7_10 (RKVPSS_ZME_BASE + 0x0470)
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#define RKVPSS_ZME_UV_HOR_COE7_32 (RKVPSS_ZME_BASE + 0x0474)
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#define RKVPSS_ZME_UV_HOR_COE7_54 (RKVPSS_ZME_BASE + 0x0478)
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#define RKVPSS_ZME_UV_HOR_COE7_76 (RKVPSS_ZME_BASE + 0x047c)
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#define RKVPSS_ZME_UV_HOR_COE8_10 (RKVPSS_ZME_BASE + 0x0480)
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#define RKVPSS_ZME_UV_HOR_COE8_32 (RKVPSS_ZME_BASE + 0x0484)
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#define RKVPSS_ZME_UV_HOR_COE8_54 (RKVPSS_ZME_BASE + 0x0488)
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#define RKVPSS_ZME_UV_HOR_COE8_76 (RKVPSS_ZME_BASE + 0x048c)
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#define RKVPSS_ZME_UV_HOR_COE9_10 (RKVPSS_ZME_BASE + 0x0490)
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#define RKVPSS_ZME_UV_HOR_COE9_32 (RKVPSS_ZME_BASE + 0x0494)
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#define RKVPSS_ZME_UV_HOR_COE9_54 (RKVPSS_ZME_BASE + 0x0498)
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#define RKVPSS_ZME_UV_HOR_COE9_76 (RKVPSS_ZME_BASE + 0x049c)
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#define RKVPSS_ZME_UV_HOR_COE10_10 (RKVPSS_ZME_BASE + 0x04a0)
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#define RKVPSS_ZME_UV_HOR_COE10_32 (RKVPSS_ZME_BASE + 0x04a4)
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#define RKVPSS_ZME_UV_HOR_COE10_54 (RKVPSS_ZME_BASE + 0x04a8)
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#define RKVPSS_ZME_UV_HOR_COE10_76 (RKVPSS_ZME_BASE + 0x04ac)
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#define RKVPSS_ZME_UV_HOR_COE11_10 (RKVPSS_ZME_BASE + 0x04b0)
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#define RKVPSS_ZME_UV_HOR_COE11_32 (RKVPSS_ZME_BASE + 0x04b4)
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#define RKVPSS_ZME_UV_HOR_COE11_54 (RKVPSS_ZME_BASE + 0x04b8)
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#define RKVPSS_ZME_UV_HOR_COE11_76 (RKVPSS_ZME_BASE + 0x04bc)
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#define RKVPSS_ZME_UV_HOR_COE12_10 (RKVPSS_ZME_BASE + 0x04c0)
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#define RKVPSS_ZME_UV_HOR_COE12_32 (RKVPSS_ZME_BASE + 0x04c4)
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#define RKVPSS_ZME_UV_HOR_COE12_54 (RKVPSS_ZME_BASE + 0x04c8)
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#define RKVPSS_ZME_UV_HOR_COE12_76 (RKVPSS_ZME_BASE + 0x04cc)
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#define RKVPSS_ZME_UV_HOR_COE13_10 (RKVPSS_ZME_BASE + 0x04d0)
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#define RKVPSS_ZME_UV_HOR_COE13_32 (RKVPSS_ZME_BASE + 0x04d4)
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#define RKVPSS_ZME_UV_HOR_COE13_54 (RKVPSS_ZME_BASE + 0x04d8)
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#define RKVPSS_ZME_UV_HOR_COE13_76 (RKVPSS_ZME_BASE + 0x04dc)
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#define RKVPSS_ZME_UV_HOR_COE14_10 (RKVPSS_ZME_BASE + 0x04e0)
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#define RKVPSS_ZME_UV_HOR_COE14_32 (RKVPSS_ZME_BASE + 0x04e4)
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#define RKVPSS_ZME_UV_HOR_COE14_54 (RKVPSS_ZME_BASE + 0x04e8)
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#define RKVPSS_ZME_UV_HOR_COE14_76 (RKVPSS_ZME_BASE + 0x04ec)
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#define RKVPSS_ZME_UV_HOR_COE15_10 (RKVPSS_ZME_BASE + 0x04f0)
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#define RKVPSS_ZME_UV_HOR_COE15_32 (RKVPSS_ZME_BASE + 0x04f4)
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#define RKVPSS_ZME_UV_HOR_COE15_54 (RKVPSS_ZME_BASE + 0x04f8)
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#define RKVPSS_ZME_UV_HOR_COE15_76 (RKVPSS_ZME_BASE + 0x04fc)
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#define RKVPSS_ZME_UV_HOR_COE16_10 (RKVPSS_ZME_BASE + 0x0500)
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#define RKVPSS_ZME_UV_HOR_COE16_32 (RKVPSS_ZME_BASE + 0x0504)
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#define RKVPSS_ZME_UV_HOR_COE16_54 (RKVPSS_ZME_BASE + 0x0508)
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#define RKVPSS_ZME_UV_HOR_COE16_76 (RKVPSS_ZME_BASE + 0x050c)
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#define RKVPSS_ZME_UV_VER_COE0_10 (RKVPSS_ZME_BASE + 0x0600)
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#define RKVPSS_ZME_UV_VER_COE0_32 (RKVPSS_ZME_BASE + 0x0604)
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#define RKVPSS_ZME_UV_VER_COE0_54 (RKVPSS_ZME_BASE + 0x0608)
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#define RKVPSS_ZME_UV_VER_COE0_76 (RKVPSS_ZME_BASE + 0x060c)
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#define RKVPSS_ZME_UV_VER_COE1_10 (RKVPSS_ZME_BASE + 0x0610)
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#define RKVPSS_ZME_UV_VER_COE1_32 (RKVPSS_ZME_BASE + 0x0614)
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#define RKVPSS_ZME_UV_VER_COE1_54 (RKVPSS_ZME_BASE + 0x0618)
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#define RKVPSS_ZME_UV_VER_COE1_76 (RKVPSS_ZME_BASE + 0x061c)
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#define RKVPSS_ZME_UV_VER_COE2_10 (RKVPSS_ZME_BASE + 0x0620)
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#define RKVPSS_ZME_UV_VER_COE2_32 (RKVPSS_ZME_BASE + 0x0624)
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#define RKVPSS_ZME_UV_VER_COE2_54 (RKVPSS_ZME_BASE + 0x0628)
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#define RKVPSS_ZME_UV_VER_COE2_76 (RKVPSS_ZME_BASE + 0x062c)
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#define RKVPSS_ZME_UV_VER_COE3_10 (RKVPSS_ZME_BASE + 0x0630)
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#define RKVPSS_ZME_UV_VER_COE3_32 (RKVPSS_ZME_BASE + 0x0634)
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#define RKVPSS_ZME_UV_VER_COE3_54 (RKVPSS_ZME_BASE + 0x0638)
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#define RKVPSS_ZME_UV_VER_COE3_76 (RKVPSS_ZME_BASE + 0x063c)
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#define RKVPSS_ZME_UV_VER_COE4_10 (RKVPSS_ZME_BASE + 0x0640)
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#define RKVPSS_ZME_UV_VER_COE4_32 (RKVPSS_ZME_BASE + 0x0644)
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#define RKVPSS_ZME_UV_VER_COE4_54 (RKVPSS_ZME_BASE + 0x0648)
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#define RKVPSS_ZME_UV_VER_COE4_76 (RKVPSS_ZME_BASE + 0x064c)
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#define RKVPSS_ZME_UV_VER_COE5_10 (RKVPSS_ZME_BASE + 0x0650)
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#define RKVPSS_ZME_UV_VER_COE5_32 (RKVPSS_ZME_BASE + 0x0654)
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#define RKVPSS_ZME_UV_VER_COE5_54 (RKVPSS_ZME_BASE + 0x0658)
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#define RKVPSS_ZME_UV_VER_COE5_76 (RKVPSS_ZME_BASE + 0x065c)
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#define RKVPSS_ZME_UV_VER_COE6_10 (RKVPSS_ZME_BASE + 0x0660)
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#define RKVPSS_ZME_UV_VER_COE6_32 (RKVPSS_ZME_BASE + 0x0664)
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#define RKVPSS_ZME_UV_VER_COE6_54 (RKVPSS_ZME_BASE + 0x0668)
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#define RKVPSS_ZME_UV_VER_COE6_76 (RKVPSS_ZME_BASE + 0x066c)
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#define RKVPSS_ZME_UV_VER_COE7_10 (RKVPSS_ZME_BASE + 0x0670)
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#define RKVPSS_ZME_UV_VER_COE7_32 (RKVPSS_ZME_BASE + 0x0674)
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#define RKVPSS_ZME_UV_VER_COE7_54 (RKVPSS_ZME_BASE + 0x0678)
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#define RKVPSS_ZME_UV_VER_COE7_76 (RKVPSS_ZME_BASE + 0x067c)
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#define RKVPSS_ZME_UV_VER_COE8_10 (RKVPSS_ZME_BASE + 0x0680)
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#define RKVPSS_ZME_UV_VER_COE8_32 (RKVPSS_ZME_BASE + 0x0684)
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#define RKVPSS_ZME_UV_VER_COE8_54 (RKVPSS_ZME_BASE + 0x0688)
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#define RKVPSS_ZME_UV_VER_COE8_76 (RKVPSS_ZME_BASE + 0x068c)
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#define RKVPSS_ZME_UV_VER_COE9_10 (RKVPSS_ZME_BASE + 0x0690)
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#define RKVPSS_ZME_UV_VER_COE9_32 (RKVPSS_ZME_BASE + 0x0694)
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#define RKVPSS_ZME_UV_VER_COE9_54 (RKVPSS_ZME_BASE + 0x0698)
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#define RKVPSS_ZME_UV_VER_COE9_76 (RKVPSS_ZME_BASE + 0x069c)
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#define RKVPSS_ZME_UV_VER_COE10_10 (RKVPSS_ZME_BASE + 0x06a0)
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#define RKVPSS_ZME_UV_VER_COE10_32 (RKVPSS_ZME_BASE + 0x06a4)
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#define RKVPSS_ZME_UV_VER_COE10_54 (RKVPSS_ZME_BASE + 0x06a8)
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#define RKVPSS_ZME_UV_VER_COE10_76 (RKVPSS_ZME_BASE + 0x06ac)
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#define RKVPSS_ZME_UV_VER_COE11_10 (RKVPSS_ZME_BASE + 0x06b0)
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#define RKVPSS_ZME_UV_VER_COE11_32 (RKVPSS_ZME_BASE + 0x06b4)
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#define RKVPSS_ZME_UV_VER_COE11_54 (RKVPSS_ZME_BASE + 0x06b8)
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#define RKVPSS_ZME_UV_VER_COE11_76 (RKVPSS_ZME_BASE + 0x06bc)
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#define RKVPSS_ZME_UV_VER_COE12_10 (RKVPSS_ZME_BASE + 0x06c0)
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#define RKVPSS_ZME_UV_VER_COE12_32 (RKVPSS_ZME_BASE + 0x06c4)
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#define RKVPSS_ZME_UV_VER_COE12_54 (RKVPSS_ZME_BASE + 0x06c8)
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#define RKVPSS_ZME_UV_VER_COE12_76 (RKVPSS_ZME_BASE + 0x06cc)
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#define RKVPSS_ZME_UV_VER_COE13_10 (RKVPSS_ZME_BASE + 0x06d0)
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#define RKVPSS_ZME_UV_VER_COE13_32 (RKVPSS_ZME_BASE + 0x06d4)
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#define RKVPSS_ZME_UV_VER_COE13_54 (RKVPSS_ZME_BASE + 0x06d8)
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#define RKVPSS_ZME_UV_VER_COE13_76 (RKVPSS_ZME_BASE + 0x06dc)
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#define RKVPSS_ZME_UV_VER_COE14_10 (RKVPSS_ZME_BASE + 0x06e0)
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#define RKVPSS_ZME_UV_VER_COE14_32 (RKVPSS_ZME_BASE + 0x06e4)
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#define RKVPSS_ZME_UV_VER_COE14_54 (RKVPSS_ZME_BASE + 0x06e8)
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#define RKVPSS_ZME_UV_VER_COE14_76 (RKVPSS_ZME_BASE + 0x06ec)
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#define RKVPSS_ZME_UV_VER_COE15_10 (RKVPSS_ZME_BASE + 0x06f0)
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#define RKVPSS_ZME_UV_VER_COE15_32 (RKVPSS_ZME_BASE + 0x06f4)
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#define RKVPSS_ZME_UV_VER_COE15_54 (RKVPSS_ZME_BASE + 0x06f8)
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#define RKVPSS_ZME_UV_VER_COE15_76 (RKVPSS_ZME_BASE + 0x06fc)
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#define RKVPSS_ZME_UV_VER_COE16_10 (RKVPSS_ZME_BASE + 0x0700)
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#define RKVPSS_ZME_UV_VER_COE16_32 (RKVPSS_ZME_BASE + 0x0704)
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#define RKVPSS_ZME_UV_VER_COE16_54 (RKVPSS_ZME_BASE + 0x0708)
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#define RKVPSS_ZME_UV_VER_COE16_76 (RKVPSS_ZME_BASE + 0x070c)
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#define RKVPSS_ZME_CTRL (RKVPSS_ZME_BASE + 0x0800)
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#define RKVPSS_ZME_UPDATE (RKVPSS_ZME_BASE + 0x0804)
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#define RKVPSS_ZME_H_SIZE (RKVPSS_ZME_BASE + 0x0808)
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#define RKVPSS_ZME_H_OFFS (RKVPSS_ZME_BASE + 0x080c)
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#define RKVPSS_ZME_Y_SCL_CTRL (RKVPSS_ZME_BASE + 0x0810)
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#define RKVPSS_ZME_Y_SRC_SIZE (RKVPSS_ZME_BASE + 0x0814)
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#define RKVPSS_ZME_Y_DST_SIZE (RKVPSS_ZME_BASE + 0x0818)
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#define RKVPSS_ZME_Y_DERING_PARA (RKVPSS_ZME_BASE + 0x081c)
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#define RKVPSS_ZME_Y_XSCL_FACTOR (RKVPSS_ZME_BASE + 0x0820)
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#define RKVPSS_ZME_Y_YSCL_FACTOR (RKVPSS_ZME_BASE + 0x0824)
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#define RKVPSS_ZME_UV_SCL_CTRL (RKVPSS_ZME_BASE + 0x0830)
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#define RKVPSS_ZME_UV_SRC_SIZE (RKVPSS_ZME_BASE + 0x0834)
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#define RKVPSS_ZME_UV_DST_SIZE (RKVPSS_ZME_BASE + 0x0838)
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#define RKVPSS_ZME_UV_DERING_PARA (RKVPSS_ZME_BASE + 0x083c)
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#define RKVPSS_ZME_UV_XSCL_FACTOR (RKVPSS_ZME_BASE + 0x0840)
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#define RKVPSS_ZME_UV_YSCL_FACTOR (RKVPSS_ZME_BASE + 0x0844)
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#define RKVPSS_ZME_SCL_CTRL_SHD (RKVPSS_ZME_BASE + 0x084c)
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#define RKVPSS_ZME_Y_SRC_SIZE_SHD (RKVPSS_ZME_BASE + 0x0850)
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#define RKVPSS_ZME_Y_DST_SIZE_SHD (RKVPSS_ZME_BASE + 0x0854)
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#define RKVPSS_ZME_Y_XSCL_FACTOR_SHD (RKVPSS_ZME_BASE + 0x0858)
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#define RKVPSS_ZME_Y_YSCL_FACTOR_SHD (RKVPSS_ZME_BASE + 0x085c)
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#define RKVPSS_ZME_UV_SRC_SIZE_SHD (RKVPSS_ZME_BASE + 0x0860)
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#define RKVPSS_ZME_UV_DST_SIZE_SHD (RKVPSS_ZME_BASE + 0x0864)
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#define RKVPSS_ZME_UV_XSCL_FACTOR_SHD (RKVPSS_ZME_BASE + 0x0868)
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#define RKVPSS_ZME_UV_YSCL_FACTOR_SHD (RKVPSS_ZME_BASE + 0x086c)
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#define RKVPSS_ZME_H_SIZE_SHD (RKVPSS_ZME_BASE + 0x0870)
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#define RKVPSS_ZME_H_OFFS_SHD (RKVPSS_ZME_BASE + 0x0874)
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#define RKVPSS_RATIO0_BASE 0x1900
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#define RKVPSS_RATIO0_CTRL (RKVPSS_RATIO0_BASE + 0x0000)
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#define RKVPSS_RATIO0_UPDATE (RKVPSS_RATIO0_BASE + 0x0004)
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#define RKVPSS_RATIO0_ACT_SIZE (RKVPSS_RATIO0_BASE + 0x0010)
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#define RKVPSS_RATIO0_VIR_SIZE (RKVPSS_RATIO0_BASE + 0x0014)
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#define RKVPSS_RATIO0_OFFS (RKVPSS_RATIO0_BASE + 0x0018)
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#define RKVPSS_RATIO0_COLOR (RKVPSS_RATIO0_BASE + 0x001c)
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#define RKVPSS_RATIO0_ACT_SIZE_SHD (RKVPSS_RATIO0_BASE + 0x0030)
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#define RKVPSS_RATIO0_VIR_SIZE_SHD (RKVPSS_RATIO0_BASE + 0x0034)
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#define RKVPSS_RATIO0_OFFS_SHD (RKVPSS_RATIO0_BASE + 0x0038)
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#define RKVPSS_RATIO0_COLOR_SHD (RKVPSS_RATIO0_BASE + 0x003c)
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#define RKVPSS_RATIO1_BASE 0x2500
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#define RKVPSS_RATIO1_CTRL (RKVPSS_RATIO1_BASE + 0x0000)
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#define RKVPSS_RATIO1_UPDATE (RKVPSS_RATIO1_BASE + 0x0004)
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#define RKVPSS_RATIO1_ACT_SIZE (RKVPSS_RATIO1_BASE + 0x0010)
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#define RKVPSS_RATIO1_VIR_SIZE (RKVPSS_RATIO1_BASE + 0x0014)
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#define RKVPSS_RATIO1_OFFS (RKVPSS_RATIO1_BASE + 0x0018)
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#define RKVPSS_RATIO1_COLOR (RKVPSS_RATIO1_BASE + 0x001c)
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#define RKVPSS_RATIO1_ACT_SIZE_SHD (RKVPSS_RATIO1_BASE + 0x0030)
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#define RKVPSS_RATIO1_VIR_SIZE_SHD (RKVPSS_RATIO1_BASE + 0x0034)
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#define RKVPSS_RATIO1_OFFS_SHD (RKVPSS_RATIO1_BASE + 0x0038)
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#define RKVPSS_RATIO1_COLOR_SHD (RKVPSS_RATIO1_BASE + 0x003c)
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#define RKVPSS_RATIO2_BASE 0x2900
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#define RKVPSS_RATIO2_CTRL (RKVPSS_RATIO2_BASE + 0x0000)
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#define RKVPSS_RATIO2_UPDATE (RKVPSS_RATIO2_BASE + 0x0004)
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#define RKVPSS_RATIO2_ACT_SIZE (RKVPSS_RATIO2_BASE + 0x0010)
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#define RKVPSS_RATIO2_VIR_SIZE (RKVPSS_RATIO2_BASE + 0x0014)
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#define RKVPSS_RATIO2_OFFS (RKVPSS_RATIO2_BASE + 0x0018)
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#define RKVPSS_RATIO2_COLOR (RKVPSS_RATIO2_BASE + 0x001c)
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#define RKVPSS_RATIO2_ACT_SIZE_SHD (RKVPSS_RATIO2_BASE + 0x0030)
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#define RKVPSS_RATIO2_VIR_SIZE_SHD (RKVPSS_RATIO2_BASE + 0x0034)
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#define RKVPSS_RATIO2_OFFS_SHD (RKVPSS_RATIO2_BASE + 0x0038)
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#define RKVPSS_RATIO2_COLOR_SHD (RKVPSS_RATIO2_BASE + 0x003c)
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#define RKVPSS_RATIO3_BASE 0x2d00
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#define RKVPSS_RATIO3_CTRL (RKVPSS_RATIO3_BASE + 0x0000)
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#define RKVPSS_RATIO3_UPDATE (RKVPSS_RATIO3_BASE + 0x0004)
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#define RKVPSS_RATIO3_ACT_SIZE (RKVPSS_RATIO3_BASE + 0x0010)
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#define RKVPSS_RATIO3_VIR_SIZE (RKVPSS_RATIO3_BASE + 0x0014)
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#define RKVPSS_RATIO3_OFFS (RKVPSS_RATIO3_BASE + 0x0018)
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#define RKVPSS_RATIO3_COLOR (RKVPSS_RATIO3_BASE + 0x001c)
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#define RKVPSS_RATIO3_ACT_SIZE_SHD (RKVPSS_RATIO3_BASE + 0x0030)
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#define RKVPSS_RATIO3_VIR_SIZE_SHD (RKVPSS_RATIO3_BASE + 0x0034)
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#define RKVPSS_RATIO3_OFFS_SHD (RKVPSS_RATIO3_BASE + 0x0038)
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#define RKVPSS_RATIO3_COLOR_SHD (RKVPSS_RATIO3_BASE + 0x003c)
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#define RKVPSS_SCALE1_BASE 0x1c00
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#define RKVPSS_SCALE1_CTRL (RKVPSS_SCALE1_BASE + 0x0000)
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#define RKVPSS_SCALE1_UPDATE (RKVPSS_SCALE1_BASE + 0x0004)
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#define RKVPSS_SCALE1_SRC_SIZE (RKVPSS_SCALE1_BASE + 0x0008)
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#define RKVPSS_SCALE1_DST_SIZE (RKVPSS_SCALE1_BASE + 0x000c)
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#define RKVPSS_SCALE1_HY_FAC (RKVPSS_SCALE1_BASE + 0x0010)
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#define RKVPSS_SCALE1_HC_FAC (RKVPSS_SCALE1_BASE + 0x0014)
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#define RKVPSS_SCALE1_VY_FAC (RKVPSS_SCALE1_BASE + 0x0018)
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#define RKVPSS_SCALE1_VC_FAC (RKVPSS_SCALE1_BASE + 0x001c)
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#define RKVPSS_SCALE1_HY_OFFS (RKVPSS_SCALE1_BASE + 0x0020)
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#define RKVPSS_SCALE1_HC_OFFS (RKVPSS_SCALE1_BASE + 0x0024)
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#define RKVPSS_SCALE1_VY_OFFS (RKVPSS_SCALE1_BASE + 0x0028)
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#define RKVPSS_SCALE1_VC_OFFS (RKVPSS_SCALE1_BASE + 0x002c)
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#define RKVPSS_SCALE1_HY_SIZE (RKVPSS_SCALE1_BASE + 0x0040)
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#define RKVPSS_SCALE1_HC_SIZE (RKVPSS_SCALE1_BASE + 0x0044)
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#define RKVPSS_SCALE1_HY_OFFS_MI (RKVPSS_SCALE1_BASE + 0x0048)
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#define RKVPSS_SCALE1_HC_OFFS_MI (RKVPSS_SCALE1_BASE + 0x004c)
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#define RKVPSS_SCALE1_IN_CROP_OFFSET (RKVPSS_SCALE1_BASE + 0x0050)
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#define RKVPSS_SCALE1_CTRL_SHD (RKVPSS_SCALE1_BASE + 0x0080)
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#define RKVPSS_SCALE1_SRC_SIZE_SHD (RKVPSS_SCALE1_BASE + 0x0088)
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#define RKVPSS_SCALE1_DST_SIZE_SHD (RKVPSS_SCALE1_BASE + 0x008c)
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#define RKVPSS_SCALE1_HY_FAC_SHD (RKVPSS_SCALE1_BASE + 0x0090)
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#define RKVPSS_SCALE1_HC_FAC_SHD (RKVPSS_SCALE1_BASE + 0x0094)
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#define RKVPSS_SCALE1_VY_FAC_SHD (RKVPSS_SCALE1_BASE + 0x0098)
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#define RKVPSS_SCALE1_VC_FAC_SHD (RKVPSS_SCALE1_BASE + 0x009c)
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#define RKVPSS_SCALE1_HY_OFFS_SHD (RKVPSS_SCALE1_BASE + 0x00a0)
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#define RKVPSS_SCALE1_HC_OFFS_SHD (RKVPSS_SCALE1_BASE + 0x00a4)
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#define RKVPSS_SCALE1_VY_OFFS_SHD (RKVPSS_SCALE1_BASE + 0x00a8)
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#define RKVPSS_SCALE1_VC_OFFS_SHD (RKVPSS_SCALE1_BASE + 0x00ac)
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#define RKVPSS_SCALE1_HY_SIZE_SHD (RKVPSS_SCALE1_BASE + 0x00c0)
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#define RKVPSS_SCALE1_HC_SIZE_SHD (RKVPSS_SCALE1_BASE + 0x00c4)
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#define RKVPSS_SCALE1_HY_OFFS_MI_SHD (RKVPSS_SCALE1_BASE + 0x00c8)
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#define RKVPSS_SCALE1_HC_OFFS_MI_SHD (RKVPSS_SCALE1_BASE + 0x00cc)
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#define RKVPSS_SCALE1_IN_CROP_OFFSET_SHD (RKVPSS_SCALE1_BASE + 0x00d0)
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#define RKVPSS_SCALE2_BASE 0x2800
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#define RKVPSS_SCALE2_CTRL (RKVPSS_SCALE2_BASE + 0x0000)
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#define RKVPSS_SCALE2_UPDATE (RKVPSS_SCALE2_BASE + 0x0004)
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#define RKVPSS_SCALE2_SRC_SIZE (RKVPSS_SCALE2_BASE + 0x0008)
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#define RKVPSS_SCALE2_DST_SIZE (RKVPSS_SCALE2_BASE + 0x000c)
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#define RKVPSS_SCALE2_HY_FAC (RKVPSS_SCALE2_BASE + 0x0010)
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#define RKVPSS_SCALE2_HC_FAC (RKVPSS_SCALE2_BASE + 0x0014)
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#define RKVPSS_SCALE2_VY_FAC (RKVPSS_SCALE2_BASE + 0x0018)
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#define RKVPSS_SCALE2_VC_FAC (RKVPSS_SCALE2_BASE + 0x001c)
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#define RKVPSS_SCALE2_HY_OFFS (RKVPSS_SCALE2_BASE + 0x0020)
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#define RKVPSS_SCALE2_HC_OFFS (RKVPSS_SCALE2_BASE + 0x0024)
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#define RKVPSS_SCALE2_VY_OFFS (RKVPSS_SCALE2_BASE + 0x0028)
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#define RKVPSS_SCALE2_VC_OFFS (RKVPSS_SCALE2_BASE + 0x002c)
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#define RKVPSS_SCALE2_HY_SIZE (RKVPSS_SCALE2_BASE + 0x0040)
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#define RKVPSS_SCALE2_HC_SIZE (RKVPSS_SCALE2_BASE + 0x0044)
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#define RKVPSS_SCALE2_HY_OFFS_MI (RKVPSS_SCALE2_BASE + 0x0048)
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#define RKVPSS_SCALE2_HC_OFFS_MI (RKVPSS_SCALE2_BASE + 0x004c)
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#define RKVPSS_SCALE2_IN_CROP_OFFSET (RKVPSS_SCALE2_BASE + 0x0050)
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#define RKVPSS_SCALE2_CTRL_SHD (RKVPSS_SCALE2_BASE + 0x0080)
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#define RKVPSS_SCALE2_SRC_SIZE_SHD (RKVPSS_SCALE2_BASE + 0x0088)
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#define RKVPSS_SCALE2_DST_SIZE_SHD (RKVPSS_SCALE2_BASE + 0x008c)
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#define RKVPSS_SCALE2_HY_FAC_SHD (RKVPSS_SCALE2_BASE + 0x0090)
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#define RKVPSS_SCALE2_HC_FAC_SHD (RKVPSS_SCALE2_BASE + 0x0094)
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#define RKVPSS_SCALE2_VY_FAC_SHD (RKVPSS_SCALE2_BASE + 0x0098)
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#define RKVPSS_SCALE2_VC_FAC_SHD (RKVPSS_SCALE2_BASE + 0x009c)
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#define RKVPSS_SCALE2_HY_OFFS_SHD (RKVPSS_SCALE2_BASE + 0x00a0)
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#define RKVPSS_SCALE2_HC_OFFS_SHD (RKVPSS_SCALE2_BASE + 0x00a4)
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#define RKVPSS_SCALE2_VY_OFFS_SHD (RKVPSS_SCALE2_BASE + 0x00a8)
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#define RKVPSS_SCALE2_VC_OFFS_SHD (RKVPSS_SCALE2_BASE + 0x00ac)
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#define RKVPSS_SCALE2_HY_SIZE_SHD (RKVPSS_SCALE2_BASE + 0x00c0)
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#define RKVPSS_SCALE2_HC_SIZE_SHD (RKVPSS_SCALE2_BASE + 0x00c4)
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#define RKVPSS_SCALE2_HY_OFFS_MI_SHD (RKVPSS_SCALE2_BASE + 0x00c8)
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#define RKVPSS_SCALE2_HC_OFFS_MI_SHD (RKVPSS_SCALE2_BASE + 0x00cc)
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#define RKVPSS_SCALE2_IN_CROP_OFFSET_SHD (RKVPSS_SCALE2_BASE + 0x00d0)
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#define RKVPSS_SCALE3_BASE 0x2c00
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#define RKVPSS_SCALE3_CTRL (RKVPSS_SCALE3_BASE + 0x0000)
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#define RKVPSS_SCALE3_UPDATE (RKVPSS_SCALE3_BASE + 0x0004)
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#define RKVPSS_SCALE3_SRC_SIZE (RKVPSS_SCALE3_BASE + 0x0008)
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#define RKVPSS_SCALE3_DST_SIZE (RKVPSS_SCALE3_BASE + 0x000c)
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#define RKVPSS_SCALE3_HY_FAC (RKVPSS_SCALE3_BASE + 0x0010)
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#define RKVPSS_SCALE3_HC_FAC (RKVPSS_SCALE3_BASE + 0x0014)
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#define RKVPSS_SCALE3_VY_FAC (RKVPSS_SCALE3_BASE + 0x0018)
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#define RKVPSS_SCALE3_VC_FAC (RKVPSS_SCALE3_BASE + 0x001c)
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#define RKVPSS_SCALE3_HY_OFFS (RKVPSS_SCALE3_BASE + 0x0020)
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#define RKVPSS_SCALE3_HC_OFFS (RKVPSS_SCALE3_BASE + 0x0024)
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#define RKVPSS_SCALE3_VY_OFFS (RKVPSS_SCALE3_BASE + 0x0028)
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#define RKVPSS_SCALE3_VC_OFFS (RKVPSS_SCALE3_BASE + 0x002c)
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#define RKVPSS_SCALE3_HY_SIZE (RKVPSS_SCALE3_BASE + 0x0040)
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#define RKVPSS_SCALE3_HC_SIZE (RKVPSS_SCALE3_BASE + 0x0044)
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#define RKVPSS_SCALE3_HY_OFFS_MI (RKVPSS_SCALE3_BASE + 0x0048)
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#define RKVPSS_SCALE3_HC_OFFS_MI (RKVPSS_SCALE3_BASE + 0x004c)
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#define RKVPSS_SCALE3_IN_CROP_OFFSET (RKVPSS_SCALE3_BASE + 0x0050)
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#define RKVPSS_SCALE3_CTRL_SHD (RKVPSS_SCALE3_BASE + 0x0080)
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#define RKVPSS_SCALE3_SRC_SIZE_SHD (RKVPSS_SCALE3_BASE + 0x0088)
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#define RKVPSS_SCALE3_DST_SIZE_SHD (RKVPSS_SCALE3_BASE + 0x008c)
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#define RKVPSS_SCALE3_HY_FAC_SHD (RKVPSS_SCALE3_BASE + 0x0090)
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#define RKVPSS_SCALE3_HC_FAC_SHD (RKVPSS_SCALE3_BASE + 0x0094)
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#define RKVPSS_SCALE3_VY_FAC_SHD (RKVPSS_SCALE3_BASE + 0x0098)
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#define RKVPSS_SCALE3_VC_FAC_SHD (RKVPSS_SCALE3_BASE + 0x009c)
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#define RKVPSS_SCALE3_HY_OFFS_SHD (RKVPSS_SCALE3_BASE + 0x00a0)
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#define RKVPSS_SCALE3_HC_OFFS_SHD (RKVPSS_SCALE3_BASE + 0x00a4)
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#define RKVPSS_SCALE3_VY_OFFS_SHD (RKVPSS_SCALE3_BASE + 0x00a8)
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#define RKVPSS_SCALE3_VC_OFFS_SHD (RKVPSS_SCALE3_BASE + 0x00ac)
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#define RKVPSS_SCALE3_HY_SIZE_SHD (RKVPSS_SCALE3_BASE + 0x00c0)
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#define RKVPSS_SCALE3_HC_SIZE_SHD (RKVPSS_SCALE3_BASE + 0x00c4)
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#define RKVPSS_SCALE3_HY_OFFS_MI_SHD (RKVPSS_SCALE3_BASE + 0x00c8)
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#define RKVPSS_SCALE3_HC_OFFS_MI_SHD (RKVPSS_SCALE3_BASE + 0x00cc)
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#define RKVPSS_SCALE3_IN_CROP_OFFSET_SHD (RKVPSS_SCALE3_BASE + 0x00d0)
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#define RKVPSS_MI_BASE 0x3000
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#define RKVPSS_MI_WR_CTRL (RKVPSS_MI_BASE + 0x0000)
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#define RKVPSS_MI_WR_INIT (RKVPSS_MI_BASE + 0x0004)
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#define RKVPSS_MI_WR_WRAP_CTRL (RKVPSS_MI_BASE + 0x0010)
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#define RKVPSS_MI_WR_VFLIP_CTRL (RKVPSS_MI_BASE + 0x0014)
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#define RKVPSS_MI_HURRY_CTRL (RKVPSS_MI_BASE + 0x0040)
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#define RKVPSS_MI_ARQOS_CTRL (RKVPSS_MI_BASE + 0x0044)
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#define RKVPSS_MI_AWQOS_CTRL (RKVPSS_MI_BASE + 0x0048)
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#define RKVPSS_MI_IMSC (RKVPSS_MI_BASE + 0x0050)
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#define RKVPSS_MI_RIS (RKVPSS_MI_BASE + 0x0054)
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#define RKVPSS_MI_MIS (RKVPSS_MI_BASE + 0x0058)
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#define RKVPSS_MI_ICR (RKVPSS_MI_BASE + 0x005c)
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#define RKVPSS_MI_ISR (RKVPSS_MI_BASE + 0x0060)
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#define RKVPSS_MI_STATUS (RKVPSS_MI_BASE + 0x0070)
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#define RKVPSS_MI_STATUS_CLR (RKVPSS_MI_BASE + 0x0074)
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#define RKVPSS_MI_RD_CTRL (RKVPSS_MI_BASE + 0x0100)
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#define RKVPSS_MI_RD_INIT (RKVPSS_MI_BASE + 0x0104)
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#define RKVPSS_MI_RD_START (RKVPSS_MI_BASE + 0x0108)
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#define RKVPSS_MI_RD_Y_BASE (RKVPSS_MI_BASE + 0x0110)
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#define RKVPSS_MI_RD_Y_WIDTH (RKVPSS_MI_BASE + 0x0114)
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#define RKVPSS_MI_RD_Y_HEIGHT (RKVPSS_MI_BASE + 0x0118)
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#define RKVPSS_MI_RD_Y_STRIDE (RKVPSS_MI_BASE + 0x011c)
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#define RKVPSS_MI_RD_C_BASE (RKVPSS_MI_BASE + 0x0120)
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#define RKVPSS_MI_RD_Y_BASE_SHD (RKVPSS_MI_BASE + 0x0130)
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#define RKVPSS_MI_RD_C_BASE_SHD (RKVPSS_MI_BASE + 0x0134)
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#define RKVPSS_MI_RD_Y_WIDTH_SHD (RKVPSS_MI_BASE + 0x0138)
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#define RKVPSS_MI_RD_Y_HEIGHT_SHD (RKVPSS_MI_BASE + 0x013c)
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#define RKVPSS_AXI_CFG_RD_CTRL (RKVPSS_MI_BASE + 0x0160)
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#define RKVPSS_AXI_CFG_RD_BASE (RKVPSS_MI_BASE + 0x0164)
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#define RKVPSS_AXI_CFG_RD_H_WSIZE (RKVPSS_MI_BASE + 0x0168)
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#define RKVPSS_AXI_CFG_RD_V_SIZE (RKVPSS_MI_BASE + 0x016c)
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#define RKVPSS_MI_CHN0_WR_CTRL (RKVPSS_MI_BASE + 0x0200)
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#define RKVPSS_MI_CHN0_WR_Y_BASE (RKVPSS_MI_BASE + 0x0210)
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#define RKVPSS_MI_CHN0_WR_Y_SIZE (RKVPSS_MI_BASE + 0x0214)
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#define RKVPSS_MI_CHN0_WR_Y_OFFS_CNT (RKVPSS_MI_BASE + 0x0218)
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#define RKVPSS_MI_CHN0_WR_Y_OFFS_CNT_START (RKVPSS_MI_BASE + 0x021c)
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#define RKVPSS_MI_CHN0_WR_CB_BASE (RKVPSS_MI_BASE + 0x0220)
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#define RKVPSS_MI_CHN0_WR_CB_SIZE (RKVPSS_MI_BASE + 0x0224)
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#define RKVPSS_MI_CHN0_WR_CB_OFFS_CNT (RKVPSS_MI_BASE + 0x0228)
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#define RKVPSS_MI_CHN0_WR_CB_OFFS_CNT_START (RKVPSS_MI_BASE + 0x022c)
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#define RKVPSS_MI_CHN0_WR_Y_STRIDE (RKVPSS_MI_BASE + 0x0230)
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#define RKVPSS_MI_CHN0_WR_Y_PIC_WIDTH (RKVPSS_MI_BASE + 0x0234)
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#define RKVPSS_MI_CHN0_WR_Y_PIC_SIZE (RKVPSS_MI_BASE + 0x023c)
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#define RKVPSS_MI_CHN0_WR_CTRL_SHD (RKVPSS_MI_BASE + 0x0250)
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#define RKVPSS_MI_CHN0_WR_Y_BASE_SHD (RKVPSS_MI_BASE + 0x0260)
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#define RKVPSS_MI_CHN0_WR_Y_SIZE_SHD (RKVPSS_MI_BASE + 0x0264)
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#define RKVPSS_MI_CHN0_WR_Y_OFFS_CNT_SHD (RKVPSS_MI_BASE + 0x0268)
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#define RKVPSS_MI_CHN0_WR_CB_BASE_SHD (RKVPSS_MI_BASE + 0x0270)
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#define RKVPSS_MI_CHN0_WR_CB_SIZE_SHD (RKVPSS_MI_BASE + 0x0274)
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#define RKVPSS_MI_CHN0_WR_CB_OFFS_CNT_SHD (RKVPSS_MI_BASE + 0x0278)
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#define RKVPSS_MI_CHN0_WR_Y_END_ADDR (RKVPSS_MI_BASE + 0x0280)
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#define RKVPSS_MI_CHN0_WR_CB_END_ADDR (RKVPSS_MI_BASE + 0x0284)
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#define RKVPSS_MI_CHN0_WR_LINE_CNT (RKVPSS_MI_BASE + 0x0288)
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#define RKVPSS_MI_CHN1_WR_CTRL (RKVPSS_MI_BASE + 0x0300)
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#define RKVPSS_MI_CHN1_WR_Y_BASE (RKVPSS_MI_BASE + 0x0310)
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#define RKVPSS_MI_CHN1_WR_Y_SIZE (RKVPSS_MI_BASE + 0x0314)
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#define RKVPSS_MI_CHN1_WR_Y_OFFS_CNT (RKVPSS_MI_BASE + 0x0318)
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#define RKVPSS_MI_CHN1_WR_Y_OFFS_CNT_START (RKVPSS_MI_BASE + 0x031c)
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#define RKVPSS_MI_CHN1_WR_CB_BASE (RKVPSS_MI_BASE + 0x0320)
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#define RKVPSS_MI_CHN1_WR_CB_SIZE (RKVPSS_MI_BASE + 0x0324)
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#define RKVPSS_MI_CHN1_WR_CB_OFFS_CNT (RKVPSS_MI_BASE + 0x0328)
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#define RKVPSS_MI_CHN1_WR_CB_OFFS_CNT_START (RKVPSS_MI_BASE + 0x032c)
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#define RKVPSS_MI_CHN1_WR_Y_STRIDE (RKVPSS_MI_BASE + 0x0330)
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#define RKVPSS_MI_CHN1_WR_Y_PIC_WIDTH (RKVPSS_MI_BASE + 0x0334)
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#define RKVPSS_MI_CHN1_WR_Y_PIC_SIZE (RKVPSS_MI_BASE + 0x033c)
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#define RKVPSS_MI_CHN1_WR_CTRL_SHD (RKVPSS_MI_BASE + 0x0350)
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#define RKVPSS_MI_CHN1_WR_Y_BASE_SHD (RKVPSS_MI_BASE + 0x0360)
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#define RKVPSS_MI_CHN1_WR_Y_SIZE_SHD (RKVPSS_MI_BASE + 0x0364)
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#define RKVPSS_MI_CHN1_WR_Y_OFFS_CNT_SHD (RKVPSS_MI_BASE + 0x0368)
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#define RKVPSS_MI_CHN1_WR_CB_BASE_SHD (RKVPSS_MI_BASE + 0x0370)
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#define RKVPSS_MI_CHN1_WR_CB_SIZE_SHD (RKVPSS_MI_BASE + 0x0374)
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#define RKVPSS_MI_CHN1_WR_CB_OFFS_CNT_SHD (RKVPSS_MI_BASE + 0x0378)
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#define RKVPSS_MI_CHN1_WR_Y_END_ADDR (RKVPSS_MI_BASE + 0x0380)
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#define RKVPSS_MI_CHN1_WR_CB_END_ADDR (RKVPSS_MI_BASE + 0x0384)
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#define RKVPSS_MI_CHN1_WR_LINE_CNT (RKVPSS_MI_BASE + 0x0388)
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#define RKVPSS_MI_CHN1_WR_Y2R_COE00 (RKVPSS_MI_BASE + 0x03a0)
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#define RKVPSS_MI_CHN1_WR_Y2R_COE01 (RKVPSS_MI_BASE + 0x03a4)
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#define RKVPSS_MI_CHN1_WR_Y2R_COE02 (RKVPSS_MI_BASE + 0x03a8)
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#define RKVPSS_MI_CHN1_WR_Y2R_OFF0 (RKVPSS_MI_BASE + 0x03ac)
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#define RKVPSS_MI_CHN1_WR_Y2R_COE10 (RKVPSS_MI_BASE + 0x03b0)
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#define RKVPSS_MI_CHN1_WR_Y2R_COE11 (RKVPSS_MI_BASE + 0x03b4)
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#define RKVPSS_MI_CHN1_WR_Y2R_COE12 (RKVPSS_MI_BASE + 0x03b8)
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#define RKVPSS_MI_CHN1_WR_Y2R_OFF1 (RKVPSS_MI_BASE + 0x03bc)
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#define RKVPSS_MI_CHN1_WR_Y2R_COE20 (RKVPSS_MI_BASE + 0x03c0)
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#define RKVPSS_MI_CHN1_WR_Y2R_COE21 (RKVPSS_MI_BASE + 0x03c4)
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#define RKVPSS_MI_CHN1_WR_Y2R_COE32 (RKVPSS_MI_BASE + 0x03c8)
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#define RKVPSS_MI_CHN1_WR_Y2R_OFF2 (RKVPSS_MI_BASE + 0x03cc)
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#define RKVPSS_MI_CHN2_WR_CTRL (RKVPSS_MI_BASE + 0x0400)
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#define RKVPSS_MI_CHN2_WR_Y_BASE (RKVPSS_MI_BASE + 0x0410)
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#define RKVPSS_MI_CHN2_WR_Y_SIZE (RKVPSS_MI_BASE + 0x0414)
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#define RKVPSS_MI_CHN2_WR_Y_OFFS_CNT (RKVPSS_MI_BASE + 0x0418)
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#define RKVPSS_MI_CHN2_WR_Y_OFFS_CNT_START (RKVPSS_MI_BASE + 0x041c)
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#define RKVPSS_MI_CHN2_WR_CB_BASE (RKVPSS_MI_BASE + 0x0420)
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#define RKVPSS_MI_CHN2_WR_CB_SIZE (RKVPSS_MI_BASE + 0x0424)
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#define RKVPSS_MI_CHN2_WR_CB_OFFS_CNT (RKVPSS_MI_BASE + 0x0428)
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#define RKVPSS_MI_CHN2_WR_CB_OFFS_CNT_START (RKVPSS_MI_BASE + 0x042c)
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#define RKVPSS_MI_CHN2_WR_Y_STRIDE (RKVPSS_MI_BASE + 0x0430)
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#define RKVPSS_MI_CHN2_WR_Y_PIC_WIDTH (RKVPSS_MI_BASE + 0x0434)
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#define RKVPSS_MI_CHN2_WR_Y_PIC_SIZE (RKVPSS_MI_BASE + 0x043c)
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#define RKVPSS_MI_CHN2_WR_CTRL_SHD (RKVPSS_MI_BASE + 0x0450)
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#define RKVPSS_MI_CHN2_WR_Y_BASE_SHD (RKVPSS_MI_BASE + 0x0460)
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#define RKVPSS_MI_CHN2_WR_Y_SIZE_SHD (RKVPSS_MI_BASE + 0x0464)
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#define RKVPSS_MI_CHN2_WR_Y_OFFS_CNT_SHD (RKVPSS_MI_BASE + 0x0468)
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#define RKVPSS_MI_CHN2_WR_CB_BASE_SHD (RKVPSS_MI_BASE + 0x0470)
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#define RKVPSS_MI_CHN2_WR_CB_SIZE_SHD (RKVPSS_MI_BASE + 0x0474)
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#define RKVPSS_MI_CHN2_WR_CB_OFFS_CNT_SHD (RKVPSS_MI_BASE + 0x0478)
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#define RKVPSS_MI_CHN2_WR_Y_END_ADDR (RKVPSS_MI_BASE + 0x0480)
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#define RKVPSS_MI_CHN2_WR_CB_END_ADDR (RKVPSS_MI_BASE + 0x0484)
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#define RKVPSS_MI_CHN2_WR_LINE_CNT (RKVPSS_MI_BASE + 0x0488)
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#define RKVPSS_MI_CHN3_WR_CTRL (RKVPSS_MI_BASE + 0x0500)
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#define RKVPSS_MI_CHN3_WR_Y_BASE (RKVPSS_MI_BASE + 0x0510)
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#define RKVPSS_MI_CHN3_WR_Y_SIZE (RKVPSS_MI_BASE + 0x0514)
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#define RKVPSS_MI_CHN3_WR_Y_OFFS_CNT (RKVPSS_MI_BASE + 0x0518)
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#define RKVPSS_MI_CHN3_WR_Y_OFFS_CNT_START (RKVPSS_MI_BASE + 0x051c)
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#define RKVPSS_MI_CHN3_WR_CB_BASE (RKVPSS_MI_BASE + 0x0520)
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#define RKVPSS_MI_CHN3_WR_CB_SIZE (RKVPSS_MI_BASE + 0x0524)
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#define RKVPSS_MI_CHN3_WR_CB_OFFS_CNT (RKVPSS_MI_BASE + 0x0528)
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#define RKVPSS_MI_CHN3_WR_CB_OFFS_CNT_START (RKVPSS_MI_BASE + 0x052c)
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#define RKVPSS_MI_CHN3_WR_Y_STRIDE (RKVPSS_MI_BASE + 0x0530)
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#define RKVPSS_MI_CHN3_WR_Y_PIC_WIDTH (RKVPSS_MI_BASE + 0x0534)
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#define RKVPSS_MI_CHN3_WR_Y_PIC_SIZE (RKVPSS_MI_BASE + 0x053c)
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#define RKVPSS_MI_CHN3_WR_CTRL_SHD (RKVPSS_MI_BASE + 0x0550)
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#define RKVPSS_MI_CHN3_WR_Y_BASE_SHD (RKVPSS_MI_BASE + 0x0560)
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#define RKVPSS_MI_CHN3_WR_Y_SIZE_SHD (RKVPSS_MI_BASE + 0x0564)
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#define RKVPSS_MI_CHN3_WR_Y_OFFS_CNT_SHD (RKVPSS_MI_BASE + 0x0568)
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#define RKVPSS_MI_CHN3_WR_CB_BASE_SHD (RKVPSS_MI_BASE + 0x0570)
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#define RKVPSS_MI_CHN3_WR_CB_SIZE_SHD (RKVPSS_MI_BASE + 0x0574)
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#define RKVPSS_MI_CHN3_WR_CB_OFFS_CNT_SHD (RKVPSS_MI_BASE + 0x0578)
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#define RKVPSS_MI_CHN3_WR_Y_END_ADDR (RKVPSS_MI_BASE + 0x0580)
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#define RKVPSS_MI_CHN3_WR_CB_END_ADDR (RKVPSS_MI_BASE + 0x0584)
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#define RKVPSS_MI_CHN3_WR_LINE_CNT (RKVPSS_MI_BASE + 0x0588)
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#define RKVPSS_MI_RD_R2Y_COE00 (RKVPSS_MI_BASE + 0x058c)
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#define RKVPSS_MI_RD_R2Y_COE01 (RKVPSS_MI_BASE + 0x0590)
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#define RKVPSS_MI_RD_R2Y_COE02 (RKVPSS_MI_BASE + 0x0594)
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#define RKVPSS_MI_RD_R2Y_OFF0 (RKVPSS_MI_BASE + 0x0598)
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#define RKVPSS_MI_RD_R2Y_COE10 (RKVPSS_MI_BASE + 0x059c)
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#define RKVPSS_MI_RD_R2Y_COE11 (RKVPSS_MI_BASE + 0x05a0)
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#define RKVPSS_MI_RD_R2Y_COE12 (RKVPSS_MI_BASE + 0x05a4)
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#define RKVPSS_MI_RD_R2Y_OFF1 (RKVPSS_MI_BASE + 0x05a8)
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#define RKVPSS_MI_RD_R2Y_COE20 (RKVPSS_MI_BASE + 0x05ac)
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#define RKVPSS_MI_RD_R2Y_COE21 (RKVPSS_MI_BASE + 0x05b0)
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#define RKVPSS_MI_RD_R2Y_COE22 (RKVPSS_MI_BASE + 0x05b4)
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#define RKVPSS_MI_RD_R2Y_OFF2 (RKVPSS_MI_BASE + 0x05b8)
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/* VPSS_CTRL */
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#define RKVPSS_MIR_EN BIT(4)
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#define RKVPSS_VPSS2ENC_SEL BIT(8)
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#define RKVPSS_VPSS2ENC_PIPE_EN BIT(9)
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#define RKVPSS_VPSS2ENC_CNT_SEL BIT(10)
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#define RKVPSS_FRM_END_MODE BIT(24)
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#define RKVPSS_SUB_FRM_ST_EN BIT(25)
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#define RKVPSS_NOC_IDLE_DIS BIT(28)
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#define RKVPSS_ACK_FRM_PRO_DIS BIT(29)
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#define RKVPSS_CHN_JUDGE_DIS BIT(30)
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#define RKVPSS_ALL_CLK_DIS BIT(31)
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/* VPSS_ONLINE */
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#define RKVPSS_ISP2VPSS_CHN0_SEL(x) ((x) & 0x3)
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#define RKVPSS_ISP2VPSS_CHN1_SEL(x) (((x) & 0x3) << 2)
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#define RKVPSS_ISP2VPSS_CHN2_SEL(x) (((x) & 0x3) << 4)
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#define RKVPSS_ISP2VPSS_CHN3_SEL(x) (((x) & 0x3) << 6)
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#define RKVPSS_ONLINE_MODE_MASK GENMASK(17, 16)
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#define RKVPSS_VPSS_OFFLINE 0
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#define RKVPSS_ISP2VPSS_ONLINE1 BIT(16)
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#define RKVPSS_ISP2VPSS_ONLINE2 BIT(17)
|
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#define RKVPSS_ISP2VPSS_ONLINE2_CMSC_EN BIT(18)
|
|
|
|
/* VPSS_UPDATE */
|
|
#define RKVPSS_CFG_FORCE_UPD BIT(0)
|
|
#define RKVPSS_CFG_GEN_UPD BIT(1)
|
|
#define RKVPSS_MIR_FORCE_UPD BIT(4)
|
|
#define RKVPSS_MIR_GEN_UPD BIT(5)
|
|
#define RKVPSS_CHN_FORCE_UPD BIT(8)
|
|
#define RKVPSS_ONLINE2_CHN_FORCE_UPD BIT(9)
|
|
|
|
/* VPSS_CLK_EN */
|
|
#define RKVPSS_MIR_CLK_EN BIT(0)
|
|
#define RKVPSS_CMSC_CLK_EN BIT(1)
|
|
#define RKVPSS_CR_CLK_EN BIT(2)
|
|
#define RKVPSS_CR1_CLK_EN BIT(3)
|
|
#define RKVPSS_SCL0_CLK_EN BIT(4)
|
|
#define RKVPSS_SCL1_CLK_EN BIT(5)
|
|
#define RKVPSS_SCL2_CLK_EN BIT(6)
|
|
#define RKVPSS_SCL3_CLK_EN BIT(7)
|
|
#define RKVPSS_RATIO0_CLK_EN BIT(8)
|
|
#define RKVPSS_RATIO1_CLK_EN BIT(9)
|
|
#define RKVPSS_RATIO2_CLK_EN BIT(10)
|
|
#define RKVPSS_RATIO3_CLK_EN BIT(11)
|
|
#define RKVPSS_MI_CLK_EN BIT(16)
|
|
|
|
/* VPSS_CLK_GATE */
|
|
#define RKVPSS_MIR_CKG_DIS BIT(0)
|
|
#define RKVPSS_CMSC_CKG_DIS BIT(1)
|
|
#define RKVPSS_SCL0_CKG_DIS BIT(4)
|
|
#define RKVPSS_SCL1_CKG_DIS BIT(5)
|
|
#define RKVPSS_SCL2_CKG_DIS BIT(6)
|
|
#define RKVPSS_SCL3_CKG_DIS BIT(7)
|
|
#define RKVPSS_RATIO0_CKG_DIS BIT(8)
|
|
#define RKVPSS_RATIO1_CKG_DIS BIT(9)
|
|
#define RKVPSS_RATIO2_CKG_DIS BIT(10)
|
|
#define RKVPSS_RATIO3_CKG_DIS BIT(11)
|
|
#define RKVPSS_MI_CHN0_CKG_DIS BIT(16)
|
|
#define RKVPSS_MI_CHN1_CKG_DIS BIT(17)
|
|
#define RKVPSS_MI_CHN2_CKG_DIS BIT(18)
|
|
#define RKVPSS_MI_CHN3_CKG_DIS BIT(19)
|
|
#define RKVPSS_MI_RD_CKG_DIS BIT(24)
|
|
|
|
/* VPSS_RESET */
|
|
#define RKVPSS_SOFT_RST BIT(0)
|
|
#define RKVPSS_RST_PROTECT_DIS BIT(30)
|
|
#define RKVPSS_RST_SAFETY_DONE_CLR BIT(31)
|
|
|
|
/* VPSS_SLICE_CTRL */
|
|
#define RKVPSS_SLICE_ST BIT(0)
|
|
#define RKVPSS_SLICE_EN BIT(1)
|
|
|
|
/* VPSS_IRQ_CFG */
|
|
#define RKVPSS_CROP_IN_IRQ_LINE(x) ((x) & 0x3fff)
|
|
|
|
/* VPSS_IMSC */
|
|
#define RKVPSS_CROP_IN_FRM_ST BIT(0)
|
|
#define RKVPSS_CROP_IN_FRM_END BIT(1)
|
|
#define RKVPSS_CROP_IN_CFG_IRQ BIT(2)
|
|
#define RKVPSS_ALL_FRM_END BIT(3)
|
|
#define RKVPSS_MIR_FRM_END BIT(4)
|
|
#define RKVPSS_CROP1_IN_FRM_END BIT(5)
|
|
#define RKVPSS_CROP1_IN_CFG_IRQ BIT(6)
|
|
#define RKVPSS_ISP_ALL_FRM_END BIT(7)
|
|
#define RKVPSS_SCL0_IN_FRM_END BIT(8)
|
|
#define RKVPSS_SCL1_IN_FRM_END BIT(9)
|
|
#define RKVPSS_SCL2_IN_FRM_END BIT(10)
|
|
#define RKVPSS_SCL3_IN_FRM_END BIT(11)
|
|
#define RKVPSS_RATIO0_IN_FRM_END BIT(12)
|
|
#define RKVPSS_RATIO1_IN_FRM_END BIT(13)
|
|
#define RKVPSS_RATIO2_IN_FRM_END BIT(14)
|
|
#define RKVPSS_RATIO3_IN_FRM_END BIT(15)
|
|
|
|
/* VPSS_CTRL_SHD */
|
|
#define RKVPSS_MIR_EN_SHD BIT(4)
|
|
|
|
/* VPSS_ONLINE_SHD */
|
|
#define RKVPSS_CHN0_EN_SHD BIT(0)
|
|
#define RKVPSS_ISP_CHN0_EN_SHD BIT(1)
|
|
#define RKVPSS_CHN1_EN_SHD BIT(2)
|
|
#define RKVPSS_ISP_CHN1_EN_SHD BIT(3)
|
|
#define RKVPSS_CHN2_EN_SHD BIT(4)
|
|
#define RKVPSS_ISP_CHN2_EN_SHD BIT(5)
|
|
#define RKVPSS_CHN3_EN_SHD BIT(6)
|
|
#define RKVPSS_ISP_CHN3_EN_SHD BIT(7)
|
|
#define RKVPSS_ISP2VPSS_ONLINE1_EN_SHD BIT(16)
|
|
#define RKVPSS_ISP2VPSS_ONLINE2_EN_SHD BIT(17)
|
|
#define RKVPSS_ISP2VPSS_CMSC_EN_SHD BIT(18)
|
|
|
|
/* VPSS_WORKING */
|
|
#define RKVPSS_MIR_WORKING BIT(0)
|
|
#define RKVPSS_CMSC_WORKING BIT(1)
|
|
#define RKVPSS_SCL0_WORKING BIT(4)
|
|
#define RKVPSS_SCL1_WORKING BIT(5)
|
|
#define RKVPSS_SCL2_WORKING BIT(6)
|
|
#define RKVPSS_SCL3_WORKING BIT(7)
|
|
#define RKVPSS_RATIO0_WORKING BTI(8)
|
|
#define RKVPSS_RATIO1_WORKING BTI(9)
|
|
#define RKVPSS_RATIO2_WORKING BTI(10)
|
|
#define RKVPSS_RATIO3_WORKING BTI(11)
|
|
#define RKVPSS_ISP_WORKING BIT(28)
|
|
#define RKVPSS_VPSS_WORKING BIT(29)
|
|
#define RKVPSS_ISP2VPSS_WORKING BIT(30)
|
|
#define RKVPSS_OFFLINE_WORKING BIT(31)
|
|
|
|
/* VPSS_LINE_CNT0 */
|
|
#define RKVPSS_CROP_IN_LINE(x) ((x) & 0x3fff)
|
|
#define RKVPSS_CHN0_IN_LINE(x) (((x) & 0x3fff) >> 16)
|
|
|
|
/* VPSS_LINE_CNT1 */
|
|
#define RKVPSS_CROP1_IN_LINE(x) ((x) & 0x3fff)
|
|
|
|
/* VPSS_Y2R_COE00 */
|
|
#define RKVPSS_Y2R_RB_SWAP BIT(30)
|
|
#define RKVPSS_Y2R_EN BIT(31)
|
|
|
|
/* CMSC_CTRL */
|
|
#define RKVPSS_CMSC_EN BIT(0)
|
|
#define RKVPSS_CMSC_CHN_EN(x) (BIT(4) << (x))
|
|
#define RKVPSS_CMSC_BLK_SZIE(x) (((x) & 0x3) << 8)
|
|
#define RKVPSS_CMSC_EN_SHD BIT(16)
|
|
#define RKVPSS_CMSC_CHN0_EN_SHD BIT(20)
|
|
#define RKVPSS_CMSC_CHN1_EN_SHD BIT(21)
|
|
#define RKVPSS_CMSC_CHN2_EN_SHD BIT(22)
|
|
#define RKVPSS_CMSC_CHN3_EN_SHD BIT(23)
|
|
|
|
/* CMSC_UPDATE */
|
|
#define RKVPSS_CMSC_FORCE_UPD BIT(4)
|
|
#define RKVPSS_CMSC_GEN_UPD BIT(5)
|
|
|
|
/* CMSC_INSCT_CORR */
|
|
#define RKVPSS_CMSC_WIN0_INTSCT_EXIST_CORR BIT(0)
|
|
#define RKVPSS_CMSC_WIN1_INTSCT_EXIST_CORR BIT(1)
|
|
#define RKVPSS_CMSC_WIN2_INTSCT_EXIST_CORR BIT(2)
|
|
#define RKVPSS_CMSC_WIN3_INTSCT_EXIST_CORR BIT(3)
|
|
#define RKVPSS_CMSC_WIN4_INTSCT_EXIST_CORR BIT(4)
|
|
#define RKVPSS_CMSC_WIN5_INTSCT_EXIST_CORR BIT(5)
|
|
#define RKVPSS_CMSC_WIN6_INTSCT_EXIST_CORR BIT(6)
|
|
#define RKVPSS_CMSC_WIN7_INTSCT_EXIST_CORR BIT(7)
|
|
#define RKVPSS_CMSC_WIN0_INTSCT_EXIST_CORR_DIS BIT(8)
|
|
#define RKVPSS_CMSC_WIN1_INTSCT_EXIST_CORR_DIS BIT(9)
|
|
#define RKVPSS_CMSC_WIN2_INTSCT_EXIST_CORR_DIS BIT(10)
|
|
#define RKVPSS_CMSC_WIN3_INTSCT_EXIST_CORR_DIS BIT(11)
|
|
#define RKVPSS_CMSC_WIN4_INTSCT_EXIST_CORR_DIS BIT(12)
|
|
#define RKVPSS_CMSC_WIN5_INTSCT_EXIST_CORR_DIS BIT(13)
|
|
#define RKVPSS_CMSC_WIN6_INTSCT_EXIST_CORR_DIS BIT(14)
|
|
#define RKVPSS_CMSC_WIN7_INTSCT_EXIST_CORR_DIS BIT(15)
|
|
#define RKVPSS_CMSC_WIN0_INTSCT_CONTI_CORR_DIS BIT(16)
|
|
#define RKVPSS_CMSC_WIN1_INTSCT_CONTI_CORR_DIS BIT(17)
|
|
#define RKVPSS_CMSC_WIN2_INTSCT_CONTI_CORR_DIS BIT(18)
|
|
#define RKVPSS_CMSC_WIN3_INTSCT_CONTI_CORR_DIS BIT(19)
|
|
#define RKVPSS_CMSC_WIN4_INTSCT_CONTI_CORR_DIS BIT(20)
|
|
#define RKVPSS_CMSC_WIN5_INTSCT_CONTI_CORR_DIS BIT(21)
|
|
#define RKVPSS_CMSC_WIN6_INTSCT_CONTI_CORR_DIS BIT(22)
|
|
#define RKVPSS_CMSC_WIN7_INTSCT_CONTI_CORR_DIS BIT(23)
|
|
#define RKVPSS_CMSC_WIN0_INTSCT_PTY_CORR_DIS BIT(24)
|
|
#define RKVPSS_CMSC_WIN1_INTSCT_PTY_CORR_DIS BIT(25)
|
|
#define RKVPSS_CMSC_WIN2_INTSCT_PTY_CORR_DIS BIT(26)
|
|
#define RKVPSS_CMSC_WIN3_INTSCT_PTY_CORR_DIS BIT(27)
|
|
#define RKVPSS_CMSC_WIN4_INTSCT_PTY_CORR_DIS BIT(28)
|
|
#define RKVPSS_CMSC_WIN5_INTSCT_PTY_CORR_DIS BIT(29)
|
|
#define RKVPSS_CMSC_WIN6_INTSCT_PTY_CORR_DIS BIT(30)
|
|
#define RKVPSS_CMSC_WIN7_INTSCT_PTY_CORR_DIS BIT(31)
|
|
|
|
#define RKVPSS_CMSC_CHN_WIN_EN(x) ((x) & 0xff)
|
|
#define RKVPSS_CMSC_CHN_MODE(x) ((x) & 0xff)
|
|
#define RKVPSS_CMSK_WIN_YUV(y, u, v) ((y) | ((u) << 8) | ((v) << 16))
|
|
#define RKVPSS_CMSC_WIN_ALPHA(x) (((x) & 0xf) << 24)
|
|
#define RKVPSS_CMSC_WIN_INTSCT_PTY_CORR(x) (((x) & 0x3) << 28)
|
|
|
|
#define RKVPSS_CMSC_WIN_VTX(x, y) ((x) | ((y) << 16))
|
|
#define RKVPSS_CMSC_WIN_SLP(x, y) (((x) & 0x3ffff) | (y) << 20)
|
|
|
|
/* CROP_CTRL */
|
|
#define RKVPSS_CROP_CHN_EN(x) (1 << (x))
|
|
#define RKVPSS_CROP_IN_UPD_DIS BIT(31)
|
|
|
|
/* CROP_UPDATE */
|
|
#define RKVPSS_CROP_FORCE_UPD BIT(4)
|
|
#define RKVPSS_CROP_GEN_UPD BIT(5)
|
|
#define RKVPSS_CROP_CHN_FORCE_UPD(x) (0x100 << (x))
|
|
|
|
/* CROP_CTRL_SHD */
|
|
#define RKVPSS_CROP_CHN0_EN_SHD BIT(0)
|
|
#define RKVPSS_CROP_CHN1_EN_SHD BIT(1)
|
|
#define RKVPSS_CROP_CHN2_EN_SHD BIT(2)
|
|
#define RKVPSS_CROP_CHN3_EN_SHD BIT(3)
|
|
|
|
/* ZME_CTRL */
|
|
#define RKVPSS_ZME_GATING_EN BIT(0)
|
|
#define RKVPSS_ZME_CLIP_EN BIT(13)
|
|
#define RKVPSS_ZME_IN_CLIP_EN BIT(14)
|
|
#define RKVPSS_ZME_8K_EN BIT(15)
|
|
#define RKVPSS_ZME_422TO420_EN BIT(30)
|
|
#define RKVPSS_ZME_SCL_YUV420_REAL_EN BIT(31)
|
|
|
|
/* ZME_UPDATE */
|
|
#define RKVPSS_ZME_FORCE_UPD BIT(4)
|
|
#define RKVPSS_ZME_GEN_UPD BIT(5)
|
|
|
|
/* Y/UV_SCL_CTRL */
|
|
#define RKVPSS_ZME_XSD_EN BIT(0)
|
|
#define RKVPSS_ZME_XSU_EN BIT(1)
|
|
#define RKVPSS_ZME_XSCL_MODE (BIT(2) | BIT(3))
|
|
#define RKVPSS_ZME_YSD_EN BIT(4)
|
|
#define RKVPSS_ZME_YSU_EN BIT(5)
|
|
#define RKVPSS_ZME_YSCL_MODE (BIT(6) | BIT(7))
|
|
#define RKVPSS_ZME_DERING_EN BIT(8)
|
|
#define RKVPSS_ZME_GT_EN BIT(9)
|
|
#define RKVPSS_ZME_GT_MODE(x) (((x) & 0x3) << 10)
|
|
#define RKVPSS_ZME_XGT_EN BIT(12)
|
|
#define RKVPSS_ZME_XGT_MODE(x) (((x) & 0x3) << 13)
|
|
|
|
/* RATIO_CTRL */
|
|
#define RKVPSS_RATIO_EN BIT(0)
|
|
|
|
/* RATIO_UPDATE */
|
|
#define RKVPSS_RATIO_FORCE_UPD BIT(4)
|
|
#define RKVPSS_RATIO_GEN_UPD BIT(5)
|
|
|
|
/* SCALE_CTRL */
|
|
#define RKVPSS_SCL_HY_EN BIT(0)
|
|
#define RKVPSS_SCL_HC_EN BIT(1)
|
|
#define RKVPSS_SCL_VY_EN BIT(2)
|
|
#define RKVPSS_SCL_VC_EN BIT(3)
|
|
#define RKVPSS_SCL_CLIP_EN BIT(13)
|
|
#define RKVPSS_SCL_IN_CLIP_EN BIT(14)
|
|
#define RKVPSS_SCL_422TO420_EN BIT(30)
|
|
#define RKVPSS_SCL_YUV420_REAL_EN BIT(31)
|
|
|
|
/* SCALE_UPDATE */
|
|
#define RKVPSS_SCL_FORCE_UPD BIT(4)
|
|
#define RKVPSS_SCL_GEN_UPD BIT(5)
|
|
|
|
/* MI_WR_CTRL */
|
|
#define RKVPSS_MI_WR_INIT_BASE_EN BIT(4)
|
|
#define RKVPSS_MI_WR_UV_SWAP BIT(5)
|
|
#define RKVPSS_MI_WR_TILE_SEL(x) (((x) & 0x3) << 8)
|
|
#define RKVPSS_MI_WR_STRIDE_CFG_DIS BIT(15)
|
|
#define RKVPSS_MI_WR_GROUP_MODE(x) (((x) & 0x3) << 16)
|
|
#define RKVPSS_MI_WR_BURST4_LEN_LUM 0
|
|
#define RKVPSS_MI_WR_BURST8_LEN_LUM BIT(20)
|
|
#define RKVPSS_MI_WR_BURST16_LEN_LUM BIT(21)
|
|
#define RKVPSS_MI_WR_BURST4_LEN_CHROM 0
|
|
#define RKVPSS_MI_WR_BURST8_LEN_CHROM BIT(22)
|
|
#define RKVPSS_MI_WR_BURST16_LEN_CHROM BIT(23)
|
|
#define RKVPSS_MI_WR_ISP_PRIOR_DIS BIT(24)
|
|
#define RKVPSS_MI_WR_GLB_EN_DIS BIT(25)
|
|
#define RKVPSS_MI_ID_POLL_CLR BIT(26)
|
|
#define RKVPSS_MI_WR_ID_POLL_DIS BIT(27)
|
|
#define RKVPSS_MI_WR_GROUP_FIX BIT(28)
|
|
#define RKVPSS_MI_WR_ALIGN_DIS BIT(29)
|
|
#define RKVPSS_MI_PATH_SEL_FIX_DIS BIT(30)
|
|
#define RKVPSS_MI_NEW_WR_BURST_DIS BIT(31)
|
|
|
|
/* MI_FORCE_UPDATE */
|
|
#define RKVPSS_MI_FORCE_UPD BIT(0)
|
|
#define RKVPSS_MI_UPD_NEW_MODE BIT(1)
|
|
#define RKVPSS_MI_CHN0_FORCE_UPD BIT(4)
|
|
#define RKVPSS_MI_CHN1_FORCE_UPD BIT(5)
|
|
#define RKVPSS_MI_CHN2_FORCE_UPD BIT(6)
|
|
#define RKVPSS_MI_CHN3_FORCE_UPD BIT(7)
|
|
#define RKVPSS_MI_FORCE_PRO_DIS BIT(31)
|
|
|
|
/* MI_WR_WRAP_CTRL */
|
|
#define RKVPSS_MI_CHN_INIT_OFFSET_EN(x) (1 << (x))
|
|
#define RKVPSS_MI_CHN_DYNAMIC_UPD_ADDR(x) (BIT(8) << (x))
|
|
#define RKVPSS_MI_CHN_FRMEND_UPD_DIS(x) (BIT(24) << (x))
|
|
|
|
/* MI_WR_VFLIP_CTRL */
|
|
#define RKVPSS_MI_CHN_V_FLIP(x) (1 << (x))
|
|
|
|
/* MI_HURRY_CTRL */
|
|
#define RKVPSS_NOC_HURRY_VAL(x) ((x) & 0x7)
|
|
|
|
/* MI_ARQOS_CTRL */
|
|
#define RKVPSS_AR_QOS_EN BIT(0)
|
|
#define RKVPSS_AR_MMU_QOS(x) (((x) & 0x7) << 4)
|
|
#define RKVPSS_AR_YUV_QOS2(x) (((x) & 0x7) << 8)
|
|
#define RKVPSS_AR_YUV_QOS1(x) (((x) & 0x7) << 12)
|
|
|
|
/* MI_AWQOS_CTRL */
|
|
#define RKVPSS_AW_QOS_EN BIT(0)
|
|
#define RKVPSS_AW_YUV_QOS2(x) (((x) & 0x7) << 8)
|
|
#define RKVPSS_AW_YUV_QOS1(x) (((x) & 0x7) << 12)
|
|
|
|
/* MI_IMSC */
|
|
#define RKVPSS_MI_CHN0_FRM_END BIT(0)
|
|
#define RKVPSS_MI_CHN1_FRM_END BIT(1)
|
|
#define RKVPSS_MI_CHN2_FRM_END BIT(2)
|
|
#define RKVPSS_MI_CHN3_FRM_END BIT(3)
|
|
#define RKVPSS_MI_RD_FRM_END BIT(4)
|
|
#define RKVPSS_MI_WRAP_CHN0_Y BIT(8)
|
|
#define RKVPSS_MI_WRAP_CHN0_CB BIT(9)
|
|
#define RKVPSS_MI_WRAP_CHN1_Y BIT(10)
|
|
#define RKVPSS_MI_WRAP_CHN1_CB BIT(11)
|
|
#define RKVPSS_MI_WRAP_CHN2_Y BIT(12)
|
|
#define RKVPSS_MI_WRAP_CHN2_CB BIT(13)
|
|
#define RKVPSS_MI_WRAP_CHN3_Y BIT(14)
|
|
#define RKVPSS_MI_WRAP_CHN3_CB BIT(15)
|
|
#define RKVPSS_MI_BUS_ERR BIT(28)
|
|
#define RKVPSS_ISP2CHN_FRM_END BIT(30)
|
|
#define RKVPSS_MI_ALL_FRM_END BIT(31)
|
|
|
|
/* MI_RD_CTRL */
|
|
#define RKVPSS_MI_RD_INPUT_MASK GENMASK(2, 0)
|
|
#define RKVPSS_MI_RD_INPUT_420SP 1
|
|
#define RKVPSS_MI_RD_INPUT_422SP 2
|
|
#define RKVPSS_MI_RD_INPUT_BGR565 4
|
|
#define RKVPSS_MI_RD_INPUT_ABGR888 6
|
|
#define RKVPSS_MI_RD_INPUT_BGR888 7
|
|
#define RKVPSS_MI_RD_UV_SWAP BIT(4)
|
|
#define RKVPSS_MI_RD_RB_SWAP BIT(5)
|
|
#define RKVPSS_MI_RD_ALPHA_SWAP BIT(6)
|
|
#define RKVPSS_MI_RD_R2Y_UV_SEL BIT(7)
|
|
#define RKVPSS_MI_RD_MODE(x) (((x) & 0x3) << 8)
|
|
#define RKVPSS_MI_RD_ROT_0 0
|
|
#define RKVPSS_MI_RD_ROT_90 BIT(10)
|
|
#define RKVPSS_MI_RD_ROT_180 BIT(11)
|
|
#define RKVPSS_MI_RD_ROT_270 (BIT(10) | BIT(11))
|
|
#define RKVPSS_MI_RD_GROUP_MODE(x) (((x) & 0x3) << 16)
|
|
#define RKVPSS_MI_RD_BURST4_LEN 0
|
|
#define RKVPSS_MI_RD_BURST8_LEN BIT(20)
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#define RKVPSS_MI_RD_BURST16_LEN (BIT(20) | BIT(21))
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#define RKVPSS_MI_RD_FBCD_YUV444_EN BIT(26)
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#define RKVPSS_MI_RD_FBCD_OPT_DIS BIT(27)
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#define RKVPSS_MI_RD_R2Y_BYPASS BIT(28)
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#define RKVPSS_MI_RD_OLD BIT(30)
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#define RKVPSS_MI_RD_NEW_BURST_DIS BIT(31)
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/* MI_RD_INIT */
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#define RKVPSS_MI_RD_FORCE_UPD BIT(4)
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/* MI_RD_START */
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#define RKVPSS_MI_RD_ST BIT(0)
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/* AXI_CFG_RD_CTRL */
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#define RKVPSS_AXI_CFG_RD_ST BIT(0)
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#define RKVPSS_AXI_CFG_RD_ST_MODE BIT(1)
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#define RKVPSS_AXI_CFG_RD_CLEAR BIT(4)
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#define RKVPSS_AXI_CFG_RD_DIS BIT(7)
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#define RKVPSS_AXI_CFG_MIGHT_FAIL BIT(30)
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#define RKVPSS_AXI_CFG_RD_DONE BIT(31)
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/* MI_CHN_WR_CTRL */
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#define RKVPSS_MI_CHN_WR_EN BIT(0)
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#define RKVPSS_MI_CHN_WR_AUTO_UPD BIT(1)
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#define RKVPSS_MI_CHN_WR_RB_SWAP BIT(2)
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#define RKVPSS_MI_CHN_WR_42XSP BIT(4)
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#define RKVPSS_MI_CHN_WR_422P BIT(5)
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#define RKVPSS_MI_CHN_WR_OUTPUT_RGB888 (7 << 8)
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#define RKVPSS_MI_CHN_WR_OUTPUT_ARGB888 (6 << 8)
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#define RKVPSS_MI_CHN_WR_OUTPUT_RGB565 (4 << 8)
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#define RKVPSS_MI_CHN_WR_OUTPUT_YUV422 (2 << 8)
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#define RKVPSS_MI_CHN_WR_OUTPUT_YUV420 BIT(8)
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#define RKVPSS_MI_CHN_WR_OUTPUT_YUV400 0
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#define RKVPSS_MI_CHN_WORKING BIT(31)
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#define IS_SYNC_REG(x) ({ \
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typeof(x) __x = (x); \
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(__x == RKVPSS_VPSS_CTRL || __x == RKVPSS_VPSS_ONLINE || \
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__x == RKVPSS_VPSS_UPDATE || __x == RKVPSS_VPSS_CLK_GATE || \
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__x == RKVPSS_VPSS_IMSC || __x == RKVPSS_MI_WR_CTRL || \
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__x == RKVPSS_MI_WR_INIT || __x == RKVPSS_MI_WR_WRAP_CTRL || \
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__x == RKVPSS_MI_WR_VFLIP_CTRL); \
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})
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#endif
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