497 lines
19 KiB
C
497 lines
19 KiB
C
/*
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* Rockchip isp1 driver
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*
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* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <media/v4l2-common.h>
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#include <linux/rk-camera-module.h>
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#include "regs.h"
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void rkisp_disable_dcrop(struct rkisp_stream *stream, bool async)
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{
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struct rkisp_device *dev = stream->ispdev;
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u32 mask = stream->config->dual_crop.yuvmode_mask |
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stream->config->dual_crop.rawmode_mask;
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u32 val = CIF_DUAL_CROP_CFG_UPD;
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if (async && dev->hw_dev->is_single)
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val = CIF_DUAL_CROP_GEN_CFG_UPD;
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rkisp_unite_set_bits(dev, stream->config->dual_crop.ctrl, mask, val, false);
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}
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void rkisp_config_dcrop(struct rkisp_stream *stream,
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struct v4l2_rect *rect, bool async)
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{
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struct rkisp_device *dev = stream->ispdev;
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u32 val = stream->config->dual_crop.yuvmode_mask;
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struct v4l2_rect tmp = *rect;
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u32 reg;
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if (dev->unite_div > ISP_UNITE_DIV1) {
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tmp.width /= 2;
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if (stream->id == RKISP_STREAM_FBC)
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tmp.width &= ~0xf;
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}
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reg = stream->config->dual_crop.h_offset;
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rkisp_write(dev, reg, tmp.left, false);
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reg = stream->config->dual_crop.h_size;
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rkisp_write(dev, reg, tmp.width, false);
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if (dev->unite_div == ISP_UNITE_DIV4)
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tmp.height /= 2;
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reg = stream->config->dual_crop.v_offset;
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rkisp_unite_write(dev, reg, tmp.top, false);
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reg = stream->config->dual_crop.v_size;
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rkisp_unite_write(dev, reg, tmp.height, false);
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if (async && dev->hw_dev->is_single)
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val |= CIF_DUAL_CROP_GEN_CFG_UPD;
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else
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val |= CIF_DUAL_CROP_CFG_UPD;
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if (dev->unite_div > ISP_UNITE_DIV1) {
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u32 right_w, left_w = tmp.width;
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reg = stream->config->dual_crop.h_offset;
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rkisp_idx_write(dev, reg, RKMOUDLE_UNITE_EXTEND_PIXEL, ISP_UNITE_RIGHT, false);
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reg = stream->config->dual_crop.h_size;
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right_w = rect->width - left_w;
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rkisp_idx_write(dev, reg, right_w, ISP_UNITE_RIGHT, false);
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reg = stream->config->dual_crop.ctrl;
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rkisp_idx_set_bits(dev, reg, 0, val, ISP_UNITE_RIGHT, false);
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/* output with scale */
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if (stream->out_fmt.width < rect->width) {
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left_w += RKMOUDLE_UNITE_EXTEND_PIXEL;
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reg = stream->config->dual_crop.h_size;
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rkisp_idx_write(dev, reg, left_w, ISP_UNITE_LEFT, false);
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}
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v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
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"left dcrop (%d, %d) %dx%d\n",
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tmp.left, tmp.top, left_w, tmp.height);
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v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
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"right dcrop (%d, %d) %dx%d\n",
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RKMOUDLE_UNITE_EXTEND_PIXEL, tmp.top, right_w, tmp.height);
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}
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if (dev->unite_div == ISP_UNITE_DIV4) {
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reg = stream->config->dual_crop.h_offset;
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rkisp_idx_write(dev, reg, tmp.left, ISP_UNITE_LEFT_B, false);
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rkisp_idx_write(dev, reg, RKMOUDLE_UNITE_EXTEND_PIXEL, ISP_UNITE_RIGHT_B, false);
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reg = stream->config->dual_crop.h_size;
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rkisp_idx_write(dev, reg, tmp.width, ISP_UNITE_LEFT_B, false);
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rkisp_idx_write(dev, reg, tmp.width, ISP_UNITE_RIGHT_B, false);
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reg = stream->config->dual_crop.v_offset;
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rkisp_idx_write(dev, reg, RKMOUDLE_UNITE_EXTEND_PIXEL, ISP_UNITE_LEFT_B, false);
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rkisp_idx_write(dev, reg, RKMOUDLE_UNITE_EXTEND_PIXEL, ISP_UNITE_RIGHT_B, false);
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reg = stream->config->dual_crop.ctrl;
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rkisp_idx_set_bits(dev, reg, 0, val, ISP_UNITE_LEFT_B, false);
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rkisp_idx_set_bits(dev, reg, 0, val, ISP_UNITE_RIGHT_B, false);
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}
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if (val) {
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reg = stream->config->dual_crop.ctrl;
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rkisp_set_bits(dev, reg, 0, val, false);
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}
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}
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void rkisp_dump_rsz_regs(struct rkisp_stream *stream)
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{
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struct rkisp_device *dev = stream->ispdev;
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pr_info("RSZ_CTRL 0x%08x/0x%08x\n"
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"RSZ_SCALE_HY %d/%d\n"
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"RSZ_SCALE_HCB %d/%d\n"
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"RSZ_SCALE_HCR %d/%d\n"
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"RSZ_SCALE_VY %d/%d\n"
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"RSZ_SCALE_VC %d/%d\n"
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"RSZ_PHASE_HY %d/%d\n"
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"RSZ_PHASE_HC %d/%d\n"
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"RSZ_PHASE_VY %d/%d\n"
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"RSZ_PHASE_VC %d/%d\n",
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rkisp_read(dev, stream->config->rsz.ctrl, false),
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rkisp_read(dev, stream->config->rsz.ctrl_shd, true),
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rkisp_read(dev, stream->config->rsz.scale_hy, false),
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rkisp_read(dev, stream->config->rsz.scale_hy_shd, true),
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rkisp_read(dev, stream->config->rsz.scale_hcb, false),
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rkisp_read(dev, stream->config->rsz.scale_hcb_shd, true),
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rkisp_read(dev, stream->config->rsz.scale_hcr, false),
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rkisp_read(dev, stream->config->rsz.scale_hcr_shd, true),
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rkisp_read(dev, stream->config->rsz.scale_vy, false),
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rkisp_read(dev, stream->config->rsz.scale_vy_shd, true),
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rkisp_read(dev, stream->config->rsz.scale_vc, false),
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rkisp_read(dev, stream->config->rsz.scale_vc_shd, true),
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rkisp_read(dev, stream->config->rsz.phase_hy, false),
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rkisp_read(dev, stream->config->rsz.phase_hy_shd, true),
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rkisp_read(dev, stream->config->rsz.phase_hc, false),
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rkisp_read(dev, stream->config->rsz.phase_hc_shd, true),
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rkisp_read(dev, stream->config->rsz.phase_vy, false),
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rkisp_read(dev, stream->config->rsz.phase_vy_shd, true),
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rkisp_read(dev, stream->config->rsz.phase_vc, false),
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rkisp_read(dev, stream->config->rsz.phase_vc_shd, true));
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}
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static void update_rsz_shadow(struct rkisp_stream *stream, bool async)
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{
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struct rkisp_device *dev = stream->ispdev;
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u32 val = CIF_RSZ_CTRL_CFG_UPD;
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if (async && dev->hw_dev->is_single)
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val = CIF_RSZ_CTRL_CFG_UPD_AUTO;
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rkisp_unite_set_bits(dev, stream->config->rsz.ctrl, 0, val, false);
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}
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static void set_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y,
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struct v4l2_rect *in_c, struct v4l2_rect *out_y,
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struct v4l2_rect *out_c)
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{
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struct rkisp_device *dev = stream->ispdev;
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u32 scale_hy_addr = stream->config->rsz.scale_hy;
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u32 scale_hcr_addr = stream->config->rsz.scale_hcr;
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u32 scale_hcb_addr = stream->config->rsz.scale_hcb;
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u32 scale_vy_addr = stream->config->rsz.scale_vy;
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u32 scale_vc_addr = stream->config->rsz.scale_vc;
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u32 rsz_ctrl_addr = stream->config->rsz.ctrl;
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u32 scale_hy = 1, scale_hc = 1, scale_vy = 1, scale_vc = 1;
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u32 rsz_ctrl = 0;
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if (in_y->width < out_y->width) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HY_ENABLE |
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CIF_RSZ_CTRL_SCALE_HY_UP;
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scale_hy = ((in_y->width - 1) * CIF_RSZ_SCALER_FACTOR) /
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(out_y->width - 1);
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rkisp_write(dev, scale_hy_addr, scale_hy, false);
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} else if (in_y->width > out_y->width) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HY_ENABLE;
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scale_hy = ((out_y->width - 1) * CIF_RSZ_SCALER_FACTOR) /
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(in_y->width - 1) + 1;
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rkisp_write(dev, scale_hy_addr, scale_hy, false);
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}
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if (in_c->width < out_c->width) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HC_ENABLE |
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CIF_RSZ_CTRL_SCALE_HC_UP;
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scale_hc = ((in_c->width - 1) * CIF_RSZ_SCALER_FACTOR) /
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(out_c->width - 1);
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rkisp_write(dev, scale_hcb_addr, scale_hc, false);
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rkisp_write(dev, scale_hcr_addr, scale_hc, false);
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} else if (in_c->width > out_c->width) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HC_ENABLE;
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scale_hc = ((out_c->width - 1) * CIF_RSZ_SCALER_FACTOR) /
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(in_c->width - 1) + 1;
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rkisp_write(dev, scale_hcb_addr, scale_hc, false);
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rkisp_write(dev, scale_hcr_addr, scale_hc, false);
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}
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if (in_y->height < out_y->height) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VY_ENABLE |
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CIF_RSZ_CTRL_SCALE_VY_UP;
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scale_vy = ((in_y->height - 1) * CIF_RSZ_SCALER_FACTOR) /
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(out_y->height - 1);
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rkisp_write(dev, scale_vy_addr, scale_vy, false);
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} else if (in_y->height > out_y->height) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VY_ENABLE;
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scale_vy = ((out_y->height - 1) * CIF_RSZ_SCALER_FACTOR) /
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(in_y->height - 1) + 1;
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rkisp_write(dev, scale_vy_addr, scale_vy, false);
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}
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if (in_c->height < out_c->height) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VC_ENABLE |
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CIF_RSZ_CTRL_SCALE_VC_UP;
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scale_vc = ((in_c->height - 1) * CIF_RSZ_SCALER_FACTOR) /
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(out_c->height - 1);
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rkisp_write(dev, scale_vc_addr, scale_vc, false);
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} else if (in_c->height > out_c->height) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VC_ENABLE;
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scale_vc = ((out_c->height - 1) * CIF_RSZ_SCALER_FACTOR) /
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(in_c->height - 1) + 1;
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rkisp_write(dev, scale_vc_addr, scale_vc, false);
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}
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if (dev->unite_div > ISP_UNITE_DIV1) {
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u32 hy_size_reg, hc_size_reg, hy_offs_mi_reg, hc_offs_mi_reg, in_crop_offs_reg;
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u32 isp_in_w = in_y->width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
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u32 scl_w = out_y->width / 2;
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u32 left_y = scale_hy == 1 ? scl_w : DIV_ROUND_UP(scl_w * 65536, scale_hy);
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u32 left_c = scale_hc == 1 ? scl_w / 2 : DIV_ROUND_UP(scl_w * 65536 / 2, scale_hc);
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u32 phase_src_y = left_y * scale_hy;
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u32 phase_dst_y = scl_w * 65536;
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u32 phase_left_y = scale_hy == 1 ? 0 : scale_hy - (phase_src_y - phase_dst_y);
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u32 phase_src_c = left_c * scale_hc;
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u32 phase_dst_c = scl_w * 65536 / 2;
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u32 phase_left_c = scale_hc == 1 ? 0 : scale_hc - (phase_src_c - phase_dst_c);
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u32 right_y = phase_left_y ? in_y->width - (left_y - 1) : in_y->width - left_y;
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u32 right_c = phase_left_c ? in_y->width - (left_c - 1) * 2 : in_y->width - left_c * 2;
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u32 right_crop_y = isp_in_w - right_y;
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u32 right_crop_c = isp_in_w - right_c;
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u32 extend = RKMOUDLE_UNITE_EXTEND_PIXEL;
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u32 right_scl_in_y;
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u32 right_scl_in_c;
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switch (stream->id) {
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case RKISP_STREAM_MP:
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hy_size_reg = ISP3X_MAIN_RESIZE_HY_SIZE;
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hc_size_reg = ISP3X_MAIN_RESIZE_HC_SIZE;
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hy_offs_mi_reg = ISP3X_MAIN_RESIZE_HY_OFFS_MI;
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hc_offs_mi_reg = ISP3X_MAIN_RESIZE_HC_OFFS_MI;
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in_crop_offs_reg = ISP3X_MAIN_RESIZE_IN_CROP_OFFSET;
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break;
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case RKISP_STREAM_SP:
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hy_size_reg = ISP3X_SELF_RESIZE_HY_SIZE;
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hc_size_reg = ISP3X_SELF_RESIZE_HC_SIZE;
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hy_offs_mi_reg = ISP3X_SELF_RESIZE_HY_OFFS_MI;
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hc_offs_mi_reg = ISP3X_SELF_RESIZE_HC_OFFS_MI;
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in_crop_offs_reg = ISP3X_SELF_RESIZE_IN_CROP_OFFSET;
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break;
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case RKISP_STREAM_BP:
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hy_size_reg = ISP32_BP_RESIZE_HY_SIZE;
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hc_size_reg = ISP32_BP_RESIZE_HC_SIZE;
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hy_offs_mi_reg = ISP32_BP_RESIZE_HY_OFFS_MI;
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hc_offs_mi_reg = ISP32_BP_RESIZE_HC_OFFS_MI;
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in_crop_offs_reg = ISP32_BP_RESIZE_IN_CROP_OFFSET;
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break;
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default:
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v4l2_warn(&dev->v4l2_dev, "%s no support unite for stream:%d\n",
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__func__, stream->id);
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return;
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}
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if (right_crop_y < RKMOUDLE_UNITE_EXTEND_PIXEL) {
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u32 reg;
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extend = right_crop_y & ~0x1;
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reg = stream->config->dual_crop.h_offset;
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rkisp_idx_write(dev, reg, extend, ISP_UNITE_RIGHT, false);
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reg = stream->config->dual_crop.h_size;
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rkisp_idx_write(dev, reg, isp_in_w - extend, ISP_UNITE_RIGHT, false);
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reg = stream->config->dual_crop.ctrl;
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rkisp_idx_write(dev, reg,
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rkisp_idx_read_reg_cache(dev, reg, ISP_UNITE_RIGHT),
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ISP_UNITE_RIGHT, false);
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}
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right_scl_in_y = right_crop_y - extend;
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right_scl_in_c = right_crop_c - extend;
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/* left isp */
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rkisp_write(dev, hy_size_reg, scl_w, false);
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rkisp_write(dev, hc_size_reg, scl_w, false);
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rkisp_write(dev, hy_offs_mi_reg, 0, false);
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rkisp_write(dev, hc_offs_mi_reg, 0, false);
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rkisp_write(dev, in_crop_offs_reg, 0, false);
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/* right isp */
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rkisp_idx_write(dev, hy_size_reg, scl_w, ISP_UNITE_RIGHT, false);
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rkisp_idx_write(dev, hc_size_reg, scl_w, ISP_UNITE_RIGHT, false);
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rkisp_idx_write(dev, scale_hy_addr, scale_hy, ISP_UNITE_RIGHT, false);
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rkisp_idx_write(dev, scale_hcb_addr, scale_hc, ISP_UNITE_RIGHT, false);
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rkisp_idx_write(dev, scale_hcr_addr, scale_hc, ISP_UNITE_RIGHT, false);
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rkisp_idx_write(dev, scale_vy_addr, scale_vy, ISP_UNITE_RIGHT, false);
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rkisp_idx_write(dev, scale_vc_addr, scale_vc, ISP_UNITE_RIGHT, false);
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rkisp_idx_write(dev, stream->config->rsz.phase_hy, phase_left_y, ISP_UNITE_RIGHT, false);
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rkisp_idx_write(dev, stream->config->rsz.phase_hc, phase_left_c, ISP_UNITE_RIGHT, false);
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rkisp_idx_write(dev, stream->config->rsz.phase_vy, 0, ISP_UNITE_RIGHT, false);
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rkisp_idx_write(dev, stream->config->rsz.phase_vc, 0, ISP_UNITE_RIGHT, false);
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rkisp_idx_write(dev, hy_offs_mi_reg, scl_w & 15, ISP_UNITE_RIGHT, false);
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rkisp_idx_write(dev, hc_offs_mi_reg, scl_w & 15, ISP_UNITE_RIGHT, false);
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rkisp_idx_write(dev, in_crop_offs_reg,
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right_scl_in_c << 4 | right_scl_in_y, ISP_UNITE_RIGHT, false);
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rsz_ctrl |= ISP3X_SCL_CLIP_EN;
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rkisp_idx_write(dev, rsz_ctrl_addr,
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rsz_ctrl | ISP3X_SCL_HPHASE_EN | ISP3X_SCL_IN_CLIP_EN,
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ISP_UNITE_RIGHT, false);
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v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
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"scl:%dx%d, scl factor[hy:%d hc:%d vy:%d vc:%d]\n",
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scl_w, out_y->height, scale_hy, scale_hc, scale_vy, scale_vc);
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v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
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"scl_left size[y:%d c:%d] phase[y:%d c:%d]\n",
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left_y, left_c, phase_left_y, phase_left_c);
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v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
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"scl_right size[y:%d c:%d] offs_mi[y:%d c:%d] in_crop[y:%d c:%d]\n",
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right_y, right_c, scl_w & 15, scl_w & 15, right_scl_in_y, right_scl_in_c);
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}
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rkisp_write(dev, rsz_ctrl_addr, rsz_ctrl, false);
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}
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static void set_bilinear_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y,
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struct v4l2_rect *in_c, struct v4l2_rect *out_y,
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struct v4l2_rect *out_c, bool async)
|
|
{
|
|
struct rkisp_device *dev = stream->ispdev;
|
|
u32 rsz_ctrl = 0, hy = 1, hc = 1, reg, val, in_w, out_w;
|
|
bool is_avg = false;
|
|
|
|
in_w = in_y->width;
|
|
out_w = out_y->width;
|
|
if (dev->unite_div > ISP_UNITE_DIV1) {
|
|
in_w = in_y->width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
|
|
out_w /= 2;
|
|
}
|
|
val = in_w | in_y->height << 16;
|
|
reg = stream->config->rsz.src_size;
|
|
rkisp_unite_write(dev, reg, val, false);
|
|
val = out_w | out_y->height << 16;
|
|
reg = stream->config->rsz.dst_size;
|
|
rkisp_unite_write(dev, reg, val, false);
|
|
|
|
if (in_y->width != out_y->width) {
|
|
rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HY_ENABLE | CIF_RSZ_CTRL_SCALE_HC_ENABLE;
|
|
if (is_avg) {
|
|
hy = ((out_y->width - 1) * ISP32_SCALE_AVE_FACTOR) / (in_y->width - 1) + 1;
|
|
hc = ((out_c->width - 1) * ISP32_SCALE_AVE_FACTOR) / (in_c->width - 1) + 1;
|
|
rsz_ctrl |= ISP32_SCALE_AVG_H_EN;
|
|
} else {
|
|
hy = ((in_y->width - 1) * ISP32_SCALE_BIL_FACTOR) / (out_y->width - 1);
|
|
hc = ((in_c->width - 1) * ISP32_SCALE_BIL_FACTOR) / (out_c->width - 1);
|
|
}
|
|
reg = stream->config->rsz.scale_hy;
|
|
rkisp_unite_write(dev, reg, hy, false);
|
|
reg = stream->config->rsz.scale_hcr;
|
|
rkisp_unite_write(dev, reg, hc, false);
|
|
}
|
|
|
|
if (in_y->height != out_y->height) {
|
|
rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VY_ENABLE | CIF_RSZ_CTRL_SCALE_VC_ENABLE;
|
|
if (is_avg) {
|
|
val = ((out_y->height - 1) * ISP32_SCALE_AVE_FACTOR) / (in_y->height - 1) + 1;
|
|
rsz_ctrl |= ISP32_SCALE_AVG_V_EN;
|
|
} else {
|
|
val = ((in_y->height - 1) * ISP32_SCALE_BIL_FACTOR) / (out_y->height - 1);
|
|
}
|
|
reg = stream->config->rsz.scale_vy;
|
|
rkisp_unite_write(dev, reg, val, false);
|
|
reg = stream->config->rsz.scale_vc;
|
|
rkisp_unite_write(dev, reg, val, false);
|
|
}
|
|
|
|
if (dev->unite_div > ISP_UNITE_DIV1) {
|
|
u32 right_fst_point_y = out_w * hy;
|
|
u32 right_fst_point_c = out_w / 2 * hc;
|
|
u32 left_in_used_size_y = right_fst_point_y / ISP32_SCALE_BIL_FACTOR;
|
|
u32 left_in_used_size_c = right_fst_point_c / ISP32_SCALE_BIL_FACTOR * 2;
|
|
u32 phase_left_y = right_fst_point_y & 0xfff;
|
|
u32 phase_left_c = right_fst_point_c & 0xfff;
|
|
u32 right_scl_need_size_y = in_y->width - left_in_used_size_y;
|
|
u32 right_scl_need_size_c = in_y->width - left_in_used_size_c;
|
|
u32 right_scl_in_size_y = in_w - right_scl_need_size_y;
|
|
u32 right_scl_in_size_c = in_w - right_scl_need_size_c;
|
|
u32 scl_in_hy_offs = right_scl_in_size_y - RKMOUDLE_UNITE_EXTEND_PIXEL;
|
|
u32 scl_in_hc_offs = right_scl_in_size_c - RKMOUDLE_UNITE_EXTEND_PIXEL;
|
|
|
|
/* left isp */
|
|
reg = stream->config->rsz.scale_hy_offs;
|
|
rkisp_idx_write(dev, reg, 0, ISP_UNITE_LEFT, false);
|
|
reg = stream->config->rsz.scale_hc_offs;
|
|
rkisp_idx_write(dev, reg, 0, ISP_UNITE_LEFT, false);
|
|
reg = stream->config->rsz.scale_hy_offs_mi;
|
|
rkisp_idx_write(dev, reg, 0, ISP_UNITE_LEFT, false);
|
|
reg = stream->config->rsz.scale_hc_offs_mi;
|
|
rkisp_idx_write(dev, reg, 0, ISP_UNITE_LEFT, false);
|
|
reg = stream->config->rsz.scale_in_crop_offs;
|
|
rkisp_idx_write(dev, reg, 0, ISP_UNITE_LEFT, false);
|
|
reg = stream->config->rsz.scale_hy_size;
|
|
rkisp_idx_write(dev, reg, out_w, ISP_UNITE_LEFT, false);
|
|
reg = stream->config->rsz.scale_hc_size;
|
|
rkisp_idx_write(dev, reg, out_w, ISP_UNITE_LEFT, false);
|
|
/* right isp */
|
|
reg = stream->config->rsz.scale_hy_size;
|
|
rkisp_idx_write(dev, reg, out_w, ISP_UNITE_RIGHT, false);
|
|
reg = stream->config->rsz.scale_hc_size;
|
|
rkisp_idx_write(dev, reg, out_w, ISP_UNITE_RIGHT, false);
|
|
reg = stream->config->rsz.scale_hy_offs;
|
|
rkisp_idx_write(dev, reg, phase_left_y, ISP_UNITE_RIGHT, false);
|
|
reg = stream->config->rsz.scale_hc_offs;
|
|
rkisp_idx_write(dev, reg, phase_left_c, ISP_UNITE_RIGHT, false);
|
|
reg = stream->config->rsz.scale_hy_offs_mi;
|
|
rkisp_idx_write(dev, reg, out_w & 15, ISP_UNITE_RIGHT, false);
|
|
reg = stream->config->rsz.scale_hc_offs_mi;
|
|
rkisp_idx_write(dev, reg, out_w & 15, ISP_UNITE_RIGHT, false);
|
|
reg = stream->config->rsz.scale_in_crop_offs;
|
|
val = scl_in_hc_offs << 4 | scl_in_hy_offs;
|
|
rkisp_idx_write(dev, reg, val, ISP_UNITE_RIGHT, false);
|
|
|
|
rsz_ctrl |= ISP32_SCL_CLIP_EN;
|
|
reg = stream->config->rsz.ctrl;
|
|
rkisp_idx_write(dev, reg, rsz_ctrl | ISP32_SCL_IN_CLIP_EN,
|
|
ISP_UNITE_RIGHT, false);
|
|
}
|
|
|
|
reg = stream->config->rsz.ctrl;
|
|
rkisp_write(dev, reg, rsz_ctrl, false);
|
|
val = ISP32_SCALE_FORCE_UPD | ISP32_SCALE_GEN_UPD;
|
|
if (async && dev->hw_dev->is_single)
|
|
val = ISP32_SCALE_GEN_UPD;
|
|
reg = stream->config->rsz.update;
|
|
rkisp_write(dev, reg, val, false);
|
|
}
|
|
|
|
void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y,
|
|
struct v4l2_rect *in_c, struct v4l2_rect *out_y,
|
|
struct v4l2_rect *out_c, bool async)
|
|
{
|
|
struct rkisp_device *dev = stream->ispdev;
|
|
int i = 0;
|
|
|
|
if (dev->isp_ver == ISP_V39 || dev->isp_ver == ISP_V33 ||
|
|
(dev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP)) {
|
|
set_bilinear_scale(stream, in_y, in_c, out_y, out_c, async);
|
|
return;
|
|
}
|
|
|
|
/* No phase offset */
|
|
rkisp_unite_write(dev, stream->config->rsz.phase_hy, 0, true);
|
|
rkisp_unite_write(dev, stream->config->rsz.phase_hc, 0, true);
|
|
rkisp_unite_write(dev, stream->config->rsz.phase_vy, 0, true);
|
|
rkisp_unite_write(dev, stream->config->rsz.phase_vc, 0, true);
|
|
|
|
/* Linear interpolation */
|
|
for (i = 0; i < 64; i++) {
|
|
rkisp_unite_write(dev, stream->config->rsz.scale_lut_addr, i, true);
|
|
rkisp_unite_write(dev, stream->config->rsz.scale_lut, i, true);
|
|
}
|
|
|
|
set_scale(stream, in_y, in_c, out_y, out_c);
|
|
|
|
update_rsz_shadow(stream, async);
|
|
}
|
|
|
|
void rkisp_disable_rsz(struct rkisp_stream *stream, bool async)
|
|
{
|
|
rkisp_unite_write(stream->ispdev, stream->config->rsz.ctrl, 0, false);
|
|
if (stream->ispdev->isp_ver == ISP_V39 ||
|
|
stream->ispdev->isp_ver == ISP_V33 ||
|
|
(stream->ispdev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP))
|
|
return;
|
|
update_rsz_shadow(stream, async);
|
|
}
|