5414 lines
266 KiB
C
5414 lines
266 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* ar2020 driver
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*
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* Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd.
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*
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* V0.0X01.0X00 first version.
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* V0.0X01.0X01 support conversion gain switch.
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* V0.0X01.0X02 add debug interface for conversion gain switch.
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* V0.0X01.0X03 support enum sensor fmt
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* V0.0X01.0X04 add quick stream on/off
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/sysfs.h>
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#include <linux/slab.h>
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#include <linux/version.h>
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#include <linux/rk-camera-module.h>
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#include <media/media-entity.h>
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#include <media/v4l2-async.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-subdev.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/rk-preisp.h>
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#include "../platform/rockchip/isp/rkisp_tb_helper.h"
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#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
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#ifndef V4L2_CID_DIGITAL_GAIN
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#define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
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#endif
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#define USE_8LANE 1
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#define LANE_NUM_8 8
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#define AR2020_BPP 10
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#define AR2020_LANES 4
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#define MIPI_FREQ_600M 600000000
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#define MIPI_FREQ_860M 860000000
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#define PIXEL_RATE_WITH_600M (MIPI_FREQ_600M / AR2020_BPP * 2 * AR2020_LANES)
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#define PIXEL_RATE_MAX (MIPI_FREQ_860M / AR2020_BPP * 2 * AR2020_LANES)
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#define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
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#define AR2020_XVCLK_FREQ_27M 27000000
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#define AR2020_XVCLK_FREQ_20M 20000000
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#define CHIP_ID 0x0653
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#define AR2020_REG_CHIP_ID 0x0016
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#define AR2020_REG_CTRL_MODE 0x0100
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#define AR2020_MODE_SW_STANDBY 0x0000
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#define AR2020_MODE_STREAMING 0x0001
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#define AR2020_EXPOSURE_MIN 2
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#define AR2020_EXPOSURE_STEP 1
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#define AR2020_VTS_MAX 0xffff
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#define AR2020_REG_EXP 0x0202
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#define AR2020_REG_EXP_T2 0x0224
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//needed be updated for different settings, FLL(REG 0x0342)-t1_to_t2_dist-1
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#define AR2020_CIT_MAX_T1 7498
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//needed be updated for different settings, t1_to_t2_dist(R0x3042[14:0])-4
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#define AR2020_CIT_MAX_T2 237
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#define AR2020_REG_GAIN 0x3062
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#define AR2020_REG_GAIN2 0x3062
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#define AR2020_GAIN_MIN 0
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#define AR2020_GAIN_MAX 127
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#define AR2020_GAIN_STEP 1
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#define AR2020_GAIN_DEFAULT 0x20
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#define AR2020_REG_VTS 0x0340
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/* make sure exposure and gain take effect from N+2 frame; open.k */
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#define AR2020_GROUP_UPDATE_ADDRESS 0x0104
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#define AR2020_GROUP_UPDATE_START_DATA 0x0001
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#define AR2020_GROUP_UPDATE_END_DATA 0x0000
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#define AR2020_SOFTWARE_RESET_REG 0x0103
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/* Flag address for I2C array write,indicate this is the last row of I2C register table; open.k */
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#define REG_NULL 0xFFFF
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#define REG_DELAY 0xFFFE
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#define AR2020_REG_VALUE_08BIT 1
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#define AR2020_REG_VALUE_16BIT 2
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#define AR2020_REG_VALUE_24BIT 3
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#define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
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#define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
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#define AR2020_NAME "ar2020"
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enum regmode {
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REG_MODE_DEFAULT = -1,
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INITIAL_STREAMING,
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SEPERATE_STREAMING,
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REG_MODE_MAX,
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};
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/* sensor power on config, need check power, MCLK, GPIO etc,,,
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* need go to .dts file to change the config;
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* open.k
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*/
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static const char * const ar2020_supply_names[] = {
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"avdd", /* Analog power */
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"dovdd", /* Digital I/O power */
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"dvdd", /* Digital core power */
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};
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#define AR2020_NUM_SUPPLIES ARRAY_SIZE(ar2020_supply_names)
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#define AR2020_FLIP_REG 0x0101
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#define MIRROR_BIT_MASK BIT(0)
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#define FLIP_BIT_MASK BIT(1)
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struct regval {
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u16 addr;
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u16 val;
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u8 bits;
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};
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/* Config resolution ,LLPCLK, FLL,
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* exposure time,fps, MIPI channel config, HDR mode ,
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* open.k
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*/
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struct ar2020_mode {
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u32 bus_fmt;
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u32 width;
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u32 height;
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struct v4l2_fract max_fps;
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u32 hts_def;
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u32 vts_def;
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u32 exp_def;
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const struct regval *reg_list;
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u32 hdr_mode;
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u32 mipi_freq;
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u32 mipi_rate;
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u32 mclk;
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u32 reg_mode;
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u32 vc[PAD_MAX];
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};
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struct ar2020 {
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struct i2c_client *client;
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struct clk *xvclk;
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struct gpio_desc *reset_gpio;
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struct gpio_desc *pwdn_gpio;
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struct regulator_bulk_data supplies[AR2020_NUM_SUPPLIES];
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_default;
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struct pinctrl_state *pins_sleep;
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struct v4l2_subdev subdev;
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struct media_pad pad;
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struct v4l2_ctrl_handler ctrl_handler;
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struct v4l2_ctrl *exposure;
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struct v4l2_ctrl *anal_gain;
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struct v4l2_ctrl *digi_gain;
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struct v4l2_ctrl *hblank;
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struct v4l2_ctrl *vblank;
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struct v4l2_ctrl *test_pattern;
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struct v4l2_ctrl *pixel_rate;
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struct v4l2_ctrl *link_freq;
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struct v4l2_ctrl *h_flip;
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struct v4l2_ctrl *v_flip;
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struct mutex mutex;
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bool streaming;
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bool power_on;
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const struct ar2020_mode *cur_mode;
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u32 cfg_num;
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u32 module_index;
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const char *module_facing;
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const char *module_name;
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struct rkmodule_multi_dev_info multi_dev_info;
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const char *len_name;
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bool has_init_exp;
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struct preisp_hdrae_exp_s init_hdrae_exp;
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bool long_hcg;
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bool middle_hcg;
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bool short_hcg;
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bool is_thunderboot;
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bool is_thunderboot_ng;
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bool is_first_streamoff;
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u8 flip;
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u32 cur_mclk;
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u32 csi_lanes_in_use;
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};
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#define to_ar2020(sd) container_of(sd, struct ar2020, subdev)
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static const struct regval ar2020_edr12bit_5120x3840_30fps_8lane_regs[] = {
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{REG_DELAY, 2000, AR2020_REG_VALUE_16BIT},
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{0x44D6, 0xF206, AR2020_REG_VALUE_16BIT},//DAC_LD_32_33
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{0x0100, 0x00, AR2020_REG_VALUE_08BIT},//MODE_SELECT
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{0x0304, 0x0006, AR2020_REG_VALUE_16BIT},//VT_PRE_PLL_CLK_DIV
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{0x0306, 0x00E5, AR2020_REG_VALUE_16BIT},//VT_PLL_MULTIPLIER
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{0x0300, 0x0006, AR2020_REG_VALUE_16BIT},//VT_PIX_CLK_DIV
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{0x0302, 0x0001, AR2020_REG_VALUE_16BIT},//VT_SYS_CLK_DIV
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{0x030C, 0x0007, AR2020_REG_VALUE_16BIT},//OP_PRE_PLL_CLK_DIV
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{0x030E, 0x01BD, AR2020_REG_VALUE_16BIT},//OP_PLL_MULTIPLIER
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{0x0308, 0x0006, AR2020_REG_VALUE_16BIT},//OP_PIX_CLK_DIV
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{0x030A, 0x0002, AR2020_REG_VALUE_16BIT},//OP_SYS_CLK_DIV
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{0x0344, 0x0008, AR2020_REG_VALUE_16BIT},//X_ADDR_START
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{0x0348, 0x1407, AR2020_REG_VALUE_16BIT},//X_ADDR_END
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{0x0346, 0x0008, AR2020_REG_VALUE_16BIT},//Y_ADDR_START
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{0x034A, 0x0F07, AR2020_REG_VALUE_16BIT},//Y_ADDR_END
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{0x034C, 0x1400, AR2020_REG_VALUE_16BIT},//X_OUTPUT_SIZE
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{0x034E, 0x0F00, AR2020_REG_VALUE_16BIT},//Y_OUTPUT_SIZE
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{0x0380, 0x0001, AR2020_REG_VALUE_16BIT},//X_EVEN_INC
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{0x0382, 0x0001, AR2020_REG_VALUE_16BIT},//X_ODD_INC
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{0x0384, 0x0001, AR2020_REG_VALUE_16BIT},//Y_EVEN_INC
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{0x0386, 0x0001, AR2020_REG_VALUE_16BIT},//Y_ODD_INC
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{0x0900, 0x00, AR2020_REG_VALUE_08BIT},//BINNING_MODE
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{0x0901, 0x11, AR2020_REG_VALUE_08BIT},//BINNING_TYPE
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{0x0342, 0x2E30, AR2020_REG_VALUE_16BIT},//LINE_LENGTH_PCK
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{0x0340, 0x0F1E, AR2020_REG_VALUE_16BIT},//FRAME_LENGTH_LINES
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{0x0202, 0x0D9E, AR2020_REG_VALUE_16BIT},//COARSE_INTEGRATION_TIME
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{0x0112, 0x0C0C, AR2020_REG_VALUE_16BIT},//CSI_DATA_FORMAT
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{0x0114, 0x07, AR2020_REG_VALUE_08BIT},//CSI_LANE_MODE
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{0x0800, 0x0D, AR2020_REG_VALUE_08BIT},//TCLK_POST
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{0x0801, 0x08, AR2020_REG_VALUE_08BIT},//THS_PREPARE
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{0x0802, 0x0E, AR2020_REG_VALUE_08BIT},//THS_ZERO_MIN
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{0x0803, 0x0A, AR2020_REG_VALUE_08BIT},//THS_TRAIL
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{0x0804, 0x0C, AR2020_REG_VALUE_08BIT},//TCLK_TRAIL_MIN
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{0x0805, 0x07, AR2020_REG_VALUE_08BIT},//TCLK_PREPARE
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{0x0806, 0x2B, AR2020_REG_VALUE_08BIT},//TCLK_ZERO
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{0x0807, 0x09, AR2020_REG_VALUE_08BIT},//TLPX
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{0x082A, 0x12, AR2020_REG_VALUE_08BIT},//TWAKEUP
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{0x082B, 0x0E, AR2020_REG_VALUE_08BIT},//TINIT
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{0x082C, 0x10, AR2020_REG_VALUE_08BIT},//THS_EXIT
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{0x3F06, 0x00C0, AR2020_REG_VALUE_16BIT},//MIPI_TIMING_2
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{0x3F0A, 0xA000, AR2020_REG_VALUE_16BIT},//MIPI_TIMING_4
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{0x3F0C, 0x000C, AR2020_REG_VALUE_16BIT},//MIPI_TIMING_5
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{0x3F20, 0x8080, AR2020_REG_VALUE_16BIT},//MIPI_PHY_TRIM_MSB
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{0x3F1E, 0x0004, AR2020_REG_VALUE_16BIT},//MIPI_PHY_TRIM_LSB
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{0x3f22, 0x3806, AR2020_REG_VALUE_16BIT},
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{0x3040, 0x0011, AR2020_REG_VALUE_16BIT},//READ_MODE
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{0x0220, 0x01, AR2020_REG_VALUE_08BIT},//HDR_MODE
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{0x3F18, 0x3B30, AR2020_REG_VALUE_16BIT},//MIPI_JPEG_PN9_DATA_TYPE
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{0x4000, 0x0114, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_00
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{0x4002, 0x1A25, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_02
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{0x4004, 0x3DFF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_04
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{0x4006, 0xFFFF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_06
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{0x4008, 0x0A35, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_08
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{0x400A, 0x10EF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_0A
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{0x400C, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_0C
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{0x400E, 0x30D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_0E
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{0x4010, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10
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{0x4012, 0xB5F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12
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{0x4014, 0x0085, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14
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{0x4016, 0xF004, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16
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{0x4018, 0x9A89, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18
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{0x401A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A
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{0x401C, 0x9997, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C
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{0x401E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E
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{0x4020, 0x30C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20
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{0x4022, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22
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{0x4024, 0x82F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24
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{0x4026, 0x0030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26
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{0x4028, 0x18F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28
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{0x402A, 0x0320, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A
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{0x402C, 0x58F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C
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{0x402E, 0x089C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E
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{0x4030, 0xF010, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30
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{0x4032, 0x99B6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32
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{0x4034, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34
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{0x4036, 0xB498, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36
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{0x4038, 0xA096, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38
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{0x403A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A
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{0x403C, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C
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{0x403E, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E
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{0x4040, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40
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{0x4042, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42
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{0x4044, 0x209D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44
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{0x4046, 0x8C08, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46
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{0x4048, 0x08F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48
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{0x404A, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A
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{0x404C, 0x008F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4C
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{0x404E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4E
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{0x4050, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_50
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{0x4052, 0x0488, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_52
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{0x4054, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_54
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{0x4056, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_56
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{0x4058, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_58
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{0x405A, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_5A
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{0x405C, 0x0290, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_5C
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{0x405E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_5E
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{0x4060, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_60
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{0x4062, 0x2EA3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_62
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{0x4064, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_64
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{0x4066, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_66
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{0x4068, 0x089D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_68
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{0x406A, 0xF075, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_6A
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{0x406C, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_6C
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{0x406E, 0x4070, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_6E
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{0x4070, 0x216D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_70
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{0x4072, 0x1CF6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_72
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{0x4074, 0x8B00, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_74
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{0x4076, 0x5186, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_76
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{0x4078, 0x1300, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_78
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{0x407A, 0x0205, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_7A
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{0x407C, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_7C
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{0x407E, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_7E
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{0x4080, 0x8387, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_80
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{0x4082, 0xF006, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_82
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{0x4084, 0x8702, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_84
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{0x4086, 0x0D02, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_86
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{0x4088, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_88
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{0x408A, 0x0383, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_8A
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{0x408C, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_8C
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{0x408E, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_8E
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{0x4090, 0x0213, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_90
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{0x4092, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_92
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{0x4094, 0xD887, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_94
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{0x4096, 0x020D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_96
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{0x4098, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_98
|
|
{0x409A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_9A
|
|
{0x409C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_9C
|
|
{0x409E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_9E
|
|
{0x40A0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A0
|
|
{0x40A2, 0x0401, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A2
|
|
{0x40A4, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A4
|
|
{0x40A6, 0x82F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A6
|
|
{0x40A8, 0x0883, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A8
|
|
{0x40AA, 0xF009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_AA
|
|
{0x40AC, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_AC
|
|
{0x40AE, 0x2985, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_AE
|
|
{0x40B0, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B0
|
|
{0x40B2, 0x2A87, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B2
|
|
{0x40B4, 0xF63E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B4
|
|
{0x40B6, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B6
|
|
{0x40B8, 0x0801, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B8
|
|
{0x40BA, 0x40F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_BA
|
|
{0x40BC, 0x0800, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_BC
|
|
{0x40BE, 0x48F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_BE
|
|
{0x40C0, 0x0882, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C0
|
|
{0x40C2, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C2
|
|
{0x40C4, 0x0401, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C4
|
|
{0x40C6, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C6
|
|
{0x40C8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C8
|
|
{0x40CA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_CA
|
|
{0x40CC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_CC
|
|
{0x40CE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_CE
|
|
{0x40D0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D0
|
|
{0x40D2, 0x0401, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D2
|
|
{0x40D4, 0xF015, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D4
|
|
{0x40D6, 0x002C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D6
|
|
{0x40D8, 0xF00E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D8
|
|
{0x40DA, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_DA
|
|
{0x40DC, 0x0687, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_DC
|
|
{0x40DE, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_DE
|
|
{0x40E0, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E0
|
|
{0x40E2, 0x61E8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E2
|
|
{0x40E4, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E4
|
|
{0x40E6, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E6
|
|
{0x40E8, 0x3480, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E8
|
|
{0x40EA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_EA
|
|
{0x40EC, 0x3240, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_EC
|
|
{0x40EE, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_EE
|
|
{0x40F0, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F0
|
|
{0x40F2, 0xF00E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F2
|
|
{0x40F4, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F4
|
|
{0x40F6, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F6
|
|
{0x40F8, 0x3240, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F8
|
|
{0x40FA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_FA
|
|
{0x40FC, 0x3480, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_FC
|
|
{0x40FE, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_FE
|
|
{0x4100, 0xC0E6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_100
|
|
{0x4102, 0xF004, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_102
|
|
{0x4104, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_104
|
|
{0x4106, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_106
|
|
{0x4108, 0xB0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_108
|
|
{0x410A, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10A
|
|
{0x410C, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10C
|
|
{0x410E, 0x86F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10E
|
|
{0x4110, 0x0086, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_110
|
|
{0x4112, 0xF089, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_112
|
|
{0x4114, 0xB0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_114
|
|
{0x4116, 0x00E9, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_116
|
|
{0x4118, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_118
|
|
{0x411A, 0x8AF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_11A
|
|
{0x411C, 0x0000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_11C
|
|
{0x411E, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_11E
|
|
{0x4120, 0x00E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_120
|
|
{0x4122, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_122
|
|
{0x4124, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_124
|
|
{0x4126, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_126
|
|
{0x4128, 0x0A35, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_128
|
|
{0x412A, 0x10EF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12A
|
|
{0x412C, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12C
|
|
{0x412E, 0x30D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12E
|
|
{0x4130, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_130
|
|
{0x4132, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_132
|
|
{0x4134, 0x049A, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_134
|
|
{0x4136, 0x89F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_136
|
|
{0x4138, 0x0099, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_138
|
|
{0x413A, 0x97F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_13A
|
|
{0x413C, 0x0030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_13C
|
|
{0x413E, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_13E
|
|
{0x4140, 0x0082, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_140
|
|
{0x4142, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_142
|
|
{0x4144, 0x3018, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_144
|
|
{0x4146, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_146
|
|
{0x4148, 0xB520, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_148
|
|
{0x414A, 0x58F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14A
|
|
{0x414C, 0x089C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14C
|
|
{0x414E, 0xF010, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14E
|
|
{0x4150, 0x99B6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_150
|
|
{0x4152, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_152
|
|
{0x4154, 0xB498, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_154
|
|
{0x4156, 0xA096, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_156
|
|
{0x4158, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_158
|
|
{0x415A, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_15A
|
|
{0x415C, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_15C
|
|
{0x415E, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_15E
|
|
{0x4160, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_160
|
|
{0x4162, 0x209D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_162
|
|
{0x4164, 0x8C08, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_164
|
|
{0x4166, 0x08F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_166
|
|
{0x4168, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_168
|
|
{0x416A, 0x008F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16A
|
|
{0x416C, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16C
|
|
{0x416E, 0x0188, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16E
|
|
{0x4170, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_170
|
|
{0x4172, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_172
|
|
{0x4174, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_174
|
|
{0x4176, 0x0290, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_176
|
|
{0x4178, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_178
|
|
{0x417A, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_17A
|
|
{0x417C, 0x2DA3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_17C
|
|
{0x417E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_17E
|
|
{0x4180, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_180
|
|
{0x4182, 0x089D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_182
|
|
{0x4184, 0xF06D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_184
|
|
{0x4186, 0x4070, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_186
|
|
{0x4188, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_188
|
|
{0x418A, 0x214D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18A
|
|
{0x418C, 0x1FF6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18C
|
|
{0x418E, 0x0851, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18E
|
|
{0x4190, 0x0245, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_190
|
|
{0x4192, 0x9D36, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_192
|
|
{0x4194, 0xD8F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_194
|
|
{0x4196, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_196
|
|
{0x4198, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_198
|
|
{0x419A, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_19A
|
|
{0x419C, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_19C
|
|
{0x419E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_19E
|
|
{0x41A0, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A0
|
|
{0x41A2, 0x020D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A2
|
|
{0x41A4, 0x0205, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A4
|
|
{0x41A6, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A6
|
|
{0x41A8, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A8
|
|
{0x41AA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1AA
|
|
{0x41AC, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1AC
|
|
{0x41AE, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1AE
|
|
{0x41B0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B0
|
|
{0x41B2, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B2
|
|
{0x41B4, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B4
|
|
{0x41B6, 0xD802, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B6
|
|
{0x41B8, 0x0D02, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B8
|
|
{0x41BA, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1BA
|
|
{0x41BC, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1BC
|
|
{0x41BE, 0xD8F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1BE
|
|
{0x41C0, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C0
|
|
{0x41C2, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C2
|
|
{0x41C4, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C4
|
|
{0x41C6, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C6
|
|
{0x41C8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C8
|
|
{0x41CA, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1CA
|
|
{0x41CC, 0x020D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1CC
|
|
{0x41CE, 0x0205, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1CE
|
|
{0x41D0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D0
|
|
{0x41D2, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D2
|
|
{0x41D4, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D4
|
|
{0x41D6, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D6
|
|
{0x41D8, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D8
|
|
{0x41DA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1DA
|
|
{0x41DC, 0x8713, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1DC
|
|
{0x41DE, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1DE
|
|
{0x41E0, 0xD802, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E0
|
|
{0x41E2, 0x0DE0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E2
|
|
{0x41E4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E4
|
|
{0x41E6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E6
|
|
{0x41E8, 0x0035, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E8
|
|
{0x41EA, 0x10AF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1EA
|
|
{0x41EC, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1EC
|
|
{0x41EE, 0x30C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1EE
|
|
{0x41F0, 0xB2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F0
|
|
{0x41F2, 0x01B5, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F2
|
|
{0x41F4, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F4
|
|
{0x41F6, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F6
|
|
{0x41F8, 0x0292, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F8
|
|
{0x41FA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1FA
|
|
{0x41FC, 0x9A8B, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1FC
|
|
{0x41FE, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1FE
|
|
{0x4200, 0x9997, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_200
|
|
{0x4202, 0xF007, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_202
|
|
{0x4204, 0xB6F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_204
|
|
{0x4206, 0x0020, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_206
|
|
{0x4208, 0x5830, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_208
|
|
{0x420A, 0xC040, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20A
|
|
{0x420C, 0x1282, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20C
|
|
{0x420E, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20E
|
|
{0x4210, 0x9CF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_210
|
|
{0x4212, 0x01B2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_212
|
|
{0x4214, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_214
|
|
{0x4216, 0xB8F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_216
|
|
{0x4218, 0x0799, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_218
|
|
{0x421A, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_21A
|
|
{0x421C, 0x98F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_21C
|
|
{0x421E, 0x0296, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_21E
|
|
{0x4220, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_220
|
|
{0x4222, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_222
|
|
{0x4224, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_224
|
|
{0x4226, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_226
|
|
{0x4228, 0x02A1, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_228
|
|
{0x422A, 0xF01F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22A
|
|
{0x422C, 0x1009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22C
|
|
{0x422E, 0x2220, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22E
|
|
{0x4230, 0x0808, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_230
|
|
{0x4232, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_232
|
|
{0x4234, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_234
|
|
{0x4236, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_236
|
|
{0x4238, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_238
|
|
{0x423A, 0x0788, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_23A
|
|
{0x423C, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_23C
|
|
{0x423E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_23E
|
|
{0x4240, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_240
|
|
{0x4242, 0x0290, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_242
|
|
{0x4244, 0xF016, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_244
|
|
{0x4246, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_246
|
|
{0x4248, 0x11A3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_248
|
|
{0x424A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24A
|
|
{0x424C, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24C
|
|
{0x424E, 0x089D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24E
|
|
{0x4250, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_250
|
|
{0x4252, 0xA1F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_252
|
|
{0x4254, 0x20A1, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_254
|
|
{0x4256, 0xF006, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_256
|
|
{0x4258, 0x4300, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_258
|
|
{0x425A, 0xF04A, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_25A
|
|
{0x425C, 0x8B8E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_25C
|
|
{0x425E, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_25E
|
|
{0x4260, 0x1640, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_260
|
|
{0x4262, 0x14F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_262
|
|
{0x4264, 0x0B02, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_264
|
|
{0x4266, 0x02F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_266
|
|
{0x4268, 0x00A6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_268
|
|
{0x426A, 0xF013, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26A
|
|
{0x426C, 0xB283, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26C
|
|
{0x426E, 0x9C36, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26E
|
|
{0x4270, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_270
|
|
{0x4272, 0x0636, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_272
|
|
{0x4274, 0x009C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_274
|
|
{0x4276, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_276
|
|
{0x4278, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_278
|
|
{0x427A, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_27A
|
|
{0x427C, 0xA0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_27C
|
|
{0x427E, 0x0630, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_27E
|
|
{0x4280, 0x18F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_280
|
|
{0x4282, 0x02A3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_282
|
|
{0x4284, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_284
|
|
{0x4286, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_286
|
|
{0x4288, 0x0243, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_288
|
|
{0x428A, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28A
|
|
{0x428C, 0x049D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28C
|
|
{0x428E, 0xF078, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28E
|
|
{0x4290, 0x3018, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_290
|
|
{0x4292, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_292
|
|
{0x4294, 0x9D82, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_294
|
|
{0x4296, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_296
|
|
{0x4298, 0x9030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_298
|
|
{0x429A, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_29A
|
|
{0x429C, 0x1130, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_29C
|
|
{0x429E, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_29E
|
|
{0x42A0, 0x0082, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A0
|
|
{0x42A2, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A2
|
|
{0x42A4, 0x1009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A4
|
|
{0x42A6, 0xF02A, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A6
|
|
{0x42A8, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A8
|
|
{0x42AA, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2AA
|
|
{0x42AC, 0x3018, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2AC
|
|
{0x42AE, 0xF007, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2AE
|
|
{0x42B0, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B0
|
|
{0x42B2, 0x1C8C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B2
|
|
{0x42B4, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B4
|
|
{0x42B6, 0x301F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B6
|
|
{0x42B8, 0x216D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B8
|
|
{0x42BA, 0x0A51, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2BA
|
|
{0x42BC, 0x1CEA, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2BC
|
|
{0x42BE, 0x4162, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2BE
|
|
{0x42C0, 0x0045, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C0
|
|
{0x42C2, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C2
|
|
{0x42C4, 0x30C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C4
|
|
{0x42C6, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C6
|
|
{0x42C8, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C8
|
|
{0x42CA, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2CA
|
|
{0x42CC, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2CC
|
|
{0x42CE, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2CE
|
|
{0x42D0, 0xF006, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D0
|
|
{0x42D2, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D2
|
|
{0x42D4, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D4
|
|
{0x42D6, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D6
|
|
{0x42D8, 0x0000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D8
|
|
{0x42DA, 0x0D00, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2DA
|
|
{0x42DC, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2DC
|
|
{0x42DE, 0x0030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2DE
|
|
{0x42E0, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E0
|
|
{0x42E2, 0x0183, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E2
|
|
{0x42E4, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E4
|
|
{0x42E6, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E6
|
|
{0x42E8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E8
|
|
{0x42EA, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2EA
|
|
{0x42EC, 0x0687, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2EC
|
|
{0x42EE, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2EE
|
|
{0x42F0, 0x36C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F0
|
|
{0x42F2, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F2
|
|
{0x42F4, 0x000F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F4
|
|
{0x42F6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F6
|
|
{0x42F8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F8
|
|
{0x42FA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2FA
|
|
{0x42FC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2FC
|
|
{0x42FE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2FE
|
|
{0x4300, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_300
|
|
{0x4302, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_302
|
|
{0x4304, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_304
|
|
{0x4306, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_306
|
|
{0x4308, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_308
|
|
{0x430A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30A
|
|
{0x430C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30C
|
|
{0x430E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30E
|
|
{0x4310, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_310
|
|
{0x4312, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_312
|
|
{0x4314, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_314
|
|
{0x4316, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_316
|
|
{0x4318, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_318
|
|
{0x431A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_31A
|
|
{0x431C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_31C
|
|
{0x431E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_31E
|
|
{0x4320, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_320
|
|
{0x4322, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_322
|
|
{0x4324, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_324
|
|
{0x4326, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_326
|
|
{0x4328, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_328
|
|
{0x432A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32A
|
|
{0x432C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32C
|
|
{0x432E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32E
|
|
{0x4330, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_330
|
|
{0x4332, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_332
|
|
{0x4334, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_334
|
|
{0x4336, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_336
|
|
{0x4338, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_338
|
|
{0x433A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_33A
|
|
{0x433C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_33C
|
|
{0x433E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_33E
|
|
{0x4340, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_340
|
|
{0x4342, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_342
|
|
{0x4344, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_344
|
|
{0x4346, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_346
|
|
{0x4348, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_348
|
|
{0x434A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34A
|
|
{0x434C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34C
|
|
{0x434E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34E
|
|
{0x4350, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_350
|
|
{0x4352, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_352
|
|
{0x4354, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_354
|
|
{0x4356, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_356
|
|
{0x4358, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_358
|
|
{0x435A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_35A
|
|
{0x435C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_35C
|
|
{0x435E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_35E
|
|
{0x4360, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_360
|
|
{0x4362, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_362
|
|
{0x4364, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_364
|
|
{0x4366, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_366
|
|
{0x4368, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_368
|
|
{0x436A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36A
|
|
{0x436C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36C
|
|
{0x436E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36E
|
|
{0x4370, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_370
|
|
{0x4372, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_372
|
|
{0x4374, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_374
|
|
{0x4376, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_376
|
|
{0x4378, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_378
|
|
{0x437A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_37A
|
|
{0x437C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_37C
|
|
{0x437E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_37E
|
|
{0x4380, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_380
|
|
{0x4382, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_382
|
|
{0x4384, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_384
|
|
{0x4386, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_386
|
|
{0x4388, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_388
|
|
{0x438A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38A
|
|
{0x438C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38C
|
|
{0x438E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38E
|
|
{0x4390, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_390
|
|
{0x4392, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_392
|
|
{0x4394, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_394
|
|
{0x4396, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_396
|
|
{0x4398, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_398
|
|
{0x439A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_39A
|
|
{0x439C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_39C
|
|
{0x439E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_39E
|
|
{0x43A0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A0
|
|
{0x43A2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A2
|
|
{0x43A4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A4
|
|
{0x43A6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A6
|
|
{0x43A8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A8
|
|
{0x43AA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3AA
|
|
{0x43AC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3AC
|
|
{0x43AE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3AE
|
|
{0x43B0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B0
|
|
{0x43B2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B2
|
|
{0x43B4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B4
|
|
{0x43B6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B6
|
|
{0x43B8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B8
|
|
{0x43BA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3BA
|
|
{0x43BC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3BC
|
|
{0x43BE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3BE
|
|
{0x43C0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C0
|
|
{0x43C2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C2
|
|
{0x43C4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C4
|
|
{0x43C6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C6
|
|
{0x43C8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C8
|
|
{0x43CA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3CA
|
|
{0x43CC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3CC
|
|
{0x43CE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3CE
|
|
{0x43D0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D0
|
|
{0x43D2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D2
|
|
{0x43D4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D4
|
|
{0x43D6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D6
|
|
{0x43D8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D8
|
|
{0x43DA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3DA
|
|
{0x43DC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3DC
|
|
{0x43DE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3DE
|
|
{0x43E0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E0
|
|
{0x43E2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E2
|
|
{0x43E4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E4
|
|
{0x43E6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E6
|
|
{0x43E8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E8
|
|
{0x43EA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3EA
|
|
{0x43EC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3EC
|
|
{0x43EE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3EE
|
|
{0x43F0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F0
|
|
{0x43F2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F2
|
|
{0x43F4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F4
|
|
{0x43F6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F6
|
|
{0x43F8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F8
|
|
{0x43FA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3FA
|
|
{0x43FC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3FC
|
|
{0x43FE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3FE
|
|
{0x4400, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_400
|
|
{0x4402, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_402
|
|
{0x4404, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_404
|
|
{0x4406, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_406
|
|
{0x4408, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_408
|
|
{0x440A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40A
|
|
{0x440C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40C
|
|
{0x440E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40E
|
|
{0x4410, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_410
|
|
{0x4412, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_412
|
|
{0x4414, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_414
|
|
{0x4416, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_416
|
|
{0x4418, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_418
|
|
{0x441A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_41A
|
|
{0x441C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_41C
|
|
{0x441E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_41E
|
|
{0x4420, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_420
|
|
{0x4422, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_422
|
|
{0x4424, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_424
|
|
{0x4426, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_426
|
|
{0x4428, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_428
|
|
{0x442A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42A
|
|
{0x442C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42C
|
|
{0x442E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42E
|
|
{0x4430, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_430
|
|
{0x4432, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_432
|
|
{0x4434, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_434
|
|
{0x4436, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_436
|
|
{0x4438, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_438
|
|
{0x443A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_43A
|
|
{0x443C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_43C
|
|
{0x443E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_43E
|
|
{0x4440, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_440
|
|
{0x4442, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_442
|
|
{0x4444, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_444
|
|
{0x4446, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_446
|
|
{0x4448, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_448
|
|
{0x444A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44A
|
|
{0x444C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44C
|
|
{0x444E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44E
|
|
{0x4450, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_450
|
|
{0x4452, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_452
|
|
{0x4454, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_454
|
|
{0x4456, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_456
|
|
{0x4458, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_458
|
|
{0x445A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_45A
|
|
{0x445C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_45C
|
|
{0x445E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_45E
|
|
{0x4460, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_460
|
|
{0x4462, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_462
|
|
{0x4464, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_464
|
|
{0x4466, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_466
|
|
{0x4468, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_468
|
|
{0x446A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46A
|
|
{0x446C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46C
|
|
{0x446E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46E
|
|
{0x4470, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_470
|
|
{0x4472, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_472
|
|
{0x4474, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_474
|
|
{0x4476, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_476
|
|
{0x4478, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_478
|
|
{0x447A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_47A
|
|
{0x447C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_47C
|
|
{0x447E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_47E
|
|
{0x4480, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_480
|
|
{0x4482, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_482
|
|
{0x4484, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_484
|
|
{0x4486, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_486
|
|
{0x4488, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_488
|
|
{0x448A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48A
|
|
{0x448C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48C
|
|
{0x448E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48E
|
|
{0x4490, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_490
|
|
{0x4492, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_492
|
|
{0x4494, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_494
|
|
{0x4496, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_496
|
|
{0x4498, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_498
|
|
{0x449A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_49A
|
|
{0x449C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_49C
|
|
{0x449E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_49E
|
|
{0x44A0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A0
|
|
{0x44A2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A2
|
|
{0x44A4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A4
|
|
{0x44A6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A6
|
|
{0x44A8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A8
|
|
{0x44AA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4AA
|
|
{0x44AC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4AC
|
|
{0x44AE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4AE
|
|
{0x44B0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4B0
|
|
{0x44B2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4B2
|
|
{0x44B4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4B4
|
|
{0x44BA, 0x036A, AR2020_REG_VALUE_16BIT},//DAC_LD_4_5
|
|
{0x44BC, 0xACAA, AR2020_REG_VALUE_16BIT},//DAC_LD_6_7
|
|
{0x44BE, 0x86C0, AR2020_REG_VALUE_16BIT},//DAC_LD_8_9
|
|
{0x44C0, 0x404B, AR2020_REG_VALUE_16BIT},//DAC_LD_10_11
|
|
{0x44C2, 0x2080, AR2020_REG_VALUE_16BIT},//DAC_LD_12_13
|
|
{0x44C4, 0x04BC, AR2020_REG_VALUE_16BIT},//DAC_LD_14_15
|
|
{0x44C6, 0x14E2, AR2020_REG_VALUE_16BIT},//DAC_LD_16_17
|
|
{0x44C8, 0x7743, AR2020_REG_VALUE_16BIT},//DAC_LD_18_19
|
|
{0x44CA, 0x000E, AR2020_REG_VALUE_16BIT},//DAC_LD_20_21
|
|
{0x44CC, 0x8888, AR2020_REG_VALUE_16BIT},//DAC_LD_22_23
|
|
{0x44CE, 0x8BA4, AR2020_REG_VALUE_16BIT},//DAC_LD_24_25
|
|
{0x44D0, 0x1735, AR2020_REG_VALUE_16BIT},//DAC_LD_26_27
|
|
{0x44D2, 0x0B87, AR2020_REG_VALUE_16BIT},//DAC_LD_28_29
|
|
{0x44D4, 0x8000, AR2020_REG_VALUE_16BIT},//DAC_LD_30_31
|
|
{0x44D6, 0xF206, AR2020_REG_VALUE_16BIT},//DAC_LD_32_33
|
|
{0x44D8, 0xAAFA, AR2020_REG_VALUE_16BIT},//DAC_LD_34_35
|
|
{0x44DA, 0xC001, AR2020_REG_VALUE_16BIT},//DAC_LD_36_37
|
|
{0x44DC, 0x1C80, AR2020_REG_VALUE_16BIT},//DAC_LD_38_39
|
|
{0x44DE, 0x1ABC, AR2020_REG_VALUE_16BIT},//DAC_LD_40_41
|
|
{0x44E0, 0x323C, AR2020_REG_VALUE_16BIT},//DAC_LD_42_43
|
|
{0x44E2, 0x3221, AR2020_REG_VALUE_16BIT},//DAC_LD_44_45
|
|
{0x44E4, 0x8000, AR2020_REG_VALUE_16BIT},//DAC_LD_46_47
|
|
{0x44E6, 0x723F, AR2020_REG_VALUE_16BIT},//DAC_LD_48_49
|
|
{0x32A4, 0x0000, AR2020_REG_VALUE_16BIT},//CRM_CTRL
|
|
{0x328E, 0x0004, AR2020_REG_VALUE_16BIT},//ADDR_CTRL
|
|
{0x333C, 0x0001, AR2020_REG_VALUE_16BIT},//DYNAMIC_CTRL
|
|
{0x3098, 0x0001, AR2020_REG_VALUE_16BIT},//MODULE_ODP_FORCE_CLK
|
|
{0x301A, 0x0000, AR2020_REG_VALUE_16BIT},//RESET_REGISTER
|
|
{0x3600, 0x94DF, AR2020_REG_VALUE_16BIT},//FDOC_CTRL
|
|
{0x3616, 0x0000, AR2020_REG_VALUE_16BIT},//FDOC_CTRL2
|
|
{0x3700, 0x0001, AR2020_REG_VALUE_16BIT},//PIX_DEF_ID
|
|
{0x3980, 0x0003, AR2020_REG_VALUE_16BIT},//PIX_DEF_CORR
|
|
{0x36C0, 0x0001, AR2020_REG_VALUE_16BIT},//DIGITAL_GAIN_CTRL
|
|
{0x36DE, 0x002A, AR2020_REG_VALUE_16BIT},//DATA_PEDESTAL1
|
|
{0x301A, 0x0008, AR2020_REG_VALUE_16BIT},//RESET_REGISTER
|
|
{0x31D2, 0x0784, AR2020_REG_VALUE_16BIT},//HDR_SC_GAIN_RATIO
|
|
{0x31D4, 0x110D, AR2020_REG_VALUE_16BIT},//HDR_SC_SCALE
|
|
{0x31D6, 0x01F4, AR2020_REG_VALUE_16BIT},//HDR_SC_THRESHOLD_1A
|
|
{0x31DA, 0x03D5, AR2020_REG_VALUE_16BIT},//HDR_SC_THRESHOLD_2A
|
|
{0x301A, 0x0000, AR2020_REG_VALUE_16BIT},//RESET_REGISTER
|
|
{0x0008, 0x00A8, AR2020_REG_VALUE_16BIT},//DATA_PEDESTAL
|
|
{0x301A, 0x0008, AR2020_REG_VALUE_16BIT},//RESET_REGISTER
|
|
{0x3340, 0x0C60, AR2020_REG_VALUE_16BIT},//OTPM_CTRL
|
|
{0x3340, 0x1C60, AR2020_REG_VALUE_16BIT},//OTPM_CTRL
|
|
{0x0100, 0x01, AR2020_REG_VALUE_08BIT},//MODE_SELECT
|
|
{0x44D6, 0xB206, AR2020_REG_VALUE_16BIT},//DAC_LD_32_33
|
|
|
|
{REG_NULL, 0x00, AR2020_REG_VALUE_16BIT},
|
|
};
|
|
|
|
static const struct regval ar2020_hdr10bit_5120x3840_30fps_8lane_regs[] = {
|
|
{REG_DELAY, 2000, AR2020_REG_VALUE_16BIT},
|
|
{0x44D6, 0xF206, AR2020_REG_VALUE_16BIT},//DAC_LD_32_33
|
|
{0x0100, 0x00, AR2020_REG_VALUE_08BIT},//MODE_SELECT
|
|
{0x0304, 0x0006, AR2020_REG_VALUE_16BIT},//VT_PRE_PLL_CLK_DIV
|
|
{0x0306, 0x00E5, AR2020_REG_VALUE_16BIT},//VT_PLL_MULTIPLIER
|
|
{0x0300, 0x0006, AR2020_REG_VALUE_16BIT},//VT_PIX_CLK_DIV
|
|
{0x0302, 0x0001, AR2020_REG_VALUE_16BIT},//VT_SYS_CLK_DIV
|
|
{0x030C, 0x0007, AR2020_REG_VALUE_16BIT},//OP_PRE_PLL_CLK_DIV
|
|
{0x030E, 0x01BD, AR2020_REG_VALUE_16BIT},//OP_PLL_MULTIPLIER
|
|
{0x0308, 0x0005, AR2020_REG_VALUE_16BIT},//OP_PIX_CLK_DIV
|
|
{0x030A, 0x0002, AR2020_REG_VALUE_16BIT},//OP_SYS_CLK_DIV
|
|
{0x0344, 0x0008, AR2020_REG_VALUE_16BIT},//X_ADDR_START
|
|
{0x0348, 0x1407, AR2020_REG_VALUE_16BIT},//X_ADDR_END
|
|
{0x0346, 0x0008, AR2020_REG_VALUE_16BIT},//Y_ADDR_START
|
|
{0x034A, 0x0F07, AR2020_REG_VALUE_16BIT},//Y_ADDR_END
|
|
{0x034C, 0x1400, AR2020_REG_VALUE_16BIT},//X_OUTPUT_SIZE
|
|
{0x034E, 0x0F00, AR2020_REG_VALUE_16BIT},//Y_OUTPUT_SIZE
|
|
{0x0380, 0x0001, AR2020_REG_VALUE_16BIT},//X_EVEN_INC
|
|
{0x0382, 0x0001, AR2020_REG_VALUE_16BIT},//X_ODD_INC
|
|
{0x0384, 0x0001, AR2020_REG_VALUE_16BIT},//Y_EVEN_INC
|
|
{0x0386, 0x0001, AR2020_REG_VALUE_16BIT},//Y_ODD_INC
|
|
{0x0900, 0x00, AR2020_REG_VALUE_08BIT},//BINNING_MODE
|
|
{0x0901, 0x11, AR2020_REG_VALUE_08BIT},//BINNING_TYPE
|
|
{0x0342, 0x1718, AR2020_REG_VALUE_16BIT},//LINE_LENGTH_PCK
|
|
{0x0340, 0x1E3C, AR2020_REG_VALUE_16BIT},//FRAME_LENGTH_LINES
|
|
{0x0112, 0x0A0A, AR2020_REG_VALUE_16BIT},//CSI_DATA_FORMAT
|
|
{0x0114, 0x07, AR2020_REG_VALUE_08BIT},//CSI_LANE_MODE
|
|
{0x0800, 0x10, AR2020_REG_VALUE_08BIT},//TCLK_POST
|
|
{0x0801, 0x09, AR2020_REG_VALUE_08BIT},//THS_PREPARE
|
|
{0x0802, 0x11, AR2020_REG_VALUE_08BIT},//THS_ZERO_MIN
|
|
{0x0803, 0x0C, AR2020_REG_VALUE_08BIT},//THS_TRAIL
|
|
{0x0804, 0x0F, AR2020_REG_VALUE_08BIT},//TCLK_TRAIL_MIN
|
|
{0x0805, 0x08, AR2020_REG_VALUE_08BIT},//TCLK_PREPARE
|
|
{0x0806, 0x34, AR2020_REG_VALUE_08BIT},//TCLK_ZERO
|
|
{0x0807, 0x0A, AR2020_REG_VALUE_08BIT},//TLPX
|
|
{0x082A, 0x15, AR2020_REG_VALUE_08BIT},//TWAKEUP
|
|
{0x082B, 0x11, AR2020_REG_VALUE_08BIT},//TINIT
|
|
{0x082C, 0x13, AR2020_REG_VALUE_08BIT},//THS_EXIT
|
|
{0x3F06, 0x00C0, AR2020_REG_VALUE_16BIT},//MIPI_TIMING_2
|
|
{0x3F0A, 0xA000, AR2020_REG_VALUE_16BIT},//MIPI_TIMING_4
|
|
{0x3F0C, 0x000E, AR2020_REG_VALUE_16BIT},//MIPI_TIMING_5
|
|
{0x3F20, 0x8080, AR2020_REG_VALUE_16BIT},//MIPI_PHY_TRIM_MSB
|
|
{0x3F1E, 0x0004, AR2020_REG_VALUE_16BIT},//MIPI_PHY_TRIM_LSB
|
|
{0x0202, 0x079E, AR2020_REG_VALUE_16BIT},//COARSE_INTEGRATION_TIME
|
|
{0x0224, 0x00C3, AR2020_REG_VALUE_16BIT},//SHORT_COARSE_INTEGRATION_TIME
|
|
{0x3040, 0x0010, AR2020_REG_VALUE_16BIT},//READ_MODE
|
|
{0x3042, 0x80F1, AR2020_REG_VALUE_16BIT},//T1_TO_T2_DIST_CTRL
|
|
{0x0220, 0x73, AR2020_REG_VALUE_08BIT},//HDR_MODE
|
|
{0x3F18, 0x7B70, AR2020_REG_VALUE_16BIT},//MIPI_JPEG_PN9_DATA_TYPE
|
|
{0x3F1A, 0x102B, AR2020_REG_VALUE_16BIT},
|
|
{0x3f22, 0x3806, AR2020_REG_VALUE_16BIT},
|
|
{0x4000, 0x0114, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_00
|
|
{0x4002, 0x1A25, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_02
|
|
{0x4004, 0x3DFF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_04
|
|
{0x4006, 0xFFFF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_06
|
|
{0x4008, 0x0A35, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_08
|
|
{0x400A, 0x10EF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_0A
|
|
{0x400C, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_0C
|
|
{0x400E, 0x30D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_0E
|
|
{0x4010, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10
|
|
{0x4012, 0xB5F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12
|
|
{0x4014, 0x0085, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14
|
|
{0x4016, 0xF004, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16
|
|
{0x4018, 0x9A89, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18
|
|
{0x401A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A
|
|
{0x401C, 0x9997, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C
|
|
{0x401E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E
|
|
{0x4020, 0x30C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20
|
|
{0x4022, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22
|
|
{0x4024, 0x82F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24
|
|
{0x4026, 0x0030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26
|
|
{0x4028, 0x18F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28
|
|
{0x402A, 0x0320, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A
|
|
{0x402C, 0x58F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C
|
|
{0x402E, 0x089C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E
|
|
{0x4030, 0xF010, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30
|
|
{0x4032, 0x99B6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32
|
|
{0x4034, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34
|
|
{0x4036, 0xB498, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36
|
|
{0x4038, 0xA096, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38
|
|
{0x403A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A
|
|
{0x403C, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C
|
|
{0x403E, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E
|
|
{0x4040, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40
|
|
{0x4042, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42
|
|
{0x4044, 0x209D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44
|
|
{0x4046, 0x8C08, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46
|
|
{0x4048, 0x08F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48
|
|
{0x404A, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A
|
|
{0x404C, 0x008F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4C
|
|
{0x404E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4E
|
|
{0x4050, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_50
|
|
{0x4052, 0x0488, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_52
|
|
{0x4054, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_54
|
|
{0x4056, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_56
|
|
{0x4058, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_58
|
|
{0x405A, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_5A
|
|
{0x405C, 0x0290, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_5C
|
|
{0x405E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_5E
|
|
{0x4060, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_60
|
|
{0x4062, 0x2EA3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_62
|
|
{0x4064, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_64
|
|
{0x4066, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_66
|
|
{0x4068, 0x089D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_68
|
|
{0x406A, 0xF075, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_6A
|
|
{0x406C, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_6C
|
|
{0x406E, 0x4070, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_6E
|
|
{0x4070, 0x216D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_70
|
|
{0x4072, 0x1CF6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_72
|
|
{0x4074, 0x8B00, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_74
|
|
{0x4076, 0x5186, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_76
|
|
{0x4078, 0x1300, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_78
|
|
{0x407A, 0x0205, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_7A
|
|
{0x407C, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_7C
|
|
{0x407E, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_7E
|
|
{0x4080, 0x8387, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_80
|
|
{0x4082, 0xF006, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_82
|
|
{0x4084, 0x8702, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_84
|
|
{0x4086, 0x0D02, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_86
|
|
{0x4088, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_88
|
|
{0x408A, 0x0383, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_8A
|
|
{0x408C, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_8C
|
|
{0x408E, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_8E
|
|
{0x4090, 0x0213, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_90
|
|
{0x4092, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_92
|
|
{0x4094, 0xD887, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_94
|
|
{0x4096, 0x020D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_96
|
|
{0x4098, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_98
|
|
{0x409A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_9A
|
|
{0x409C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_9C
|
|
{0x409E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_9E
|
|
{0x40A0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A0
|
|
{0x40A2, 0x0401, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A2
|
|
{0x40A4, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A4
|
|
{0x40A6, 0x82F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A6
|
|
{0x40A8, 0x0883, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A8
|
|
{0x40AA, 0xF009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_AA
|
|
{0x40AC, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_AC
|
|
{0x40AE, 0x2985, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_AE
|
|
{0x40B0, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B0
|
|
{0x40B2, 0x2A87, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B2
|
|
{0x40B4, 0xF63E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B4
|
|
{0x40B6, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B6
|
|
{0x40B8, 0x0801, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B8
|
|
{0x40BA, 0x40F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_BA
|
|
{0x40BC, 0x0800, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_BC
|
|
{0x40BE, 0x48F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_BE
|
|
{0x40C0, 0x0882, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C0
|
|
{0x40C2, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C2
|
|
{0x40C4, 0x0401, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C4
|
|
{0x40C6, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C6
|
|
{0x40C8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C8
|
|
{0x40CA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_CA
|
|
{0x40CC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_CC
|
|
{0x40CE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_CE
|
|
{0x40D0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D0
|
|
{0x40D2, 0x0401, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D2
|
|
{0x40D4, 0xF015, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D4
|
|
{0x40D6, 0x002C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D6
|
|
{0x40D8, 0xF00E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D8
|
|
{0x40DA, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_DA
|
|
{0x40DC, 0x0687, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_DC
|
|
{0x40DE, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_DE
|
|
{0x40E0, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E0
|
|
{0x40E2, 0x61E8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E2
|
|
{0x40E4, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E4
|
|
{0x40E6, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E6
|
|
{0x40E8, 0x3480, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E8
|
|
{0x40EA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_EA
|
|
{0x40EC, 0x3240, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_EC
|
|
{0x40EE, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_EE
|
|
{0x40F0, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F0
|
|
{0x40F2, 0xF00E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F2
|
|
{0x40F4, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F4
|
|
{0x40F6, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F6
|
|
{0x40F8, 0x3240, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F8
|
|
{0x40FA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_FA
|
|
{0x40FC, 0x3480, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_FC
|
|
{0x40FE, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_FE
|
|
{0x4100, 0xC0E6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_100
|
|
{0x4102, 0xF004, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_102
|
|
{0x4104, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_104
|
|
{0x4106, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_106
|
|
{0x4108, 0xB0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_108
|
|
{0x410A, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10A
|
|
{0x410C, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10C
|
|
{0x410E, 0x86F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10E
|
|
{0x4110, 0x0086, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_110
|
|
{0x4112, 0xF089, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_112
|
|
{0x4114, 0xB0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_114
|
|
{0x4116, 0x00E9, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_116
|
|
{0x4118, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_118
|
|
{0x411A, 0x8AF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_11A
|
|
{0x411C, 0x0000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_11C
|
|
{0x411E, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_11E
|
|
{0x4120, 0x00E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_120
|
|
{0x4122, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_122
|
|
{0x4124, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_124
|
|
{0x4126, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_126
|
|
{0x4128, 0x0A35, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_128
|
|
{0x412A, 0x10EF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12A
|
|
{0x412C, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12C
|
|
{0x412E, 0x30D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12E
|
|
{0x4130, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_130
|
|
{0x4132, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_132
|
|
{0x4134, 0x049A, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_134
|
|
{0x4136, 0x89F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_136
|
|
{0x4138, 0x0099, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_138
|
|
{0x413A, 0x97F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_13A
|
|
{0x413C, 0x0030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_13C
|
|
{0x413E, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_13E
|
|
{0x4140, 0x0082, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_140
|
|
{0x4142, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_142
|
|
{0x4144, 0x3018, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_144
|
|
{0x4146, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_146
|
|
{0x4148, 0xB520, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_148
|
|
{0x414A, 0x58F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14A
|
|
{0x414C, 0x089C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14C
|
|
{0x414E, 0xF010, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14E
|
|
{0x4150, 0x99B6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_150
|
|
{0x4152, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_152
|
|
{0x4154, 0xB498, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_154
|
|
{0x4156, 0xA096, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_156
|
|
{0x4158, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_158
|
|
{0x415A, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_15A
|
|
{0x415C, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_15C
|
|
{0x415E, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_15E
|
|
{0x4160, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_160
|
|
{0x4162, 0x209D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_162
|
|
{0x4164, 0x8C08, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_164
|
|
{0x4166, 0x08F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_166
|
|
{0x4168, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_168
|
|
{0x416A, 0x008F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16A
|
|
{0x416C, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16C
|
|
{0x416E, 0x0188, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16E
|
|
{0x4170, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_170
|
|
{0x4172, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_172
|
|
{0x4174, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_174
|
|
{0x4176, 0x0290, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_176
|
|
{0x4178, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_178
|
|
{0x417A, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_17A
|
|
{0x417C, 0x2DA3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_17C
|
|
{0x417E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_17E
|
|
{0x4180, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_180
|
|
{0x4182, 0x089D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_182
|
|
{0x4184, 0xF06D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_184
|
|
{0x4186, 0x4070, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_186
|
|
{0x4188, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_188
|
|
{0x418A, 0x214D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18A
|
|
{0x418C, 0x1FF6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18C
|
|
{0x418E, 0x0851, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18E
|
|
{0x4190, 0x0245, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_190
|
|
{0x4192, 0x9D36, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_192
|
|
{0x4194, 0xD8F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_194
|
|
{0x4196, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_196
|
|
{0x4198, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_198
|
|
{0x419A, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_19A
|
|
{0x419C, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_19C
|
|
{0x419E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_19E
|
|
{0x41A0, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A0
|
|
{0x41A2, 0x020D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A2
|
|
{0x41A4, 0x0205, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A4
|
|
{0x41A6, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A6
|
|
{0x41A8, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A8
|
|
{0x41AA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1AA
|
|
{0x41AC, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1AC
|
|
{0x41AE, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1AE
|
|
{0x41B0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B0
|
|
{0x41B2, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B2
|
|
{0x41B4, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B4
|
|
{0x41B6, 0xD802, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B6
|
|
{0x41B8, 0x0D02, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B8
|
|
{0x41BA, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1BA
|
|
{0x41BC, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1BC
|
|
{0x41BE, 0xD8F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1BE
|
|
{0x41C0, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C0
|
|
{0x41C2, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C2
|
|
{0x41C4, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C4
|
|
{0x41C6, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C6
|
|
{0x41C8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C8
|
|
{0x41CA, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1CA
|
|
{0x41CC, 0x020D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1CC
|
|
{0x41CE, 0x0205, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1CE
|
|
{0x41D0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D0
|
|
{0x41D2, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D2
|
|
{0x41D4, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D4
|
|
{0x41D6, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D6
|
|
{0x41D8, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D8
|
|
{0x41DA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1DA
|
|
{0x41DC, 0x8713, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1DC
|
|
{0x41DE, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1DE
|
|
{0x41E0, 0xD802, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E0
|
|
{0x41E2, 0x0DE0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E2
|
|
{0x41E4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E4
|
|
{0x41E6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E6
|
|
{0x41E8, 0x0035, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E8
|
|
{0x41EA, 0x10AF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1EA
|
|
{0x41EC, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1EC
|
|
{0x41EE, 0x30C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1EE
|
|
{0x41F0, 0xB2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F0
|
|
{0x41F2, 0x01B5, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F2
|
|
{0x41F4, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F4
|
|
{0x41F6, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F6
|
|
{0x41F8, 0x0292, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F8
|
|
{0x41FA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1FA
|
|
{0x41FC, 0x9A8B, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1FC
|
|
{0x41FE, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1FE
|
|
{0x4200, 0x9997, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_200
|
|
{0x4202, 0xF007, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_202
|
|
{0x4204, 0xB6F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_204
|
|
{0x4206, 0x0020, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_206
|
|
{0x4208, 0x5830, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_208
|
|
{0x420A, 0xC040, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20A
|
|
{0x420C, 0x1282, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20C
|
|
{0x420E, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20E
|
|
{0x4210, 0x9CF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_210
|
|
{0x4212, 0x01B2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_212
|
|
{0x4214, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_214
|
|
{0x4216, 0xB8F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_216
|
|
{0x4218, 0x0799, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_218
|
|
{0x421A, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_21A
|
|
{0x421C, 0x98F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_21C
|
|
{0x421E, 0x0296, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_21E
|
|
{0x4220, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_220
|
|
{0x4222, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_222
|
|
{0x4224, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_224
|
|
{0x4226, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_226
|
|
{0x4228, 0x02A1, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_228
|
|
{0x422A, 0xF01F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22A
|
|
{0x422C, 0x1009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22C
|
|
{0x422E, 0x2220, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22E
|
|
{0x4230, 0x0808, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_230
|
|
{0x4232, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_232
|
|
{0x4234, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_234
|
|
{0x4236, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_236
|
|
{0x4238, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_238
|
|
{0x423A, 0x0788, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_23A
|
|
{0x423C, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_23C
|
|
{0x423E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_23E
|
|
{0x4240, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_240
|
|
{0x4242, 0x0290, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_242
|
|
{0x4244, 0xF016, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_244
|
|
{0x4246, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_246
|
|
{0x4248, 0x11A3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_248
|
|
{0x424A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24A
|
|
{0x424C, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24C
|
|
{0x424E, 0x089D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24E
|
|
{0x4250, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_250
|
|
{0x4252, 0xA1F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_252
|
|
{0x4254, 0x20A1, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_254
|
|
{0x4256, 0xF006, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_256
|
|
{0x4258, 0x4300, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_258
|
|
{0x425A, 0xF04A, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_25A
|
|
{0x425C, 0x8B8E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_25C
|
|
{0x425E, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_25E
|
|
{0x4260, 0x1640, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_260
|
|
{0x4262, 0x14F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_262
|
|
{0x4264, 0x0B02, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_264
|
|
{0x4266, 0x02F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_266
|
|
{0x4268, 0x00A6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_268
|
|
{0x426A, 0xF013, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26A
|
|
{0x426C, 0xB283, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26C
|
|
{0x426E, 0x9C36, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26E
|
|
{0x4270, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_270
|
|
{0x4272, 0x0636, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_272
|
|
{0x4274, 0x009C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_274
|
|
{0x4276, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_276
|
|
{0x4278, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_278
|
|
{0x427A, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_27A
|
|
{0x427C, 0xA0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_27C
|
|
{0x427E, 0x0630, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_27E
|
|
{0x4280, 0x18F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_280
|
|
{0x4282, 0x02A3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_282
|
|
{0x4284, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_284
|
|
{0x4286, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_286
|
|
{0x4288, 0x0243, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_288
|
|
{0x428A, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28A
|
|
{0x428C, 0x049D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28C
|
|
{0x428E, 0xF078, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28E
|
|
{0x4290, 0x3018, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_290
|
|
{0x4292, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_292
|
|
{0x4294, 0x9D82, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_294
|
|
{0x4296, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_296
|
|
{0x4298, 0x9030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_298
|
|
{0x429A, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_29A
|
|
{0x429C, 0x1130, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_29C
|
|
{0x429E, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_29E
|
|
{0x42A0, 0x0082, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A0
|
|
{0x42A2, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A2
|
|
{0x42A4, 0x1009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A4
|
|
{0x42A6, 0xF02A, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A6
|
|
{0x42A8, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A8
|
|
{0x42AA, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2AA
|
|
{0x42AC, 0x3018, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2AC
|
|
{0x42AE, 0xF007, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2AE
|
|
{0x42B0, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B0
|
|
{0x42B2, 0x1C8C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B2
|
|
{0x42B4, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B4
|
|
{0x42B6, 0x301F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B6
|
|
{0x42B8, 0x216D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B8
|
|
{0x42BA, 0x0A51, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2BA
|
|
{0x42BC, 0x1CEA, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2BC
|
|
{0x42BE, 0x4162, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2BE
|
|
{0x42C0, 0x0045, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C0
|
|
{0x42C2, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C2
|
|
{0x42C4, 0x30C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C4
|
|
{0x42C6, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C6
|
|
{0x42C8, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C8
|
|
{0x42CA, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2CA
|
|
{0x42CC, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2CC
|
|
{0x42CE, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2CE
|
|
{0x42D0, 0xF006, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D0
|
|
{0x42D2, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D2
|
|
{0x42D4, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D4
|
|
{0x42D6, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D6
|
|
{0x42D8, 0x0000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D8
|
|
{0x42DA, 0x0D00, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2DA
|
|
{0x42DC, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2DC
|
|
{0x42DE, 0x0030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2DE
|
|
{0x42E0, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E0
|
|
{0x42E2, 0x0183, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E2
|
|
{0x42E4, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E4
|
|
{0x42E6, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E6
|
|
{0x42E8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E8
|
|
{0x42EA, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2EA
|
|
{0x42EC, 0x0687, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2EC
|
|
{0x42EE, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2EE
|
|
{0x42F0, 0x36C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F0
|
|
{0x42F2, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F2
|
|
{0x42F4, 0x000F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F4
|
|
{0x42F6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F6
|
|
{0x42F8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F8
|
|
{0x42FA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2FA
|
|
{0x42FC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2FC
|
|
{0x42FE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2FE
|
|
{0x4300, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_300
|
|
{0x4302, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_302
|
|
{0x4304, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_304
|
|
{0x4306, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_306
|
|
{0x4308, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_308
|
|
{0x430A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30A
|
|
{0x430C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30C
|
|
{0x430E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30E
|
|
{0x4310, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_310
|
|
{0x4312, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_312
|
|
{0x4314, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_314
|
|
{0x4316, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_316
|
|
{0x4318, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_318
|
|
{0x431A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_31A
|
|
{0x431C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_31C
|
|
{0x431E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_31E
|
|
{0x4320, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_320
|
|
{0x4322, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_322
|
|
{0x4324, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_324
|
|
{0x4326, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_326
|
|
{0x4328, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_328
|
|
{0x432A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32A
|
|
{0x432C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32C
|
|
{0x432E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32E
|
|
{0x4330, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_330
|
|
{0x4332, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_332
|
|
{0x4334, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_334
|
|
{0x4336, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_336
|
|
{0x4338, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_338
|
|
{0x433A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_33A
|
|
{0x433C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_33C
|
|
{0x433E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_33E
|
|
{0x4340, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_340
|
|
{0x4342, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_342
|
|
{0x4344, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_344
|
|
{0x4346, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_346
|
|
{0x4348, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_348
|
|
{0x434A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34A
|
|
{0x434C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34C
|
|
{0x434E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34E
|
|
{0x4350, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_350
|
|
{0x4352, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_352
|
|
{0x4354, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_354
|
|
{0x4356, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_356
|
|
{0x4358, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_358
|
|
{0x435A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_35A
|
|
{0x435C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_35C
|
|
{0x435E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_35E
|
|
{0x4360, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_360
|
|
{0x4362, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_362
|
|
{0x4364, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_364
|
|
{0x4366, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_366
|
|
{0x4368, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_368
|
|
{0x436A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36A
|
|
{0x436C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36C
|
|
{0x436E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36E
|
|
{0x4370, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_370
|
|
{0x4372, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_372
|
|
{0x4374, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_374
|
|
{0x4376, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_376
|
|
{0x4378, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_378
|
|
{0x437A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_37A
|
|
{0x437C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_37C
|
|
{0x437E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_37E
|
|
{0x4380, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_380
|
|
{0x4382, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_382
|
|
{0x4384, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_384
|
|
{0x4386, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_386
|
|
{0x4388, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_388
|
|
{0x438A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38A
|
|
{0x438C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38C
|
|
{0x438E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38E
|
|
{0x4390, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_390
|
|
{0x4392, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_392
|
|
{0x4394, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_394
|
|
{0x4396, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_396
|
|
{0x4398, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_398
|
|
{0x439A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_39A
|
|
{0x439C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_39C
|
|
{0x439E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_39E
|
|
{0x43A0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A0
|
|
{0x43A2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A2
|
|
{0x43A4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A4
|
|
{0x43A6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A6
|
|
{0x43A8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A8
|
|
{0x43AA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3AA
|
|
{0x43AC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3AC
|
|
{0x43AE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3AE
|
|
{0x43B0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B0
|
|
{0x43B2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B2
|
|
{0x43B4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B4
|
|
{0x43B6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B6
|
|
{0x43B8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B8
|
|
{0x43BA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3BA
|
|
{0x43BC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3BC
|
|
{0x43BE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3BE
|
|
{0x43C0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C0
|
|
{0x43C2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C2
|
|
{0x43C4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C4
|
|
{0x43C6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C6
|
|
{0x43C8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C8
|
|
{0x43CA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3CA
|
|
{0x43CC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3CC
|
|
{0x43CE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3CE
|
|
{0x43D0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D0
|
|
{0x43D2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D2
|
|
{0x43D4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D4
|
|
{0x43D6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D6
|
|
{0x43D8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D8
|
|
{0x43DA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3DA
|
|
{0x43DC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3DC
|
|
{0x43DE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3DE
|
|
{0x43E0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E0
|
|
{0x43E2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E2
|
|
{0x43E4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E4
|
|
{0x43E6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E6
|
|
{0x43E8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E8
|
|
{0x43EA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3EA
|
|
{0x43EC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3EC
|
|
{0x43EE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3EE
|
|
{0x43F0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F0
|
|
{0x43F2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F2
|
|
{0x43F4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F4
|
|
{0x43F6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F6
|
|
{0x43F8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F8
|
|
{0x43FA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3FA
|
|
{0x43FC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3FC
|
|
{0x43FE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3FE
|
|
{0x4400, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_400
|
|
{0x4402, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_402
|
|
{0x4404, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_404
|
|
{0x4406, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_406
|
|
{0x4408, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_408
|
|
{0x440A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40A
|
|
{0x440C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40C
|
|
{0x440E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40E
|
|
{0x4410, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_410
|
|
{0x4412, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_412
|
|
{0x4414, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_414
|
|
{0x4416, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_416
|
|
{0x4418, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_418
|
|
{0x441A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_41A
|
|
{0x441C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_41C
|
|
{0x441E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_41E
|
|
{0x4420, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_420
|
|
{0x4422, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_422
|
|
{0x4424, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_424
|
|
{0x4426, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_426
|
|
{0x4428, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_428
|
|
{0x442A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42A
|
|
{0x442C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42C
|
|
{0x442E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42E
|
|
{0x4430, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_430
|
|
{0x4432, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_432
|
|
{0x4434, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_434
|
|
{0x4436, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_436
|
|
{0x4438, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_438
|
|
{0x443A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_43A
|
|
{0x443C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_43C
|
|
{0x443E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_43E
|
|
{0x4440, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_440
|
|
{0x4442, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_442
|
|
{0x4444, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_444
|
|
{0x4446, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_446
|
|
{0x4448, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_448
|
|
{0x444A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44A
|
|
{0x444C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44C
|
|
{0x444E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44E
|
|
{0x4450, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_450
|
|
{0x4452, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_452
|
|
{0x4454, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_454
|
|
{0x4456, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_456
|
|
{0x4458, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_458
|
|
{0x445A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_45A
|
|
{0x445C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_45C
|
|
{0x445E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_45E
|
|
{0x4460, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_460
|
|
{0x4462, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_462
|
|
{0x4464, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_464
|
|
{0x4466, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_466
|
|
{0x4468, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_468
|
|
{0x446A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46A
|
|
{0x446C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46C
|
|
{0x446E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46E
|
|
{0x4470, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_470
|
|
{0x4472, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_472
|
|
{0x4474, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_474
|
|
{0x4476, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_476
|
|
{0x4478, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_478
|
|
{0x447A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_47A
|
|
{0x447C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_47C
|
|
{0x447E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_47E
|
|
{0x4480, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_480
|
|
{0x4482, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_482
|
|
{0x4484, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_484
|
|
{0x4486, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_486
|
|
{0x4488, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_488
|
|
{0x448A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48A
|
|
{0x448C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48C
|
|
{0x448E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48E
|
|
{0x4490, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_490
|
|
{0x4492, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_492
|
|
{0x4494, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_494
|
|
{0x4496, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_496
|
|
{0x4498, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_498
|
|
{0x449A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_49A
|
|
{0x449C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_49C
|
|
{0x449E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_49E
|
|
{0x44A0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A0
|
|
{0x44A2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A2
|
|
{0x44A4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A4
|
|
{0x44A6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A6
|
|
{0x44A8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A8
|
|
{0x44AA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4AA
|
|
{0x44AC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4AC
|
|
{0x44AE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4AE
|
|
{0x44B0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4B0
|
|
{0x44B2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4B2
|
|
{0x44B4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4B4
|
|
{0x5500, 0x0000, AR2020_REG_VALUE_16BIT},//AGAIN_LUT0
|
|
{0x5502, 0x0002, AR2020_REG_VALUE_16BIT},//AGAIN_LUT1
|
|
{0x5504, 0x0006, AR2020_REG_VALUE_16BIT},//AGAIN_LUT2
|
|
{0x5506, 0x0009, AR2020_REG_VALUE_16BIT},//AGAIN_LUT3
|
|
{0x5508, 0x000F, AR2020_REG_VALUE_16BIT},//AGAIN_LUT4
|
|
{0x550A, 0x0010, AR2020_REG_VALUE_16BIT},//AGAIN_LUT5
|
|
{0x550C, 0x0011, AR2020_REG_VALUE_16BIT},//AGAIN_LUT6
|
|
{0x550E, 0x0012, AR2020_REG_VALUE_16BIT},//AGAIN_LUT7
|
|
{0x5510, 0x0019, AR2020_REG_VALUE_16BIT},//AGAIN_LUT8
|
|
{0x5512, 0x0020, AR2020_REG_VALUE_16BIT},//AGAIN_LUT9
|
|
{0x5514, 0x0021, AR2020_REG_VALUE_16BIT},//AGAIN_LUT10
|
|
{0x5516, 0x0023, AR2020_REG_VALUE_16BIT},//AGAIN_LUT11
|
|
{0x5518, 0x0026, AR2020_REG_VALUE_16BIT},//AGAIN_LUT12
|
|
{0x551A, 0x002B, AR2020_REG_VALUE_16BIT},//AGAIN_LUT13
|
|
{0x551C, 0x002F, AR2020_REG_VALUE_16BIT},//AGAIN_LUT14
|
|
{0x551E, 0x0030, AR2020_REG_VALUE_16BIT},//AGAIN_LUT15
|
|
{0x5430, 0x0100, AR2020_REG_VALUE_16BIT},//GT2_COARSE0
|
|
{0x5432, 0x00E8, AR2020_REG_VALUE_16BIT},//GT2_COARSE1
|
|
{0x5434, 0x0123, AR2020_REG_VALUE_16BIT},//GT2_COARSE2
|
|
{0x5436, 0x0108, AR2020_REG_VALUE_16BIT},//GT2_COARSE3
|
|
{0x5438, 0x5125, AR2020_REG_VALUE_16BIT},//GT2_COARSE4
|
|
{0x543A, 0x510A, AR2020_REG_VALUE_16BIT},//GT2_COARSE5
|
|
{0x543C, 0x9133, AR2020_REG_VALUE_16BIT},//GT2_COARSE6
|
|
{0x543E, 0x9117, AR2020_REG_VALUE_16BIT},//GT2_COARSE7
|
|
{0x5440, 0xF130, AR2020_REG_VALUE_16BIT},//GT2_COARSE8
|
|
{0x5442, 0xF114, AR2020_REG_VALUE_16BIT},//GT2_COARSE9
|
|
{0x5444, 0xF186, AR2020_REG_VALUE_16BIT},//GT2_COARSE10
|
|
{0x5446, 0xF227, AR2020_REG_VALUE_16BIT},//GT2_COARSE11
|
|
{0x5448, 0xF30A, AR2020_REG_VALUE_16BIT},//GT2_COARSE12
|
|
{0x544A, 0xF44B, AR2020_REG_VALUE_16BIT},//GT2_COARSE13
|
|
{0x544C, 0xF611, AR2020_REG_VALUE_16BIT},//GT2_COARSE14
|
|
{0x544E, 0xF892, AR2020_REG_VALUE_16BIT},//GT2_COARSE15
|
|
{0x5450, 0xFC1B, AR2020_REG_VALUE_16BIT},//GT2_COARSE16
|
|
{0x5452, 0xFC1B, AR2020_REG_VALUE_16BIT},//GT2_COARSE17
|
|
{0x5454, 0x7772, AR2020_REG_VALUE_16BIT},//GT2_DCG_ATTN_SET0
|
|
{0x5456, 0x5557, AR2020_REG_VALUE_16BIT},//GT2_DCG_ATTN_SET1
|
|
{0x5458, 0x0005, AR2020_REG_VALUE_16BIT},//GT2_DCG_ATTN_SET2
|
|
{0x545A, 0xA550, AR2020_REG_VALUE_16BIT},//GT2_ZONE_SET0
|
|
{0x545C, 0xAAAA, AR2020_REG_VALUE_16BIT},//GT2_ZONE_SET1
|
|
{0x545E, 0x000A, AR2020_REG_VALUE_16BIT},//GT2_ZONE_SET2
|
|
{0x54A0, 0x0000, AR2020_REG_VALUE_16BIT},//ZT2_REG0_ADDR
|
|
{0x54A2, 0x0241, AR2020_REG_VALUE_16BIT},//ZT2_REG0_VALUE0
|
|
{0x54A4, 0x0841, AR2020_REG_VALUE_16BIT},//ZT2_REG0_VALUE1
|
|
{0x54A6, 0x0A41, AR2020_REG_VALUE_16BIT},//ZT2_REG0_VALUE2
|
|
{0x54D8, 0x0000, AR2020_REG_VALUE_16BIT},//ZT2_REG7_ADDR
|
|
{0x54DA, 0x54E2, AR2020_REG_VALUE_16BIT},//ZT2_REG7_VALUE0
|
|
{0x54DC, 0x54E3, AR2020_REG_VALUE_16BIT},//ZT2_REG7_VALUE1
|
|
{0x54DE, 0x54E3, AR2020_REG_VALUE_16BIT},//ZT2_REG7_VALUE2
|
|
{0x3060, 0x0007, AR2020_REG_VALUE_16BIT},//GAIN_TABLE_CTRL
|
|
{0x44BA, 0x0050, AR2020_REG_VALUE_16BIT},//DAC_LD_4_5
|
|
{0x44BC, 0xBCAA, AR2020_REG_VALUE_16BIT},//DAC_LD_6_7
|
|
{0x44C0, 0x4070, AR2020_REG_VALUE_16BIT},//DAC_LD_10_11
|
|
{0x44C4, 0x04D0, AR2020_REG_VALUE_16BIT},//DAC_LD_14_15
|
|
{0x44C6, 0x17E2, AR2020_REG_VALUE_16BIT},//DAC_LD_16_17
|
|
{0x44C8, 0x5A43, AR2020_REG_VALUE_16BIT},//DAC_LD_18_19
|
|
{0x44CA, 0x000E, AR2020_REG_VALUE_16BIT},//DAC_LD_20_21
|
|
{0x44CC, 0x7777, AR2020_REG_VALUE_16BIT},//DAC_LD_22_23
|
|
{0x44CE, 0x8BA4, AR2020_REG_VALUE_16BIT},//DAC_LD_24_25
|
|
{0x44D0, 0x1735, AR2020_REG_VALUE_16BIT},//DAC_LD_26_27
|
|
{0x44D4, 0x8000, AR2020_REG_VALUE_16BIT},//DAC_LD_30_31
|
|
{0x44D6, 0xF206, AR2020_REG_VALUE_16BIT},//DAC_LD_32_33
|
|
{0x44D8, 0xAAFA, AR2020_REG_VALUE_16BIT},//DAC_LD_34_35
|
|
{0x44DA, 0xE001, AR2020_REG_VALUE_16BIT},//DAC_LD_36_37
|
|
{0x44DC, 0x7480, AR2020_REG_VALUE_16BIT},//DAC_LD_38_39
|
|
{0x44DE, 0x9BBC, AR2020_REG_VALUE_16BIT},//DAC_LD_40_41
|
|
{0x44E0, 0x283C, AR2020_REG_VALUE_16BIT},//DAC_LD_42_43
|
|
{0x44E2, 0x2821, AR2020_REG_VALUE_16BIT},//DAC_LD_44_45
|
|
{0x44E4, 0x8000, AR2020_REG_VALUE_16BIT},//DAC_LD_46_47
|
|
{0x44E6, 0x703F, AR2020_REG_VALUE_16BIT},//DAC_LD_48_49
|
|
{0x32A4, 0x0000, AR2020_REG_VALUE_16BIT},//CRM_CTRL
|
|
{0x328E, 0x0004, AR2020_REG_VALUE_16BIT},//ADDR_CTRL
|
|
{0x333C, 0x0001, AR2020_REG_VALUE_16BIT},//DYNAMIC_CTRL
|
|
{0x301A, 0x0000, AR2020_REG_VALUE_16BIT},//RESET_REGISTER
|
|
{0x3600, 0x94DF, AR2020_REG_VALUE_16BIT},//FDOC_CTRL
|
|
{0x3616, 0x0000, AR2020_REG_VALUE_16BIT},//FDOC_CTRL2
|
|
{0x3700, 0x0001, AR2020_REG_VALUE_16BIT},//PIX_DEF_ID
|
|
{0x3980, 0x0003, AR2020_REG_VALUE_16BIT},//PIX_DEF_CORR
|
|
{0x36C0, 0x0001, AR2020_REG_VALUE_16BIT},//DIGITAL_GAIN_CTRL
|
|
{0x36DE, 0x002A, AR2020_REG_VALUE_16BIT},//DATA_PEDESTAL1
|
|
{0x301A, 0x0008, AR2020_REG_VALUE_16BIT},//RESET_REGISTER
|
|
{0x4600, 0x0333, AR2020_REG_VALUE_16BIT},//LISREG_CTRL
|
|
{0x4602, 0x311C, AR2020_REG_VALUE_16BIT},//LISREG0_CTRL
|
|
{0x4604, 0x090B, AR2020_REG_VALUE_16BIT},//LISREG0_DATA0N1
|
|
{0x4606, 0x0009, AR2020_REG_VALUE_16BIT},//LISREG0_DATA2
|
|
{0x4608, 0x3206, AR2020_REG_VALUE_16BIT},//LISREG1_CTRL
|
|
{0x460A, 0xBCBC, AR2020_REG_VALUE_16BIT},//LISREG1_DATA0N1
|
|
{0x460C, 0x00BE, AR2020_REG_VALUE_16BIT},//LISREG1_DATA2
|
|
{0x460E, 0x3112, AR2020_REG_VALUE_16BIT},//LISREG2_CTRL
|
|
{0x4610, 0x5AFA, AR2020_REG_VALUE_16BIT},//LISREG2_DATA0N1
|
|
{0x4612, 0x005A, AR2020_REG_VALUE_16BIT},//LISREG2_DATA2
|
|
{0x3340, 0x0C60, AR2020_REG_VALUE_16BIT},//OTPM_CTRL
|
|
{0x3340, 0x1C60, AR2020_REG_VALUE_16BIT},//OTPM_CTRL
|
|
{0x0101, 0x01, AR2020_REG_VALUE_08BIT},//Bing added, this is for H mirror FLIP.
|
|
{0x0100, 0x01, AR2020_REG_VALUE_08BIT},//MODE_SELECT
|
|
{0x44D6, 0xB206, AR2020_REG_VALUE_16BIT},//DAC_LD_32_33
|
|
|
|
{REG_NULL, 0x00, AR2020_REG_VALUE_16BIT},
|
|
};
|
|
|
|
static const struct regval ar2020_hdr10bit_5120x3840_22fps_8lane_regs[] = {
|
|
{REG_DELAY, 2000, AR2020_REG_VALUE_16BIT},
|
|
{0x44D6, 0xF206, AR2020_REG_VALUE_16BIT},//DAC_LD_32_33
|
|
{0x0100, 0x00, AR2020_REG_VALUE_08BIT},//MODE_SELECT
|
|
{0x0304, 0x0002, AR2020_REG_VALUE_16BIT},//VT_PRE_PLL_CLK_DIV
|
|
{0x0306, 0x0067, AR2020_REG_VALUE_16BIT},//VT_PLL_MULTIPLIER
|
|
{0x0300, 0x0006, AR2020_REG_VALUE_16BIT},//VT_PIX_CLK_DIV
|
|
{0x0302, 0x0001, AR2020_REG_VALUE_16BIT},//VT_SYS_CLK_DIV
|
|
{0x030C, 0x0007, AR2020_REG_VALUE_16BIT},//OP_PRE_PLL_CLK_DIV
|
|
{0x030E, 0x01A4, AR2020_REG_VALUE_16BIT},//OP_PLL_MULTIPLIER
|
|
{0x0308, 0x0005, AR2020_REG_VALUE_16BIT},//OP_PIX_CLK_DIV
|
|
{0x030A, 0x0002, AR2020_REG_VALUE_16BIT},//OP_SYS_CLK_DIV
|
|
{0x0344, 0x0008, AR2020_REG_VALUE_16BIT},//X_ADDR_START
|
|
{0x0348, 0x1407, AR2020_REG_VALUE_16BIT},//X_ADDR_END
|
|
{0x0346, 0x0008, AR2020_REG_VALUE_16BIT},//Y_ADDR_START
|
|
{0x034A, 0x0F07, AR2020_REG_VALUE_16BIT},//Y_ADDR_END
|
|
{0x034C, 0x1400, AR2020_REG_VALUE_16BIT},//X_OUTPUT_SIZE
|
|
{0x034E, 0x0F00, AR2020_REG_VALUE_16BIT},//Y_OUTPUT_SIZE
|
|
{0x0380, 0x0001, AR2020_REG_VALUE_16BIT},//X_EVEN_INC
|
|
{0x0382, 0x0001, AR2020_REG_VALUE_16BIT},//X_ODD_INC
|
|
{0x0384, 0x0001, AR2020_REG_VALUE_16BIT},//Y_EVEN_INC
|
|
{0x0386, 0x0001, AR2020_REG_VALUE_16BIT},//Y_ODD_INC
|
|
{0x0900, 0x00, AR2020_REG_VALUE_08BIT},//BINNING_MODE
|
|
{0x0901, 0x11, AR2020_REG_VALUE_08BIT},//BINNING_TYPE
|
|
{0x0342, 0x1FC0, AR2020_REG_VALUE_16BIT},//LINE_LENGTH_PCK
|
|
{0x0340, 0x1E3C, AR2020_REG_VALUE_16BIT},//FRAME_LENGTH_LINES
|
|
{0x0202, 0x00E8, AR2020_REG_VALUE_16BIT},//COARSE_INTEGRATION_TIME
|
|
{0x0112, 0x0A0A, AR2020_REG_VALUE_16BIT},//CSI_DATA_FORMAT
|
|
{0x0114, 0x07, AR2020_REG_VALUE_08BIT},//CSI_LANE_MODE
|
|
{0x0800, 0x0D, AR2020_REG_VALUE_08BIT},//TCLK_POST
|
|
{0x0801, 0x07, AR2020_REG_VALUE_08BIT},//THS_PREPARE
|
|
{0x0802, 0x0C, AR2020_REG_VALUE_08BIT},//THS_ZERO_MIN
|
|
{0x0803, 0x09, AR2020_REG_VALUE_08BIT},//THS_TRAIL
|
|
{0x0804, 0x0B, AR2020_REG_VALUE_08BIT},//TCLK_TRAIL_MIN
|
|
{0x0805, 0x06, AR2020_REG_VALUE_08BIT},//TCLK_PREPARE
|
|
{0x0806, 0x24, AR2020_REG_VALUE_08BIT},//TCLK_ZERO
|
|
{0x0807, 0x07, AR2020_REG_VALUE_08BIT},//TLPX
|
|
{0x082A, 0x0F, AR2020_REG_VALUE_08BIT},//TWAKEUP
|
|
{0x082B, 0x0C, AR2020_REG_VALUE_08BIT},//TINIT
|
|
{0x082C, 0x0D, AR2020_REG_VALUE_08BIT},//THS_EXIT
|
|
{0x3F06, 0x00C0, AR2020_REG_VALUE_16BIT},//MIPI_TIMING_2
|
|
{0x3F0A, 0xA000, AR2020_REG_VALUE_16BIT},//MIPI_TIMING_4
|
|
{0x3F0C, 0x000A, AR2020_REG_VALUE_16BIT},//MIPI_TIMING_5
|
|
{0x3F20, 0x8080, AR2020_REG_VALUE_16BIT},//MIPI_PHY_TRIM_MSB
|
|
{0x3F1E, 0x0004, AR2020_REG_VALUE_16BIT},//MIPI_PHY_TRIM_LSB
|
|
{0x3F1A, 0x102B, AR2020_REG_VALUE_16BIT},
|
|
{0x3f22, 0x3806, AR2020_REG_VALUE_16BIT},
|
|
{0x3040, 0x0010, AR2020_REG_VALUE_16BIT},//READ_MODE
|
|
{0x3042, 0x80F1, AR2020_REG_VALUE_16BIT},//T1_TO_T2_DIST_CTRL
|
|
{0x0220, 0x73, AR2020_REG_VALUE_08BIT},//HDR_MODE
|
|
{0x3F18, 0x7B70, AR2020_REG_VALUE_16BIT},//MIPI_JPEG_PN9_DATA_TYPE
|
|
{0x4000, 0x0114, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_00
|
|
{0x4002, 0x1A25, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_02
|
|
{0x4004, 0x3DFF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_04
|
|
{0x4006, 0xFFFF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_06
|
|
{0x4008, 0x0A35, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_08
|
|
{0x400A, 0x10EF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_0A
|
|
{0x400C, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_0C
|
|
{0x400E, 0x30D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_0E
|
|
{0x4010, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10
|
|
{0x4012, 0xB5F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12
|
|
{0x4014, 0x0085, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14
|
|
{0x4016, 0xF004, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16
|
|
{0x4018, 0x9A89, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18
|
|
{0x401A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A
|
|
{0x401C, 0x9997, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C
|
|
{0x401E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E
|
|
{0x4020, 0x30C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20
|
|
{0x4022, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22
|
|
{0x4024, 0x82F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24
|
|
{0x4026, 0x0030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26
|
|
{0x4028, 0x18F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28
|
|
{0x402A, 0x0320, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A
|
|
{0x402C, 0x58F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C
|
|
{0x402E, 0x089C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E
|
|
{0x4030, 0xF010, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30
|
|
{0x4032, 0x99B6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32
|
|
{0x4034, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34
|
|
{0x4036, 0xB498, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36
|
|
{0x4038, 0xA096, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38
|
|
{0x403A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A
|
|
{0x403C, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C
|
|
{0x403E, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E
|
|
{0x4040, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40
|
|
{0x4042, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42
|
|
{0x4044, 0x209D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44
|
|
{0x4046, 0x8C08, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46
|
|
{0x4048, 0x08F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48
|
|
{0x404A, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A
|
|
{0x404C, 0x008F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4C
|
|
{0x404E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4E
|
|
{0x4050, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_50
|
|
{0x4052, 0x0488, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_52
|
|
{0x4054, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_54
|
|
{0x4056, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_56
|
|
{0x4058, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_58
|
|
{0x405A, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_5A
|
|
{0x405C, 0x0290, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_5C
|
|
{0x405E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_5E
|
|
{0x4060, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_60
|
|
{0x4062, 0x2EA3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_62
|
|
{0x4064, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_64
|
|
{0x4066, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_66
|
|
{0x4068, 0x089D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_68
|
|
{0x406A, 0xF075, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_6A
|
|
{0x406C, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_6C
|
|
{0x406E, 0x4070, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_6E
|
|
{0x4070, 0x216D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_70
|
|
{0x4072, 0x1CF6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_72
|
|
{0x4074, 0x8B00, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_74
|
|
{0x4076, 0x5186, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_76
|
|
{0x4078, 0x1300, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_78
|
|
{0x407A, 0x0205, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_7A
|
|
{0x407C, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_7C
|
|
{0x407E, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_7E
|
|
{0x4080, 0x8387, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_80
|
|
{0x4082, 0xF006, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_82
|
|
{0x4084, 0x8702, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_84
|
|
{0x4086, 0x0D02, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_86
|
|
{0x4088, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_88
|
|
{0x408A, 0x0383, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_8A
|
|
{0x408C, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_8C
|
|
{0x408E, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_8E
|
|
{0x4090, 0x0213, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_90
|
|
{0x4092, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_92
|
|
{0x4094, 0xD887, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_94
|
|
{0x4096, 0x020D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_96
|
|
{0x4098, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_98
|
|
{0x409A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_9A
|
|
{0x409C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_9C
|
|
{0x409E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_9E
|
|
{0x40A0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A0
|
|
{0x40A2, 0x0401, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A2
|
|
{0x40A4, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A4
|
|
{0x40A6, 0x82F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A6
|
|
{0x40A8, 0x0883, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A8
|
|
{0x40AA, 0xF009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_AA
|
|
{0x40AC, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_AC
|
|
{0x40AE, 0x2985, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_AE
|
|
{0x40B0, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B0
|
|
{0x40B2, 0x2A87, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B2
|
|
{0x40B4, 0xF63E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B4
|
|
{0x40B6, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B6
|
|
{0x40B8, 0x0801, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B8
|
|
{0x40BA, 0x40F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_BA
|
|
{0x40BC, 0x0800, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_BC
|
|
{0x40BE, 0x48F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_BE
|
|
{0x40C0, 0x0882, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C0
|
|
{0x40C2, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C2
|
|
{0x40C4, 0x0401, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C4
|
|
{0x40C6, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C6
|
|
{0x40C8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C8
|
|
{0x40CA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_CA
|
|
{0x40CC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_CC
|
|
{0x40CE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_CE
|
|
{0x40D0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D0
|
|
{0x40D2, 0x0401, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D2
|
|
{0x40D4, 0xF015, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D4
|
|
{0x40D6, 0x002C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D6
|
|
{0x40D8, 0xF00E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D8
|
|
{0x40DA, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_DA
|
|
{0x40DC, 0x0687, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_DC
|
|
{0x40DE, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_DE
|
|
{0x40E0, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E0
|
|
{0x40E2, 0x61E8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E2
|
|
{0x40E4, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E4
|
|
{0x40E6, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E6
|
|
{0x40E8, 0x3480, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E8
|
|
{0x40EA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_EA
|
|
{0x40EC, 0x3240, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_EC
|
|
{0x40EE, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_EE
|
|
{0x40F0, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F0
|
|
{0x40F2, 0xF00E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F2
|
|
{0x40F4, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F4
|
|
{0x40F6, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F6
|
|
{0x40F8, 0x3240, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F8
|
|
{0x40FA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_FA
|
|
{0x40FC, 0x3480, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_FC
|
|
{0x40FE, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_FE
|
|
{0x4100, 0xC0E6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_100
|
|
{0x4102, 0xF004, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_102
|
|
{0x4104, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_104
|
|
{0x4106, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_106
|
|
{0x4108, 0xB0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_108
|
|
{0x410A, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10A
|
|
{0x410C, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10C
|
|
{0x410E, 0x86F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10E
|
|
{0x4110, 0x0086, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_110
|
|
{0x4112, 0xF089, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_112
|
|
{0x4114, 0xB0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_114
|
|
{0x4116, 0x00E9, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_116
|
|
{0x4118, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_118
|
|
{0x411A, 0x8AF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_11A
|
|
{0x411C, 0x0000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_11C
|
|
{0x411E, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_11E
|
|
{0x4120, 0x00E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_120
|
|
{0x4122, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_122
|
|
{0x4124, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_124
|
|
{0x4126, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_126
|
|
{0x4128, 0x0A35, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_128
|
|
{0x412A, 0x10EF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12A
|
|
{0x412C, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12C
|
|
{0x412E, 0x30D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12E
|
|
{0x4130, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_130
|
|
{0x4132, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_132
|
|
{0x4134, 0x049A, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_134
|
|
{0x4136, 0x89F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_136
|
|
{0x4138, 0x0099, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_138
|
|
{0x413A, 0x97F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_13A
|
|
{0x413C, 0x0030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_13C
|
|
{0x413E, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_13E
|
|
{0x4140, 0x0082, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_140
|
|
{0x4142, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_142
|
|
{0x4144, 0x3018, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_144
|
|
{0x4146, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_146
|
|
{0x4148, 0xB520, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_148
|
|
{0x414A, 0x58F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14A
|
|
{0x414C, 0x089C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14C
|
|
{0x414E, 0xF010, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14E
|
|
{0x4150, 0x99B6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_150
|
|
{0x4152, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_152
|
|
{0x4154, 0xB498, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_154
|
|
{0x4156, 0xA096, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_156
|
|
{0x4158, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_158
|
|
{0x415A, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_15A
|
|
{0x415C, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_15C
|
|
{0x415E, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_15E
|
|
{0x4160, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_160
|
|
{0x4162, 0x209D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_162
|
|
{0x4164, 0x8C08, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_164
|
|
{0x4166, 0x08F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_166
|
|
{0x4168, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_168
|
|
{0x416A, 0x008F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16A
|
|
{0x416C, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16C
|
|
{0x416E, 0x0188, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16E
|
|
{0x4170, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_170
|
|
{0x4172, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_172
|
|
{0x4174, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_174
|
|
{0x4176, 0x0290, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_176
|
|
{0x4178, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_178
|
|
{0x417A, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_17A
|
|
{0x417C, 0x2DA3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_17C
|
|
{0x417E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_17E
|
|
{0x4180, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_180
|
|
{0x4182, 0x089D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_182
|
|
{0x4184, 0xF06D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_184
|
|
{0x4186, 0x4070, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_186
|
|
{0x4188, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_188
|
|
{0x418A, 0x214D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18A
|
|
{0x418C, 0x1FF6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18C
|
|
{0x418E, 0x0851, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18E
|
|
{0x4190, 0x0245, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_190
|
|
{0x4192, 0x9D36, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_192
|
|
{0x4194, 0xD8F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_194
|
|
{0x4196, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_196
|
|
{0x4198, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_198
|
|
{0x419A, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_19A
|
|
{0x419C, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_19C
|
|
{0x419E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_19E
|
|
{0x41A0, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A0
|
|
{0x41A2, 0x020D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A2
|
|
{0x41A4, 0x0205, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A4
|
|
{0x41A6, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A6
|
|
{0x41A8, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A8
|
|
{0x41AA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1AA
|
|
{0x41AC, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1AC
|
|
{0x41AE, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1AE
|
|
{0x41B0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B0
|
|
{0x41B2, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B2
|
|
{0x41B4, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B4
|
|
{0x41B6, 0xD802, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B6
|
|
{0x41B8, 0x0D02, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B8
|
|
{0x41BA, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1BA
|
|
{0x41BC, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1BC
|
|
{0x41BE, 0xD8F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1BE
|
|
{0x41C0, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C0
|
|
{0x41C2, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C2
|
|
{0x41C4, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C4
|
|
{0x41C6, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C6
|
|
{0x41C8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C8
|
|
{0x41CA, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1CA
|
|
{0x41CC, 0x020D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1CC
|
|
{0x41CE, 0x0205, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1CE
|
|
{0x41D0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D0
|
|
{0x41D2, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D2
|
|
{0x41D4, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D4
|
|
{0x41D6, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D6
|
|
{0x41D8, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D8
|
|
{0x41DA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1DA
|
|
{0x41DC, 0x8713, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1DC
|
|
{0x41DE, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1DE
|
|
{0x41E0, 0xD802, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E0
|
|
{0x41E2, 0x0DE0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E2
|
|
{0x41E4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E4
|
|
{0x41E6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E6
|
|
{0x41E8, 0x9F13, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E8
|
|
{0x41EA, 0x0041, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1EA
|
|
{0x41EC, 0x80F3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1EC
|
|
{0x41EE, 0xF213, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1EE
|
|
{0x41F0, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F0
|
|
{0x41F2, 0x13B8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F2
|
|
{0x41F4, 0xF04C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F4
|
|
{0x41F6, 0x9FF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F6
|
|
{0x41F8, 0x00B7, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F8
|
|
{0x41FA, 0xF006, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1FA
|
|
{0x41FC, 0x0035, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1FC
|
|
{0x41FE, 0x10AF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1FE
|
|
{0x4200, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_200
|
|
{0x4202, 0x30C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_202
|
|
{0x4204, 0xB2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_204
|
|
{0x4206, 0x01B5, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_206
|
|
{0x4208, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_208
|
|
{0x420A, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20A
|
|
{0x420C, 0x0292, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20C
|
|
{0x420E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20E
|
|
{0x4210, 0x9A8B, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_210
|
|
{0x4212, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_212
|
|
{0x4214, 0x9997, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_214
|
|
{0x4216, 0xF007, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_216
|
|
{0x4218, 0xB6F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_218
|
|
{0x421A, 0x0020, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_21A
|
|
{0x421C, 0x5830, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_21C
|
|
{0x421E, 0xC040, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_21E
|
|
{0x4220, 0x1282, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_220
|
|
{0x4222, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_222
|
|
{0x4224, 0x9CF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_224
|
|
{0x4226, 0x01B2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_226
|
|
{0x4228, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_228
|
|
{0x422A, 0xB8F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22A
|
|
{0x422C, 0x0799, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22C
|
|
{0x422E, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22E
|
|
{0x4230, 0x98F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_230
|
|
{0x4232, 0x0296, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_232
|
|
{0x4234, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_234
|
|
{0x4236, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_236
|
|
{0x4238, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_238
|
|
{0x423A, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_23A
|
|
{0x423C, 0x02A1, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_23C
|
|
{0x423E, 0xF01F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_23E
|
|
{0x4240, 0x1009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_240
|
|
{0x4242, 0x2220, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_242
|
|
{0x4244, 0x0808, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_244
|
|
{0x4246, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_246
|
|
{0x4248, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_248
|
|
{0x424A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24A
|
|
{0x424C, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24C
|
|
{0x424E, 0x0788, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24E
|
|
{0x4250, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_250
|
|
{0x4252, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_252
|
|
{0x4254, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_254
|
|
{0x4256, 0x0290, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_256
|
|
{0x4258, 0xF016, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_258
|
|
{0x425A, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_25A
|
|
{0x425C, 0x11A3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_25C
|
|
{0x425E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_25E
|
|
{0x4260, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_260
|
|
{0x4262, 0x089D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_262
|
|
{0x4264, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_264
|
|
{0x4266, 0xA1F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_266
|
|
{0x4268, 0x20A1, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_268
|
|
{0x426A, 0xF006, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26A
|
|
{0x426C, 0x4300, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26C
|
|
{0x426E, 0xF049, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26E
|
|
{0x4270, 0x4014, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_270
|
|
{0x4272, 0x8B8E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_272
|
|
{0x4274, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_274
|
|
{0x4276, 0x0802, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_276
|
|
{0x4278, 0x02F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_278
|
|
{0x427A, 0x00A6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_27A
|
|
{0x427C, 0xF013, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_27C
|
|
{0x427E, 0xB283, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_27E
|
|
{0x4280, 0x9C36, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_280
|
|
{0x4282, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_282
|
|
{0x4284, 0x0636, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_284
|
|
{0x4286, 0x009C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_286
|
|
{0x4288, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_288
|
|
{0x428A, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28A
|
|
{0x428C, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28C
|
|
{0x428E, 0xA0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28E
|
|
{0x4290, 0x0630, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_290
|
|
{0x4292, 0x18F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_292
|
|
{0x4294, 0x02A3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_294
|
|
{0x4296, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_296
|
|
{0x4298, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_298
|
|
{0x429A, 0x0243, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_29A
|
|
{0x429C, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_29C
|
|
{0x429E, 0x049D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_29E
|
|
{0x42A0, 0xF078, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A0
|
|
{0x42A2, 0x3018, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A2
|
|
{0x42A4, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A4
|
|
{0x42A6, 0x9D82, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A6
|
|
{0x42A8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A8
|
|
{0x42AA, 0x9030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2AA
|
|
{0x42AC, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2AC
|
|
{0x42AE, 0x1130, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2AE
|
|
{0x42B0, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B0
|
|
{0x42B2, 0x0082, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B2
|
|
{0x42B4, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B4
|
|
{0x42B6, 0x1009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B6
|
|
{0x42B8, 0xF02A, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B8
|
|
{0x42BA, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2BA
|
|
{0x42BC, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2BC
|
|
{0x42BE, 0x3018, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2BE
|
|
{0x42C0, 0xF007, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C0
|
|
{0x42C2, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C2
|
|
{0x42C4, 0x1C8C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C4
|
|
{0x42C6, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C6
|
|
{0x42C8, 0x301F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C8
|
|
{0x42CA, 0x216D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2CA
|
|
{0x42CC, 0x0A51, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2CC
|
|
{0x42CE, 0x1FEA, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2CE
|
|
{0x42D0, 0x8640, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D0
|
|
{0x42D2, 0xE29F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D2
|
|
{0x42D4, 0xF009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D4
|
|
{0x42D6, 0x0005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D6
|
|
{0x42D8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D8
|
|
{0x42DA, 0x30C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2DA
|
|
{0x42DC, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2DC
|
|
{0x42DE, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2DE
|
|
{0x42E0, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E0
|
|
{0x42E2, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E2
|
|
{0x42E4, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E4
|
|
{0x42E6, 0xF007, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E6
|
|
{0x42E8, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E8
|
|
{0x42EA, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2EA
|
|
{0x42EC, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2EC
|
|
{0x42EE, 0x0000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2EE
|
|
{0x42F0, 0x0DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F0
|
|
{0x42F2, 0x0000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F2
|
|
{0x42F4, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F4
|
|
{0x42F6, 0x0030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F6
|
|
{0x42F8, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F8
|
|
{0x42FA, 0x0183, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2FA
|
|
{0x42FC, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2FC
|
|
{0x42FE, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2FE
|
|
{0x4300, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_300
|
|
{0x4302, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_302
|
|
{0x4304, 0x0787, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_304
|
|
{0x4306, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_306
|
|
{0x4308, 0x36C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_308
|
|
{0x430A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30A
|
|
{0x430C, 0x000F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30C
|
|
{0x430E, 0xF42A, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30E
|
|
{0x4310, 0x4180, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_310
|
|
{0x4312, 0x1300, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_312
|
|
{0x4314, 0x9FF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_314
|
|
{0x4316, 0x00E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_316
|
|
{0x4318, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_318
|
|
{0x431A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_31A
|
|
{0x431C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_31C
|
|
{0x431E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_31E
|
|
{0x4320, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_320
|
|
{0x4322, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_322
|
|
{0x4324, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_324
|
|
{0x4326, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_326
|
|
{0x4328, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_328
|
|
{0x432A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32A
|
|
{0x432C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32C
|
|
{0x432E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32E
|
|
{0x4330, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_330
|
|
{0x4332, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_332
|
|
{0x4334, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_334
|
|
{0x4336, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_336
|
|
{0x4338, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_338
|
|
{0x433A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_33A
|
|
{0x433C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_33C
|
|
{0x433E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_33E
|
|
{0x4340, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_340
|
|
{0x4342, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_342
|
|
{0x4344, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_344
|
|
{0x4346, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_346
|
|
{0x4348, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_348
|
|
{0x434A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34A
|
|
{0x434C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34C
|
|
{0x434E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34E
|
|
{0x4350, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_350
|
|
{0x4352, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_352
|
|
{0x4354, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_354
|
|
{0x4356, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_356
|
|
{0x4358, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_358
|
|
{0x435A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_35A
|
|
{0x435C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_35C
|
|
{0x435E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_35E
|
|
{0x4360, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_360
|
|
{0x4362, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_362
|
|
{0x4364, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_364
|
|
{0x4366, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_366
|
|
{0x4368, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_368
|
|
{0x436A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36A
|
|
{0x436C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36C
|
|
{0x436E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36E
|
|
{0x4370, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_370
|
|
{0x4372, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_372
|
|
{0x4374, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_374
|
|
{0x4376, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_376
|
|
{0x4378, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_378
|
|
{0x437A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_37A
|
|
{0x437C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_37C
|
|
{0x437E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_37E
|
|
{0x4380, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_380
|
|
{0x4382, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_382
|
|
{0x4384, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_384
|
|
{0x4386, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_386
|
|
{0x4388, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_388
|
|
{0x438A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38A
|
|
{0x438C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38C
|
|
{0x438E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38E
|
|
{0x4390, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_390
|
|
{0x4392, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_392
|
|
{0x4394, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_394
|
|
{0x4396, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_396
|
|
{0x4398, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_398
|
|
{0x439A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_39A
|
|
{0x439C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_39C
|
|
{0x439E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_39E
|
|
{0x43A0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A0
|
|
{0x43A2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A2
|
|
{0x43A4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A4
|
|
{0x43A6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A6
|
|
{0x43A8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A8
|
|
{0x43AA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3AA
|
|
{0x43AC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3AC
|
|
{0x43AE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3AE
|
|
{0x43B0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B0
|
|
{0x43B2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B2
|
|
{0x43B4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B4
|
|
{0x43B6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B6
|
|
{0x43B8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B8
|
|
{0x43BA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3BA
|
|
{0x43BC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3BC
|
|
{0x43BE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3BE
|
|
{0x43C0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C0
|
|
{0x43C2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C2
|
|
{0x43C4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C4
|
|
{0x43C6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C6
|
|
{0x43C8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C8
|
|
{0x43CA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3CA
|
|
{0x43CC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3CC
|
|
{0x43CE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3CE
|
|
{0x43D0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D0
|
|
{0x43D2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D2
|
|
{0x43D4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D4
|
|
{0x43D6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D6
|
|
{0x43D8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D8
|
|
{0x43DA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3DA
|
|
{0x43DC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3DC
|
|
{0x43DE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3DE
|
|
{0x43E0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E0
|
|
{0x43E2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E2
|
|
{0x43E4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E4
|
|
{0x43E6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E6
|
|
{0x43E8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E8
|
|
{0x43EA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3EA
|
|
{0x43EC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3EC
|
|
{0x43EE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3EE
|
|
{0x43F0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F0
|
|
{0x43F2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F2
|
|
{0x43F4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F4
|
|
{0x43F6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F6
|
|
{0x43F8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F8
|
|
{0x43FA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3FA
|
|
{0x43FC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3FC
|
|
{0x43FE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3FE
|
|
{0x4400, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_400
|
|
{0x4402, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_402
|
|
{0x4404, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_404
|
|
{0x4406, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_406
|
|
{0x4408, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_408
|
|
{0x440A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40A
|
|
{0x440C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40C
|
|
{0x440E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40E
|
|
{0x4410, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_410
|
|
{0x4412, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_412
|
|
{0x4414, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_414
|
|
{0x4416, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_416
|
|
{0x4418, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_418
|
|
{0x441A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_41A
|
|
{0x441C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_41C
|
|
{0x441E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_41E
|
|
{0x4420, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_420
|
|
{0x4422, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_422
|
|
{0x4424, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_424
|
|
{0x4426, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_426
|
|
{0x4428, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_428
|
|
{0x442A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42A
|
|
{0x442C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42C
|
|
{0x442E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42E
|
|
{0x4430, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_430
|
|
{0x4432, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_432
|
|
{0x4434, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_434
|
|
{0x4436, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_436
|
|
{0x4438, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_438
|
|
{0x443A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_43A
|
|
{0x443C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_43C
|
|
{0x443E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_43E
|
|
{0x4440, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_440
|
|
{0x4442, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_442
|
|
{0x4444, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_444
|
|
{0x4446, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_446
|
|
{0x4448, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_448
|
|
{0x444A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44A
|
|
{0x444C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44C
|
|
{0x444E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44E
|
|
{0x4450, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_450
|
|
{0x4452, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_452
|
|
{0x4454, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_454
|
|
{0x4456, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_456
|
|
{0x4458, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_458
|
|
{0x445A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_45A
|
|
{0x445C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_45C
|
|
{0x445E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_45E
|
|
{0x4460, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_460
|
|
{0x4462, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_462
|
|
{0x4464, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_464
|
|
{0x4466, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_466
|
|
{0x4468, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_468
|
|
{0x446A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46A
|
|
{0x446C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46C
|
|
{0x446E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46E
|
|
{0x4470, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_470
|
|
{0x4472, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_472
|
|
{0x4474, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_474
|
|
{0x4476, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_476
|
|
{0x4478, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_478
|
|
{0x447A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_47A
|
|
{0x447C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_47C
|
|
{0x447E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_47E
|
|
{0x4480, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_480
|
|
{0x4482, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_482
|
|
{0x4484, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_484
|
|
{0x4486, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_486
|
|
{0x4488, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_488
|
|
{0x448A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48A
|
|
{0x448C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48C
|
|
{0x448E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48E
|
|
{0x4490, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_490
|
|
{0x4492, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_492
|
|
{0x4494, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_494
|
|
{0x4496, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_496
|
|
{0x4498, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_498
|
|
{0x449A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_49A
|
|
{0x449C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_49C
|
|
{0x449E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_49E
|
|
{0x44A0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A0
|
|
{0x44A2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A2
|
|
{0x44A4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A4
|
|
{0x44A6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A6
|
|
{0x44A8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A8
|
|
{0x44AA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4AA
|
|
{0x44AC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4AC
|
|
{0x44AE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4AE
|
|
{0x44B0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4B0
|
|
{0x44B2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4B2
|
|
{0x44B4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4B4
|
|
{0x5500, 0x0000, AR2020_REG_VALUE_16BIT},//AGAIN_LUT0
|
|
{0x5502, 0x0002, AR2020_REG_VALUE_16BIT},//AGAIN_LUT1
|
|
{0x5504, 0x0006, AR2020_REG_VALUE_16BIT},//AGAIN_LUT2
|
|
{0x5506, 0x0009, AR2020_REG_VALUE_16BIT},//AGAIN_LUT3
|
|
{0x5508, 0x000F, AR2020_REG_VALUE_16BIT},//AGAIN_LUT4
|
|
{0x550A, 0x0010, AR2020_REG_VALUE_16BIT},//AGAIN_LUT5
|
|
{0x550C, 0x0011, AR2020_REG_VALUE_16BIT},//AGAIN_LUT6
|
|
{0x550E, 0x0012, AR2020_REG_VALUE_16BIT},//AGAIN_LUT7
|
|
{0x5510, 0x0019, AR2020_REG_VALUE_16BIT},//AGAIN_LUT8
|
|
{0x5512, 0x0020, AR2020_REG_VALUE_16BIT},//AGAIN_LUT9
|
|
{0x5514, 0x0021, AR2020_REG_VALUE_16BIT},//AGAIN_LUT10
|
|
{0x5516, 0x0023, AR2020_REG_VALUE_16BIT},//AGAIN_LUT11
|
|
{0x5518, 0x0026, AR2020_REG_VALUE_16BIT},//AGAIN_LUT12
|
|
{0x551A, 0x002B, AR2020_REG_VALUE_16BIT},//AGAIN_LUT13
|
|
{0x551C, 0x002F, AR2020_REG_VALUE_16BIT},//AGAIN_LUT14
|
|
{0x551E, 0x0030, AR2020_REG_VALUE_16BIT},//AGAIN_LUT15
|
|
{0x5430, 0x0100, AR2020_REG_VALUE_16BIT},//GT2_COARSE0
|
|
{0x5432, 0x00E8, AR2020_REG_VALUE_16BIT},//GT2_COARSE1
|
|
{0x5434, 0x0123, AR2020_REG_VALUE_16BIT},//GT2_COARSE2
|
|
{0x5436, 0x0108, AR2020_REG_VALUE_16BIT},//GT2_COARSE3
|
|
{0x5438, 0x5125, AR2020_REG_VALUE_16BIT},//GT2_COARSE4
|
|
{0x543A, 0x510A, AR2020_REG_VALUE_16BIT},//GT2_COARSE5
|
|
{0x543C, 0x9133, AR2020_REG_VALUE_16BIT},//GT2_COARSE6
|
|
{0x543E, 0x9117, AR2020_REG_VALUE_16BIT},//GT2_COARSE7
|
|
{0x5440, 0xF130, AR2020_REG_VALUE_16BIT},//GT2_COARSE8
|
|
{0x5442, 0xF114, AR2020_REG_VALUE_16BIT},//GT2_COARSE9
|
|
{0x5444, 0xF186, AR2020_REG_VALUE_16BIT},//GT2_COARSE10
|
|
{0x5446, 0xF227, AR2020_REG_VALUE_16BIT},//GT2_COARSE11
|
|
{0x5448, 0xF30A, AR2020_REG_VALUE_16BIT},//GT2_COARSE12
|
|
{0x544A, 0xF44B, AR2020_REG_VALUE_16BIT},//GT2_COARSE13
|
|
{0x544C, 0xF611, AR2020_REG_VALUE_16BIT},//GT2_COARSE14
|
|
{0x544E, 0xF892, AR2020_REG_VALUE_16BIT},//GT2_COARSE15
|
|
{0x5450, 0xFC1B, AR2020_REG_VALUE_16BIT},//GT2_COARSE16
|
|
{0x5452, 0xFC1B, AR2020_REG_VALUE_16BIT},//GT2_COARSE17
|
|
{0x5454, 0x7772, AR2020_REG_VALUE_16BIT},//GT2_DCG_ATTN_SET0
|
|
{0x5456, 0x5557, AR2020_REG_VALUE_16BIT},//GT2_DCG_ATTN_SET1
|
|
{0x5458, 0x0005, AR2020_REG_VALUE_16BIT},//GT2_DCG_ATTN_SET2
|
|
{0x545A, 0xA550, AR2020_REG_VALUE_16BIT},//GT2_ZONE_SET0
|
|
{0x545C, 0xAAAA, AR2020_REG_VALUE_16BIT},//GT2_ZONE_SET1
|
|
{0x545E, 0x000A, AR2020_REG_VALUE_16BIT},//GT2_ZONE_SET2
|
|
{0x54A0, 0x0000, AR2020_REG_VALUE_16BIT},//ZT2_REG0_ADDR
|
|
{0x54A2, 0x0241, AR2020_REG_VALUE_16BIT},//ZT2_REG0_VALUE0
|
|
{0x54A4, 0x0841, AR2020_REG_VALUE_16BIT},//ZT2_REG0_VALUE1
|
|
{0x54A6, 0x0A41, AR2020_REG_VALUE_16BIT},//ZT2_REG0_VALUE2
|
|
{0x54D8, 0x0000, AR2020_REG_VALUE_16BIT},//ZT2_REG7_ADDR
|
|
{0x54DA, 0x54E2, AR2020_REG_VALUE_16BIT},//ZT2_REG7_VALUE0
|
|
{0x54DC, 0x54E3, AR2020_REG_VALUE_16BIT},//ZT2_REG7_VALUE1
|
|
{0x54DE, 0x54E3, AR2020_REG_VALUE_16BIT},//ZT2_REG7_VALUE2
|
|
{0x3060, 0x0007, AR2020_REG_VALUE_16BIT},//GAIN_TABLE_CTRL
|
|
{0x44BA, 0x0050, AR2020_REG_VALUE_16BIT},//DAC_LD_4_5
|
|
{0x44BC, 0xBCAA, AR2020_REG_VALUE_16BIT},//DAC_LD_6_7
|
|
{0x44C0, 0x4070, AR2020_REG_VALUE_16BIT},//DAC_LD_10_11
|
|
{0x44C4, 0x04D0, AR2020_REG_VALUE_16BIT},//DAC_LD_14_15
|
|
{0x44C6, 0x17E2, AR2020_REG_VALUE_16BIT},//DAC_LD_16_17
|
|
{0x44C8, 0x5A43, AR2020_REG_VALUE_16BIT},//DAC_LD_18_19
|
|
{0x44CA, 0x000E, AR2020_REG_VALUE_16BIT},//DAC_LD_20_21
|
|
{0x44CC, 0x7777, AR2020_REG_VALUE_16BIT},//DAC_LD_22_23
|
|
{0x44CE, 0x8BA4, AR2020_REG_VALUE_16BIT},//DAC_LD_24_25
|
|
{0x44D0, 0x1735, AR2020_REG_VALUE_16BIT},//DAC_LD_26_27
|
|
{0x44D4, 0x8000, AR2020_REG_VALUE_16BIT},//DAC_LD_30_31
|
|
{0x44D6, 0xF206, AR2020_REG_VALUE_16BIT},//DAC_LD_32_33
|
|
{0x44D8, 0xAAFA, AR2020_REG_VALUE_16BIT},//DAC_LD_34_35
|
|
{0x44DA, 0xE001, AR2020_REG_VALUE_16BIT},//DAC_LD_36_37
|
|
{0x44DC, 0x7480, AR2020_REG_VALUE_16BIT},//DAC_LD_38_39
|
|
{0x44DE, 0x9BBC, AR2020_REG_VALUE_16BIT},//DAC_LD_40_41
|
|
{0x44E0, 0x283C, AR2020_REG_VALUE_16BIT},//DAC_LD_42_43
|
|
{0x44E2, 0x2821, AR2020_REG_VALUE_16BIT},//DAC_LD_44_45
|
|
{0x44E4, 0x8000, AR2020_REG_VALUE_16BIT},//DAC_LD_46_47
|
|
{0x44E6, 0x703F, AR2020_REG_VALUE_16BIT},//DAC_LD_48_49
|
|
{0x32A4, 0x0000, AR2020_REG_VALUE_16BIT},//CRM_CTRL
|
|
{0x328E, 0x0004, AR2020_REG_VALUE_16BIT},//ADDR_CTRL
|
|
{0x333C, 0x0001, AR2020_REG_VALUE_16BIT},//DYNAMIC_CTRL
|
|
{0x301A, 0x0000, AR2020_REG_VALUE_16BIT},//RESET_REGISTER
|
|
{0x3600, 0x94DF, AR2020_REG_VALUE_16BIT},//FDOC_CTRL
|
|
{0x3616, 0x0000, AR2020_REG_VALUE_16BIT},//FDOC_CTRL2
|
|
{0x3700, 0x0001, AR2020_REG_VALUE_16BIT},//PIX_DEF_ID
|
|
{0x3980, 0x0003, AR2020_REG_VALUE_16BIT},//PIX_DEF_CORR
|
|
{0x36C0, 0x0001, AR2020_REG_VALUE_16BIT},//DIGITAL_GAIN_CTRL
|
|
{0x36DE, 0x002A, AR2020_REG_VALUE_16BIT},//DATA_PEDESTAL1
|
|
{0x301A, 0x0008, AR2020_REG_VALUE_16BIT},//RESET_REGISTER
|
|
{0x4600, 0x0333, AR2020_REG_VALUE_16BIT},//LISREG_CTRL
|
|
{0x4602, 0x311C, AR2020_REG_VALUE_16BIT},//LISREG0_CTRL
|
|
{0x4604, 0x090B, AR2020_REG_VALUE_16BIT},//LISREG0_DATA0N1
|
|
{0x4606, 0x0009, AR2020_REG_VALUE_16BIT},//LISREG0_DATA2
|
|
{0x4608, 0x3206, AR2020_REG_VALUE_16BIT},//LISREG1_CTRL
|
|
{0x460A, 0xBCBC, AR2020_REG_VALUE_16BIT},//LISREG1_DATA0N1
|
|
{0x460C, 0x00BE, AR2020_REG_VALUE_16BIT},//LISREG1_DATA2
|
|
{0x460E, 0x3112, AR2020_REG_VALUE_16BIT},//LISREG2_CTRL
|
|
{0x4610, 0x5AFA, AR2020_REG_VALUE_16BIT},//LISREG2_DATA0N1
|
|
{0x4612, 0x005A, AR2020_REG_VALUE_16BIT},//LISREG2_DATA2
|
|
{0x3340, 0x0C60, AR2020_REG_VALUE_16BIT},//OTPM_CTRL
|
|
{0x3340, 0x1C60, AR2020_REG_VALUE_16BIT},//OTPM_CTRL
|
|
{0x0202, 0x079E, AR2020_REG_VALUE_16BIT},//COARSE_INTEGRATION_TIME
|
|
{0x0224, 0x00C3, AR2020_REG_VALUE_16BIT},//SHORT_COARSE_INTEGRATION_TIME
|
|
{0x0100, 0x01, AR2020_REG_VALUE_08BIT},//MODE_SELECT
|
|
{0x44D6, 0xB206, AR2020_REG_VALUE_16BIT},//DAC_LD_32_33
|
|
|
|
{REG_NULL, 0x00, AR2020_REG_VALUE_16BIT},
|
|
};
|
|
|
|
static const struct regval ar2020_linear_8lane_global_regs[] = {
|
|
{REG_DELAY, 2000, AR2020_REG_VALUE_16BIT},
|
|
{0x44D6, 0xF206, AR2020_REG_VALUE_16BIT},//DAC_LD_32_33
|
|
{0x0100, 0x00, AR2020_REG_VALUE_08BIT},//MODE_SELECT
|
|
{0x0304, 0x0002, AR2020_REG_VALUE_16BIT},//VT_PRE_PLL_CLK_DIV
|
|
{0x0306, 0x0067, AR2020_REG_VALUE_16BIT},//VT_PLL_MULTIPLIER
|
|
{0x0300, 0x0006, AR2020_REG_VALUE_16BIT},//VT_PIX_CLK_DIV
|
|
{0x0302, 0x0001, AR2020_REG_VALUE_16BIT},//VT_SYS_CLK_DIV
|
|
{0x030C, 0x0007, AR2020_REG_VALUE_16BIT},//OP_PRE_PLL_CLK_DIV
|
|
{0x030E, 0x01A4, AR2020_REG_VALUE_16BIT},//OP_PLL_MULTIPLIER
|
|
{0x0308, 0x0005, AR2020_REG_VALUE_16BIT},//OP_PIX_CLK_DIV
|
|
{0x030A, 0x0002, AR2020_REG_VALUE_16BIT},//OP_SYS_CLK_DIV
|
|
{0x0344, 0x0008, AR2020_REG_VALUE_16BIT},//X_ADDR_START
|
|
{0x0348, 0x1407, AR2020_REG_VALUE_16BIT},//X_ADDR_END
|
|
{0x0346, 0x0008, AR2020_REG_VALUE_16BIT},//Y_ADDR_START
|
|
{0x034A, 0x0F07, AR2020_REG_VALUE_16BIT},//Y_ADDR_END
|
|
{0x034C, 0x1400, AR2020_REG_VALUE_16BIT},//X_OUTPUT_SIZE
|
|
{0x034E, 0x0F00, AR2020_REG_VALUE_16BIT},//Y_OUTPUT_SIZE
|
|
{0x0380, 0x0001, AR2020_REG_VALUE_16BIT},//X_EVEN_INC
|
|
{0x0382, 0x0001, AR2020_REG_VALUE_16BIT},//X_ODD_INC
|
|
{0x0386, 0x0001, AR2020_REG_VALUE_16BIT},//Y_ODD_INC
|
|
{0x0384, 0x0001, AR2020_REG_VALUE_16BIT},//Y_EVEN_INC
|
|
{0x0900, 0x00, AR2020_REG_VALUE_08BIT},//BINNING_MODE
|
|
{0x0901, 0x11, AR2020_REG_VALUE_08BIT},//BINNING_TYPE
|
|
{0x0342, 0x1FC0, AR2020_REG_VALUE_16BIT},//LINE_LENGTH_PCK
|
|
{0x0340, 0x0F1E, AR2020_REG_VALUE_16BIT},//FRAME_LENGTH_LINES
|
|
{0x0202, 0x0B2D, AR2020_REG_VALUE_16BIT},//COARSE_INTEGRATION_TIME
|
|
{0x0112, 0x0A0A, AR2020_REG_VALUE_16BIT},//CSI_DATA_FORMAT
|
|
{0x0114, 0x07, AR2020_REG_VALUE_08BIT},//CSI_LANE_MODE
|
|
{0x0800, 0x0D, AR2020_REG_VALUE_08BIT},//TCLK_POST
|
|
{0x0801, 0x07, AR2020_REG_VALUE_08BIT},//THS_PREPARE
|
|
{0x0802, 0x0C, AR2020_REG_VALUE_08BIT},//THS_ZERO_MIN
|
|
{0x0803, 0x09, AR2020_REG_VALUE_08BIT},//THS_TRAIL
|
|
{0x0804, 0x0B, AR2020_REG_VALUE_08BIT},//TCLK_TRAIL_MIN
|
|
{0x0805, 0x06, AR2020_REG_VALUE_08BIT},//TCLK_PREPARE
|
|
{0x0806, 0x24, AR2020_REG_VALUE_08BIT},//TCLK_ZERO
|
|
{0x0807, 0x07, AR2020_REG_VALUE_08BIT},//TLPX
|
|
{0x082A, 0x0F, AR2020_REG_VALUE_08BIT},//TWAKEUP
|
|
{0x082B, 0x0C, AR2020_REG_VALUE_08BIT},//TINIT
|
|
{0x082C, 0x0D, AR2020_REG_VALUE_08BIT},//THS_EXIT
|
|
{0x3F06, 0x00C0, AR2020_REG_VALUE_16BIT},//MIPI_TIMING_2
|
|
{0x3F0A, 0xA000, AR2020_REG_VALUE_16BIT},//MIPI_TIMING_4
|
|
{0x3F0C, 0x000A, AR2020_REG_VALUE_16BIT},//MIPI_TIMING_5
|
|
{0x3F20, 0x8080, AR2020_REG_VALUE_16BIT},//MIPI_PHY_TRIM_MSB
|
|
{0x3F1E, 0x0004, AR2020_REG_VALUE_16BIT},//MIPI_PHY_TRIM_LSB
|
|
{0x3F22, 0x3806, AR2020_REG_VALUE_16BIT},// MIPI_8LANE_CONTROL
|
|
{0x4000, 0x0114, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_00
|
|
{0x4002, 0x1A25, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_02
|
|
{0x4004, 0x3DFF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_04
|
|
{0x4006, 0xFFFF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_06
|
|
{0x4008, 0x0A35, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_08
|
|
{0x400A, 0x10EF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_0A
|
|
{0x400C, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_0C
|
|
{0x400E, 0x30D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_0E
|
|
{0x4010, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10
|
|
{0x4012, 0xB5F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12
|
|
{0x4014, 0x0085, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14
|
|
{0x4016, 0xF004, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16
|
|
{0x4018, 0x9A89, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18
|
|
{0x401A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A
|
|
{0x401C, 0x9997, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C
|
|
{0x401E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E
|
|
{0x4020, 0x30C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20
|
|
{0x4022, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22
|
|
{0x4024, 0x82F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24
|
|
{0x4026, 0x0030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26
|
|
{0x4028, 0x18F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28
|
|
{0x402A, 0x0320, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A
|
|
{0x402C, 0x58F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C
|
|
{0x402E, 0x089C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E
|
|
{0x4030, 0xF010, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30
|
|
{0x4032, 0x99B6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32
|
|
{0x4034, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34
|
|
{0x4036, 0xB498, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36
|
|
{0x4038, 0xA096, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38
|
|
{0x403A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A
|
|
{0x403C, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C
|
|
{0x403E, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E
|
|
{0x4040, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40
|
|
{0x4042, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42
|
|
{0x4044, 0x209D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44
|
|
{0x4046, 0x8C08, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46
|
|
{0x4048, 0x08F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48
|
|
{0x404A, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A
|
|
{0x404C, 0x008F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4C
|
|
{0x404E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4E
|
|
{0x4050, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_50
|
|
{0x4052, 0x0488, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_52
|
|
{0x4054, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_54
|
|
{0x4056, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_56
|
|
{0x4058, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_58
|
|
{0x405A, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_5A
|
|
{0x405C, 0x0290, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_5C
|
|
{0x405E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_5E
|
|
{0x4060, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_60
|
|
{0x4062, 0x2EA3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_62
|
|
{0x4064, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_64
|
|
{0x4066, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_66
|
|
{0x4068, 0x089D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_68
|
|
{0x406A, 0xF075, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_6A
|
|
{0x406C, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_6C
|
|
{0x406E, 0x4070, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_6E
|
|
{0x4070, 0x216D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_70
|
|
{0x4072, 0x1CF6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_72
|
|
{0x4074, 0x8B00, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_74
|
|
{0x4076, 0x5186, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_76
|
|
{0x4078, 0x1300, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_78
|
|
{0x407A, 0x0205, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_7A
|
|
{0x407C, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_7C
|
|
{0x407E, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_7E
|
|
{0x4080, 0x8387, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_80
|
|
{0x4082, 0xF006, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_82
|
|
{0x4084, 0x8702, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_84
|
|
{0x4086, 0x0D02, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_86
|
|
{0x4088, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_88
|
|
{0x408A, 0x0383, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_8A
|
|
{0x408C, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_8C
|
|
{0x408E, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_8E
|
|
{0x4090, 0x0213, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_90
|
|
{0x4092, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_92
|
|
{0x4094, 0xD887, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_94
|
|
{0x4096, 0x020D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_96
|
|
{0x4098, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_98
|
|
{0x409A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_9A
|
|
{0x409C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_9C
|
|
{0x409E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_9E
|
|
{0x40A0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A0
|
|
{0x40A2, 0x0401, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A2
|
|
{0x40A4, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A4
|
|
{0x40A6, 0x82F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A6
|
|
{0x40A8, 0x0883, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A8
|
|
{0x40AA, 0xF009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_AA
|
|
{0x40AC, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_AC
|
|
{0x40AE, 0x2985, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_AE
|
|
{0x40B0, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B0
|
|
{0x40B2, 0x2A87, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B2
|
|
{0x40B4, 0xF63E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B4
|
|
{0x40B6, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B6
|
|
{0x40B8, 0x0801, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B8
|
|
{0x40BA, 0x40F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_BA
|
|
{0x40BC, 0x0800, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_BC
|
|
{0x40BE, 0x48F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_BE
|
|
{0x40C0, 0x0882, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C0
|
|
{0x40C2, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C2
|
|
{0x40C4, 0x0401, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C4
|
|
{0x40C6, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C6
|
|
{0x40C8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C8
|
|
{0x40CA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_CA
|
|
{0x40CC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_CC
|
|
{0x40CE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_CE
|
|
{0x40D0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D0
|
|
{0x40D2, 0x0401, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D2
|
|
{0x40D4, 0xF015, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D4
|
|
{0x40D6, 0x002C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D6
|
|
{0x40D8, 0xF00E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D8
|
|
{0x40DA, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_DA
|
|
{0x40DC, 0x0687, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_DC
|
|
{0x40DE, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_DE
|
|
{0x40E0, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E0
|
|
{0x40E2, 0x61E8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E2
|
|
{0x40E4, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E4
|
|
{0x40E6, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E6
|
|
{0x40E8, 0x3480, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E8
|
|
{0x40EA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_EA
|
|
{0x40EC, 0x3240, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_EC
|
|
{0x40EE, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_EE
|
|
{0x40F0, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F0
|
|
{0x40F2, 0xF00E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F2
|
|
{0x40F4, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F4
|
|
{0x40F6, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F6
|
|
{0x40F8, 0x3240, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F8
|
|
{0x40FA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_FA
|
|
{0x40FC, 0x3480, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_FC
|
|
{0x40FE, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_FE
|
|
{0x4100, 0xC0E6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_100
|
|
{0x4102, 0xF004, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_102
|
|
{0x4104, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_104
|
|
{0x4106, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_106
|
|
{0x4108, 0xB0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_108
|
|
{0x410A, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10A
|
|
{0x410C, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10C
|
|
{0x410E, 0x86F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10E
|
|
{0x4110, 0x0086, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_110
|
|
{0x4112, 0xF089, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_112
|
|
{0x4114, 0xB0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_114
|
|
{0x4116, 0x00E9, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_116
|
|
{0x4118, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_118
|
|
{0x411A, 0x8AF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_11A
|
|
{0x411C, 0x0000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_11C
|
|
{0x411E, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_11E
|
|
{0x4120, 0x00E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_120
|
|
{0x4122, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_122
|
|
{0x4124, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_124
|
|
{0x4126, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_126
|
|
{0x4128, 0x0A35, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_128
|
|
{0x412A, 0x10EF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12A
|
|
{0x412C, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12C
|
|
{0x412E, 0x30D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12E
|
|
{0x4130, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_130
|
|
{0x4132, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_132
|
|
{0x4134, 0x049A, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_134
|
|
{0x4136, 0x89F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_136
|
|
{0x4138, 0x0099, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_138
|
|
{0x413A, 0x97F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_13A
|
|
{0x413C, 0x0030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_13C
|
|
{0x413E, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_13E
|
|
{0x4140, 0x0082, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_140
|
|
{0x4142, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_142
|
|
{0x4144, 0x3018, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_144
|
|
{0x4146, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_146
|
|
{0x4148, 0xB520, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_148
|
|
{0x414A, 0x58F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14A
|
|
{0x414C, 0x089C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14C
|
|
{0x414E, 0xF010, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14E
|
|
{0x4150, 0x99B6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_150
|
|
{0x4152, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_152
|
|
{0x4154, 0xB498, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_154
|
|
{0x4156, 0xA096, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_156
|
|
{0x4158, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_158
|
|
{0x415A, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_15A
|
|
{0x415C, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_15C
|
|
{0x415E, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_15E
|
|
{0x4160, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_160
|
|
{0x4162, 0x209D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_162
|
|
{0x4164, 0x8C08, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_164
|
|
{0x4166, 0x08F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_166
|
|
{0x4168, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_168
|
|
{0x416A, 0x008F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16A
|
|
{0x416C, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16C
|
|
{0x416E, 0x0188, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16E
|
|
{0x4170, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_170
|
|
{0x4172, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_172
|
|
{0x4174, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_174
|
|
{0x4176, 0x0290, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_176
|
|
{0x4178, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_178
|
|
{0x417A, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_17A
|
|
{0x417C, 0x2DA3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_17C
|
|
{0x417E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_17E
|
|
{0x4180, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_180
|
|
{0x4182, 0x089D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_182
|
|
{0x4184, 0xF06D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_184
|
|
{0x4186, 0x4070, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_186
|
|
{0x4188, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_188
|
|
{0x418A, 0x214D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18A
|
|
{0x418C, 0x1FF6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18C
|
|
{0x418E, 0x0851, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18E
|
|
{0x4190, 0x0245, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_190
|
|
{0x4192, 0x9D36, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_192
|
|
{0x4194, 0xD8F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_194
|
|
{0x4196, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_196
|
|
{0x4198, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_198
|
|
{0x419A, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_19A
|
|
{0x419C, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_19C
|
|
{0x419E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_19E
|
|
{0x41A0, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A0
|
|
{0x41A2, 0x020D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A2
|
|
{0x41A4, 0x0205, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A4
|
|
{0x41A6, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A6
|
|
{0x41A8, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A8
|
|
{0x41AA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1AA
|
|
{0x41AC, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1AC
|
|
{0x41AE, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1AE
|
|
{0x41B0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B0
|
|
{0x41B2, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B2
|
|
{0x41B4, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B4
|
|
{0x41B6, 0xD802, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B6
|
|
{0x41B8, 0x0D02, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B8
|
|
{0x41BA, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1BA
|
|
{0x41BC, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1BC
|
|
{0x41BE, 0xD8F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1BE
|
|
{0x41C0, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C0
|
|
{0x41C2, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C2
|
|
{0x41C4, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C4
|
|
{0x41C6, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C6
|
|
{0x41C8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C8
|
|
{0x41CA, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1CA
|
|
{0x41CC, 0x020D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1CC
|
|
{0x41CE, 0x0205, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1CE
|
|
{0x41D0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D0
|
|
{0x41D2, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D2
|
|
{0x41D4, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D4
|
|
{0x41D6, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D6
|
|
{0x41D8, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D8
|
|
{0x41DA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1DA
|
|
{0x41DC, 0x8713, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1DC
|
|
{0x41DE, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1DE
|
|
{0x41E0, 0xD802, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E0
|
|
{0x41E2, 0x0DE0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E2
|
|
{0x41E4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E4
|
|
{0x41E6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E6
|
|
{0x41E8, 0x9F13, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E8
|
|
{0x41EA, 0x0041, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1EA
|
|
{0x41EC, 0x80F3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1EC
|
|
{0x41EE, 0xF213, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1EE
|
|
{0x41F0, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F0
|
|
{0x41F2, 0x13B8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F2
|
|
{0x41F4, 0xF04C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F4
|
|
{0x41F6, 0x9FF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F6
|
|
{0x41F8, 0x00B7, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F8
|
|
{0x41FA, 0xF006, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1FA
|
|
{0x41FC, 0x0035, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1FC
|
|
{0x41FE, 0x10AF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1FE
|
|
{0x4200, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_200
|
|
{0x4202, 0x30C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_202
|
|
{0x4204, 0xB2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_204
|
|
{0x4206, 0x01B5, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_206
|
|
{0x4208, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_208
|
|
{0x420A, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20A
|
|
{0x420C, 0x0292, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20C
|
|
{0x420E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20E
|
|
{0x4210, 0x9A8B, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_210
|
|
{0x4212, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_212
|
|
{0x4214, 0x9997, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_214
|
|
{0x4216, 0xF007, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_216
|
|
{0x4218, 0xB6F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_218
|
|
{0x421A, 0x0020, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_21A
|
|
{0x421C, 0x5830, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_21C
|
|
{0x421E, 0xC040, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_21E
|
|
{0x4220, 0x1282, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_220
|
|
{0x4222, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_222
|
|
{0x4224, 0x9CF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_224
|
|
{0x4226, 0x01B2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_226
|
|
{0x4228, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_228
|
|
{0x422A, 0xB8F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22A
|
|
{0x422C, 0x0799, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22C
|
|
{0x422E, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22E
|
|
{0x4230, 0x98F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_230
|
|
{0x4232, 0x0296, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_232
|
|
{0x4234, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_234
|
|
{0x4236, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_236
|
|
{0x4238, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_238
|
|
{0x423A, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_23A
|
|
{0x423C, 0x02A1, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_23C
|
|
{0x423E, 0xF01F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_23E
|
|
{0x4240, 0x1009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_240
|
|
{0x4242, 0x2220, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_242
|
|
{0x4244, 0x0808, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_244
|
|
{0x4246, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_246
|
|
{0x4248, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_248
|
|
{0x424A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24A
|
|
{0x424C, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24C
|
|
{0x424E, 0x0788, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24E
|
|
{0x4250, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_250
|
|
{0x4252, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_252
|
|
{0x4254, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_254
|
|
{0x4256, 0x0290, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_256
|
|
{0x4258, 0xF016, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_258
|
|
{0x425A, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_25A
|
|
{0x425C, 0x11A3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_25C
|
|
{0x425E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_25E
|
|
{0x4260, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_260
|
|
{0x4262, 0x089D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_262
|
|
{0x4264, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_264
|
|
{0x4266, 0xA1F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_266
|
|
{0x4268, 0x20A1, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_268
|
|
{0x426A, 0xF006, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26A
|
|
{0x426C, 0x4300, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26C
|
|
{0x426E, 0xF049, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26E
|
|
{0x4270, 0x4014, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_270
|
|
{0x4272, 0x8B8E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_272
|
|
{0x4274, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_274
|
|
{0x4276, 0x0802, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_276
|
|
{0x4278, 0x02F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_278
|
|
{0x427A, 0x00A6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_27A
|
|
{0x427C, 0xF013, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_27C
|
|
{0x427E, 0xB283, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_27E
|
|
{0x4280, 0x9C36, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_280
|
|
{0x4282, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_282
|
|
{0x4284, 0x0636, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_284
|
|
{0x4286, 0x009C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_286
|
|
{0x4288, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_288
|
|
{0x428A, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28A
|
|
{0x428C, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28C
|
|
{0x428E, 0xA0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28E
|
|
{0x4290, 0x0630, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_290
|
|
{0x4292, 0x18F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_292
|
|
{0x4294, 0x02A3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_294
|
|
{0x4296, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_296
|
|
{0x4298, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_298
|
|
{0x429A, 0x0243, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_29A
|
|
{0x429C, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_29C
|
|
{0x429E, 0x049D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_29E
|
|
{0x42A0, 0xF078, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A0
|
|
{0x42A2, 0x3018, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A2
|
|
{0x42A4, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A4
|
|
{0x42A6, 0x9D82, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A6
|
|
{0x42A8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A8
|
|
{0x42AA, 0x9030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2AA
|
|
{0x42AC, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2AC
|
|
{0x42AE, 0x1130, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2AE
|
|
{0x42B0, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B0
|
|
{0x42B2, 0x0082, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B2
|
|
{0x42B4, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B4
|
|
{0x42B6, 0x1009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B6
|
|
{0x42B8, 0xF02A, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B8
|
|
{0x42BA, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2BA
|
|
{0x42BC, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2BC
|
|
{0x42BE, 0x3018, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2BE
|
|
{0x42C0, 0xF007, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C0
|
|
{0x42C2, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C2
|
|
{0x42C4, 0x1C8C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C4
|
|
{0x42C6, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C6
|
|
{0x42C8, 0x301F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C8
|
|
{0x42CA, 0x216D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2CA
|
|
{0x42CC, 0x0A51, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2CC
|
|
{0x42CE, 0x1FEA, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2CE
|
|
{0x42D0, 0x8640, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D0
|
|
{0x42D2, 0xE29F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D2
|
|
{0x42D4, 0xF009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D4
|
|
{0x42D6, 0x0005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D6
|
|
{0x42D8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D8
|
|
{0x42DA, 0x30C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2DA
|
|
{0x42DC, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2DC
|
|
{0x42DE, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2DE
|
|
{0x42E0, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E0
|
|
{0x42E2, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E2
|
|
{0x42E4, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E4
|
|
{0x42E6, 0xF007, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E6
|
|
{0x42E8, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E8
|
|
{0x42EA, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2EA
|
|
{0x42EC, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2EC
|
|
{0x42EE, 0x0000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2EE
|
|
{0x42F0, 0x0DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F0
|
|
{0x42F2, 0x0000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F2
|
|
{0x42F4, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F4
|
|
{0x42F6, 0x0030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F6
|
|
{0x42F8, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F8
|
|
{0x42FA, 0x0183, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2FA
|
|
{0x42FC, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2FC
|
|
{0x42FE, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2FE
|
|
{0x4300, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_300
|
|
{0x4302, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_302
|
|
{0x4304, 0x0787, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_304
|
|
{0x4306, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_306
|
|
{0x4308, 0x36C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_308
|
|
{0x430A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30A
|
|
{0x430C, 0x000F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30C
|
|
{0x430E, 0xF42A, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30E
|
|
{0x4310, 0x4180, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_310
|
|
{0x4312, 0x1300, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_312
|
|
{0x4314, 0x9FF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_314
|
|
{0x4316, 0x00E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_316
|
|
{0x4318, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_318
|
|
{0x431A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_31A
|
|
{0x431C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_31C
|
|
{0x431E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_31E
|
|
{0x4320, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_320
|
|
{0x4322, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_322
|
|
{0x4324, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_324
|
|
{0x4326, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_326
|
|
{0x4328, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_328
|
|
{0x432A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32A
|
|
{0x432C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32C
|
|
{0x432E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32E
|
|
{0x4330, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_330
|
|
{0x4332, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_332
|
|
{0x4334, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_334
|
|
{0x4336, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_336
|
|
{0x4338, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_338
|
|
{0x433A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_33A
|
|
{0x433C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_33C
|
|
{0x433E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_33E
|
|
{0x4340, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_340
|
|
{0x4342, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_342
|
|
{0x4344, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_344
|
|
{0x4346, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_346
|
|
{0x4348, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_348
|
|
{0x434A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34A
|
|
{0x434C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34C
|
|
{0x434E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34E
|
|
{0x4350, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_350
|
|
{0x4352, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_352
|
|
{0x4354, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_354
|
|
{0x4356, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_356
|
|
{0x4358, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_358
|
|
{0x435A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_35A
|
|
{0x435C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_35C
|
|
{0x435E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_35E
|
|
{0x4360, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_360
|
|
{0x4362, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_362
|
|
{0x4364, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_364
|
|
{0x4366, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_366
|
|
{0x4368, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_368
|
|
{0x436A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36A
|
|
{0x436C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36C
|
|
{0x436E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36E
|
|
{0x4370, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_370
|
|
{0x4372, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_372
|
|
{0x4374, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_374
|
|
{0x4376, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_376
|
|
{0x4378, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_378
|
|
{0x437A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_37A
|
|
{0x437C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_37C
|
|
{0x437E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_37E
|
|
{0x4380, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_380
|
|
{0x4382, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_382
|
|
{0x4384, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_384
|
|
{0x4386, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_386
|
|
{0x4388, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_388
|
|
{0x438A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38A
|
|
{0x438C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38C
|
|
{0x438E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38E
|
|
{0x4390, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_390
|
|
{0x4392, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_392
|
|
{0x4394, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_394
|
|
{0x4396, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_396
|
|
{0x4398, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_398
|
|
{0x439A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_39A
|
|
{0x439C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_39C
|
|
{0x439E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_39E
|
|
{0x43A0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A0
|
|
{0x43A2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A2
|
|
{0x43A4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A4
|
|
{0x43A6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A6
|
|
{0x43A8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A8
|
|
{0x43AA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3AA
|
|
{0x43AC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3AC
|
|
{0x43AE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3AE
|
|
{0x43B0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B0
|
|
{0x43B2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B2
|
|
{0x43B4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B4
|
|
{0x43B6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B6
|
|
{0x43B8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B8
|
|
{0x43BA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3BA
|
|
{0x43BC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3BC
|
|
{0x43BE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3BE
|
|
{0x43C0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C0
|
|
{0x43C2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C2
|
|
{0x43C4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C4
|
|
{0x43C6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C6
|
|
{0x43C8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C8
|
|
{0x43CA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3CA
|
|
{0x43CC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3CC
|
|
{0x43CE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3CE
|
|
{0x43D0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D0
|
|
{0x43D2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D2
|
|
{0x43D4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D4
|
|
{0x43D6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D6
|
|
{0x43D8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D8
|
|
{0x43DA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3DA
|
|
{0x43DC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3DC
|
|
{0x43DE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3DE
|
|
{0x43E0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E0
|
|
{0x43E2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E2
|
|
{0x43E4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E4
|
|
{0x43E6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E6
|
|
{0x43E8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E8
|
|
{0x43EA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3EA
|
|
{0x43EC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3EC
|
|
{0x43EE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3EE
|
|
{0x43F0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F0
|
|
{0x43F2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F2
|
|
{0x43F4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F4
|
|
{0x43F6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F6
|
|
{0x43F8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F8
|
|
{0x43FA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3FA
|
|
{0x43FC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3FC
|
|
{0x43FE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3FE
|
|
{0x4400, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_400
|
|
{0x4402, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_402
|
|
{0x4404, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_404
|
|
{0x4406, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_406
|
|
{0x4408, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_408
|
|
{0x440A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40A
|
|
{0x440C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40C
|
|
{0x440E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40E
|
|
{0x4410, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_410
|
|
{0x4412, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_412
|
|
{0x4414, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_414
|
|
{0x4416, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_416
|
|
{0x4418, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_418
|
|
{0x441A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_41A
|
|
{0x441C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_41C
|
|
{0x441E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_41E
|
|
{0x4420, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_420
|
|
{0x4422, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_422
|
|
{0x4424, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_424
|
|
{0x4426, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_426
|
|
{0x4428, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_428
|
|
{0x442A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42A
|
|
{0x442C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42C
|
|
{0x442E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42E
|
|
{0x4430, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_430
|
|
{0x4432, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_432
|
|
{0x4434, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_434
|
|
{0x4436, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_436
|
|
{0x4438, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_438
|
|
{0x443A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_43A
|
|
{0x443C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_43C
|
|
{0x443E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_43E
|
|
{0x4440, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_440
|
|
{0x4442, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_442
|
|
{0x4444, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_444
|
|
{0x4446, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_446
|
|
{0x4448, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_448
|
|
{0x444A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44A
|
|
{0x444C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44C
|
|
{0x444E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44E
|
|
{0x4450, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_450
|
|
{0x4452, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_452
|
|
{0x4454, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_454
|
|
{0x4456, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_456
|
|
{0x4458, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_458
|
|
{0x445A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_45A
|
|
{0x445C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_45C
|
|
{0x445E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_45E
|
|
{0x4460, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_460
|
|
{0x4462, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_462
|
|
{0x4464, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_464
|
|
{0x4466, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_466
|
|
{0x4468, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_468
|
|
{0x446A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46A
|
|
{0x446C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46C
|
|
{0x446E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46E
|
|
{0x4470, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_470
|
|
{0x4472, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_472
|
|
{0x4474, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_474
|
|
{0x4476, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_476
|
|
{0x4478, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_478
|
|
{0x447A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_47A
|
|
{0x447C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_47C
|
|
{0x447E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_47E
|
|
{0x4480, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_480
|
|
{0x4482, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_482
|
|
{0x4484, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_484
|
|
{0x4486, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_486
|
|
{0x4488, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_488
|
|
{0x448A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48A
|
|
{0x448C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48C
|
|
{0x448E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48E
|
|
{0x4490, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_490
|
|
{0x4492, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_492
|
|
{0x4494, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_494
|
|
{0x4496, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_496
|
|
{0x4498, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_498
|
|
{0x449A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_49A
|
|
{0x449C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_49C
|
|
{0x449E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_49E
|
|
{0x44A0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A0
|
|
{0x44A2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A2
|
|
{0x44A4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A4
|
|
{0x44A6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A6
|
|
{0x44A8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A8
|
|
{0x44AA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4AA
|
|
{0x44AC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4AC
|
|
{0x44AE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4AE
|
|
{0x44B0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4B0
|
|
{0x44B2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4B2
|
|
{0x44B4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4B4
|
|
{0x5500, 0x0000, AR2020_REG_VALUE_16BIT},//AGAIN_LUT0
|
|
{0x5502, 0x0002, AR2020_REG_VALUE_16BIT},//AGAIN_LUT1
|
|
{0x5504, 0x0006, AR2020_REG_VALUE_16BIT},//AGAIN_LUT2
|
|
{0x5506, 0x0009, AR2020_REG_VALUE_16BIT},//AGAIN_LUT3
|
|
{0x5508, 0x000F, AR2020_REG_VALUE_16BIT},//AGAIN_LUT4
|
|
{0x550A, 0x0010, AR2020_REG_VALUE_16BIT},//AGAIN_LUT5
|
|
{0x550C, 0x0011, AR2020_REG_VALUE_16BIT},//AGAIN_LUT6
|
|
{0x550E, 0x0012, AR2020_REG_VALUE_16BIT},//AGAIN_LUT7
|
|
{0x5510, 0x0019, AR2020_REG_VALUE_16BIT},//AGAIN_LUT8
|
|
{0x5512, 0x0020, AR2020_REG_VALUE_16BIT},//AGAIN_LUT9
|
|
{0x5514, 0x0021, AR2020_REG_VALUE_16BIT},//AGAIN_LUT10
|
|
{0x5516, 0x0023, AR2020_REG_VALUE_16BIT},//AGAIN_LUT11
|
|
{0x5518, 0x0026, AR2020_REG_VALUE_16BIT},//AGAIN_LUT12
|
|
{0x551A, 0x002B, AR2020_REG_VALUE_16BIT},//AGAIN_LUT13
|
|
{0x551C, 0x002F, AR2020_REG_VALUE_16BIT},//AGAIN_LUT14
|
|
{0x551E, 0x0030, AR2020_REG_VALUE_16BIT},//AGAIN_LUT15
|
|
{0x5400, 0x0100, AR2020_REG_VALUE_16BIT},//GT1_COARSE0
|
|
{0x5402, 0x2106, AR2020_REG_VALUE_16BIT},//GT1_COARSE1
|
|
{0x5404, 0x1101, AR2020_REG_VALUE_16BIT},//GT1_COARSE2
|
|
{0x5406, 0x3106, AR2020_REG_VALUE_16BIT},//GT1_COARSE3
|
|
{0x5408, 0x7100, AR2020_REG_VALUE_16BIT},//GT1_COARSE4
|
|
{0x540A, 0x8107, AR2020_REG_VALUE_16BIT},//GT1_COARSE5
|
|
{0x540C, 0xB101, AR2020_REG_VALUE_16BIT},//GT1_COARSE6
|
|
{0x540E, 0xD101, AR2020_REG_VALUE_16BIT},//GT1_COARSE7
|
|
{0x5410, 0xF12E, AR2020_REG_VALUE_16BIT},//GT1_COARSE8
|
|
{0x5412, 0xF112, AR2020_REG_VALUE_16BIT},//GT1_COARSE9
|
|
{0x5414, 0xF184, AR2020_REG_VALUE_16BIT},//GT1_COARSE10
|
|
{0x5416, 0xF224, AR2020_REG_VALUE_16BIT},//GT1_COARSE11
|
|
{0x5418, 0xF306, AR2020_REG_VALUE_16BIT},//GT1_COARSE12
|
|
{0x541A, 0xF446, AR2020_REG_VALUE_16BIT},//GT1_COARSE13
|
|
{0x541C, 0xF609, AR2020_REG_VALUE_16BIT},//GT1_COARSE14
|
|
{0x541E, 0xF887, AR2020_REG_VALUE_16BIT},//GT1_COARSE15
|
|
{0x5420, 0xFC0B, AR2020_REG_VALUE_16BIT},//GT1_COARSE16
|
|
{0x5422, 0xFC0B, AR2020_REG_VALUE_16BIT},//GT1_COARSE17
|
|
{0x5424, 0xFFFA, AR2020_REG_VALUE_16BIT},//GT1_DCG_ATTN_SET0
|
|
{0x5426, 0x5557, AR2020_REG_VALUE_16BIT},//GT1_DCG_ATTN_SET1
|
|
{0x5428, 0x0005, AR2020_REG_VALUE_16BIT},//GT1_DCG_ATTN_SET2
|
|
{0x542A, 0xA550, AR2020_REG_VALUE_16BIT},//GT1_ZONE_SET0
|
|
{0x542C, 0xAAAA, AR2020_REG_VALUE_16BIT},//GT1_ZONE_SET1
|
|
{0x542E, 0x000A, AR2020_REG_VALUE_16BIT},//GT1_ZONE_SET2
|
|
{0x5460, 0x2269, AR2020_REG_VALUE_16BIT},//ZT1_REG0_ADDR
|
|
{0x5462, 0x0B87, AR2020_REG_VALUE_16BIT},//ZT1_REG0_VALUE0
|
|
{0x5464, 0x0B87, AR2020_REG_VALUE_16BIT},//ZT1_REG0_VALUE1
|
|
{0x5466, 0x0983, AR2020_REG_VALUE_16BIT},//ZT1_REG0_VALUE2
|
|
{0x5498, 0x225E, AR2020_REG_VALUE_16BIT},//ZT1_REG7_ADDR
|
|
{0x549A, 0xBCAA, AR2020_REG_VALUE_16BIT},//ZT1_REG7_VALUE0
|
|
{0x549C, 0xBCAA, AR2020_REG_VALUE_16BIT},//ZT1_REG7_VALUE1
|
|
{0x549E, 0xBDAA, AR2020_REG_VALUE_16BIT},//ZT1_REG7_VALUE2
|
|
{0x3060, 0xFF01, AR2020_REG_VALUE_16BIT},//GAIN_TABLE_CTRL
|
|
{0x44BA, 0x0050, AR2020_REG_VALUE_16BIT},//DAC_LD_4_5
|
|
{0x44BC, 0xBCAA, AR2020_REG_VALUE_16BIT},//DAC_LD_6_7
|
|
{0x44C0, 0x4070, AR2020_REG_VALUE_16BIT},//DAC_LD_10_11
|
|
{0x44C4, 0x04D0, AR2020_REG_VALUE_16BIT},//DAC_LD_14_15
|
|
{0x44C6, 0x17E2, AR2020_REG_VALUE_16BIT},//DAC_LD_16_17
|
|
{0x44C8, 0xEA43, AR2020_REG_VALUE_16BIT},//DAC_LD_18_19
|
|
{0x44CA, 0x000E, AR2020_REG_VALUE_16BIT},//DAC_LD_20_21
|
|
{0x44CC, 0x7777, AR2020_REG_VALUE_16BIT},//DAC_LD_22_23
|
|
{0x44CE, 0x8BA4, AR2020_REG_VALUE_16BIT},//DAC_LD_24_25
|
|
{0x44D0, 0x1735, AR2020_REG_VALUE_16BIT},//DAC_LD_26_27
|
|
{0x44D2, 0x0B87, AR2020_REG_VALUE_16BIT},//DAC_LD_28_29
|
|
{0x44D4, 0x0000, AR2020_REG_VALUE_16BIT},//DAC_LD_30_31
|
|
{0x44D6, 0xF206, AR2020_REG_VALUE_16BIT},//DAC_LD_32_33
|
|
{0x44D8, 0xAAFA, AR2020_REG_VALUE_16BIT},//DAC_LD_34_35
|
|
{0x44DA, 0xE001, AR2020_REG_VALUE_16BIT},//DAC_LD_36_37
|
|
{0x44DE, 0x9BBC, AR2020_REG_VALUE_16BIT},//DAC_LD_40_41
|
|
{0x44E0, 0x283C, AR2020_REG_VALUE_16BIT},//DAC_LD_42_43
|
|
{0x44E2, 0x2821, AR2020_REG_VALUE_16BIT},//DAC_LD_44_45
|
|
{0x44E4, 0x8000, AR2020_REG_VALUE_16BIT},//DAC_LD_46_47
|
|
{0x44E6, 0x503F, AR2020_REG_VALUE_16BIT},//DAC_LD_48_49
|
|
{0x32A4, 0x0000, AR2020_REG_VALUE_16BIT},//CRM_CTRL
|
|
{0x328E, 0x0004, AR2020_REG_VALUE_16BIT},//ADDR_CTRL
|
|
{0x333C, 0x0001, AR2020_REG_VALUE_16BIT},//DYNAMIC_CTRL
|
|
{0x301A, 0x0000, AR2020_REG_VALUE_16BIT},//RESET_REGISTER
|
|
{0x3600, 0x94DF, AR2020_REG_VALUE_16BIT},//FDOC_CTRL
|
|
{0x3616, 0x0000, AR2020_REG_VALUE_16BIT},//FDOC_CTRL2
|
|
{0x3700, 0x0001, AR2020_REG_VALUE_16BIT},//PIX_DEF_ID
|
|
{0x3980, 0x0003, AR2020_REG_VALUE_16BIT},//PIX_DEF_CORR
|
|
{0x36C0, 0x0001, AR2020_REG_VALUE_16BIT},//DIGITAL_GAIN_CTRL
|
|
{0x36DE, 0x002A, AR2020_REG_VALUE_16BIT},//DATA_PEDESTAL1
|
|
{0x301A, 0x0008, AR2020_REG_VALUE_16BIT},//RESET_REGISTER
|
|
{0x3060, 0x0000, AR2020_REG_VALUE_16BIT},//GAIN_TABLE_CTRL
|
|
{0x3982, 0xAC70, AR2020_REG_VALUE_16BIT},//PDC_DYN_EDGE_THRES
|
|
{0x3984, 0xFA98, AR2020_REG_VALUE_16BIT},//PDC_DYN_LO_DEFECT_THRES
|
|
{0x3986, 0xFC3F, AR2020_REG_VALUE_16BIT},//PDC_DYN_HI_DEFECT_THRES
|
|
{0x3988, 0xAC70, AR2020_REG_VALUE_16BIT},//PDC_DYN_EDGE_THRES_T2
|
|
{0x398A, 0xFA98, AR2020_REG_VALUE_16BIT},//PDC_DYN_LO_DEFECT_THRES_T2
|
|
{0x398C, 0xFC3F, AR2020_REG_VALUE_16BIT},//PDC_DYN_HI_DEFECT_THRES_T2
|
|
{0x3980, 0x0003, AR2020_REG_VALUE_16BIT},//PIX_DEF_CORR
|
|
{0x3060, 0xFF01, AR2020_REG_VALUE_16BIT},//GAIN_TABLE_CTRL
|
|
{0x3340, 0x0C60, AR2020_REG_VALUE_16BIT},//OTPM_CTRL
|
|
{0x3340, 0x1C60, AR2020_REG_VALUE_16BIT},//OTPM_CTRL
|
|
{0x0101, 0x01, AR2020_REG_VALUE_08BIT},//Bing added, this is for H mirror FLIP.
|
|
{0x0100, 0x01, AR2020_REG_VALUE_08BIT},//MODE_SELECT
|
|
{0x44D6, 0xB206, AR2020_REG_VALUE_16BIT},//DAC_LD_32_33
|
|
|
|
{REG_NULL, 0x00, AR2020_REG_VALUE_16BIT},
|
|
};
|
|
|
|
static const struct regval ar2020_linear_5120x3840_30fps_regs[] = {
|
|
{REG_DELAY, 2000, AR2020_REG_VALUE_16BIT},
|
|
{0x44D6, 0xF206, AR2020_REG_VALUE_16BIT},//DAC_LD_32_33
|
|
{0x0100, 0x00, AR2020_REG_VALUE_08BIT},//MODE_SELECT
|
|
{0x0304, 0x0002, AR2020_REG_VALUE_16BIT},//VT_PRE_PLL_CLK_DIV
|
|
{0x0306, 0x0067, AR2020_REG_VALUE_16BIT},//VT_PLL_MULTIPLIER
|
|
{0x0300, 0x0006, AR2020_REG_VALUE_16BIT},//VT_PIX_CLK_DIV
|
|
{0x0302, 0x0001, AR2020_REG_VALUE_16BIT},//VT_SYS_CLK_DIV
|
|
{0x030C, 0x0007, AR2020_REG_VALUE_16BIT},//OP_PRE_PLL_CLK_DIV
|
|
{0x030E, 0x0258, AR2020_REG_VALUE_16BIT},//OP_PLL_MULTIPLIER
|
|
{0x0308, 0x0005, AR2020_REG_VALUE_16BIT},//OP_PIX_CLK_DIV
|
|
{0x030A, 0x0002, AR2020_REG_VALUE_16BIT},//OP_SYS_CLK_DIV
|
|
{0x0344, 0x0008, AR2020_REG_VALUE_16BIT},//X_ADDR_START
|
|
{0x0348, 0x1407, AR2020_REG_VALUE_16BIT},//X_ADDR_END
|
|
{0x0346, 0x0008, AR2020_REG_VALUE_16BIT},//Y_ADDR_START
|
|
{0x034A, 0x0F07, AR2020_REG_VALUE_16BIT},//Y_ADDR_END
|
|
{0x034C, 0x1400, AR2020_REG_VALUE_16BIT},//X_OUTPUT_SIZE
|
|
{0x034E, 0x0F00, AR2020_REG_VALUE_16BIT},//Y_OUTPUT_SIZE
|
|
{0x0380, 0x0001, AR2020_REG_VALUE_16BIT},//X_EVEN_INC
|
|
{0x0382, 0x0001, AR2020_REG_VALUE_16BIT},//X_ODD_INC
|
|
{0x0384, 0x0001, AR2020_REG_VALUE_16BIT},//Y_EVEN_INC
|
|
{0x0386, 0x0001, AR2020_REG_VALUE_16BIT},//Y_ODD_INC
|
|
{0x0900, 0x00, AR2020_REG_VALUE_08BIT},//BINNING_MODE
|
|
{0x0901, 0x11, AR2020_REG_VALUE_08BIT},//BINNING_TYPE
|
|
{0x0342, 0x2DF0, AR2020_REG_VALUE_16BIT},//LINE_LENGTH_PCK
|
|
{0x0340, 0x0F28, AR2020_REG_VALUE_16BIT},//FRAME_LENGTH_LINES
|
|
{0x0202, 0x0F34, AR2020_REG_VALUE_16BIT},//COARSE_INTEGRATION_TIME
|
|
{0x0112, 0x0A0A, AR2020_REG_VALUE_16BIT},//CSI_DATA_FORMAT
|
|
{0x0114, 0x03, AR2020_REG_VALUE_08BIT},//CSI_LANE_MODE
|
|
{0x0800, 0x10, AR2020_REG_VALUE_08BIT},//TCLK_POST
|
|
{0x0801, 0x09, AR2020_REG_VALUE_08BIT},//THS_PREPARE
|
|
{0x0802, 0x11, AR2020_REG_VALUE_08BIT},//THS_ZERO_MIN
|
|
{0x0803, 0x0C, AR2020_REG_VALUE_08BIT},//THS_TRAIL
|
|
{0x0804, 0x0F, AR2020_REG_VALUE_08BIT},//TCLK_TRAIL_MIN
|
|
{0x0805, 0x08, AR2020_REG_VALUE_08BIT},//TCLK_PREPARE
|
|
{0x0806, 0x34, AR2020_REG_VALUE_08BIT},//TCLK_ZERO
|
|
{0x0807, 0x0A, AR2020_REG_VALUE_08BIT},//TLPX
|
|
{0x082A, 0x15, AR2020_REG_VALUE_08BIT},//TWAKEUP
|
|
{0x082B, 0x11, AR2020_REG_VALUE_08BIT},//TINIT
|
|
{0x082C, 0x13, AR2020_REG_VALUE_08BIT},//THS_EXIT
|
|
{0x3F06, 0x00C0, AR2020_REG_VALUE_16BIT},//MIPI_TIMING_2
|
|
{0x3F0A, 0xA000, AR2020_REG_VALUE_16BIT},//MIPI_TIMING_4
|
|
{0x3F0C, 0x000E, AR2020_REG_VALUE_16BIT},//MIPI_TIMING_5
|
|
{0x3F20, 0x8080, AR2020_REG_VALUE_16BIT},//MIPI_PHY_TRIM_MSB
|
|
{0x3F1E, 0x0004, AR2020_REG_VALUE_16BIT},//MIPI_PHY_TRIM_LSB
|
|
{0x4000, 0x0115, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_00
|
|
{0x4002, 0x1B26, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_02
|
|
{0x4004, 0x3FFF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_04
|
|
{0x4006, 0xFFFF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_06
|
|
{0x4008, 0x0A35, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_08
|
|
{0x400A, 0x10EF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_0A
|
|
{0x400C, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_0C
|
|
{0x400E, 0x30D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_0E
|
|
{0x4010, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10
|
|
{0x4012, 0xB5F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12
|
|
{0x4014, 0x0085, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14
|
|
{0x4016, 0xF004, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16
|
|
{0x4018, 0x9A89, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18
|
|
{0x401A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A
|
|
{0x401C, 0x9997, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C
|
|
{0x401E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E
|
|
{0x4020, 0x30C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20
|
|
{0x4022, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22
|
|
{0x4024, 0x82F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24
|
|
{0x4026, 0x0030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26
|
|
{0x4028, 0x18F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28
|
|
{0x402A, 0x0320, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A
|
|
{0x402C, 0x58F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C
|
|
{0x402E, 0x089C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E
|
|
{0x4030, 0xF010, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30
|
|
{0x4032, 0x99B6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32
|
|
{0x4034, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34
|
|
{0x4036, 0xB498, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36
|
|
{0x4038, 0xA096, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38
|
|
{0x403A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A
|
|
{0x403C, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C
|
|
{0x403E, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E
|
|
{0x4040, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40
|
|
{0x4042, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42
|
|
{0x4044, 0x209D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44
|
|
{0x4046, 0x8C08, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46
|
|
{0x4048, 0x08F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48
|
|
{0x404A, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A
|
|
{0x404C, 0x008F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4C
|
|
{0x404E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4E
|
|
{0x4050, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_50
|
|
{0x4052, 0x0488, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_52
|
|
{0x4054, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_54
|
|
{0x4056, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_56
|
|
{0x4058, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_58
|
|
{0x405A, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_5A
|
|
{0x405C, 0x0290, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_5C
|
|
{0x405E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_5E
|
|
{0x4060, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_60
|
|
{0x4062, 0x2EA3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_62
|
|
{0x4064, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_64
|
|
{0x4066, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_66
|
|
{0x4068, 0x089D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_68
|
|
{0x406A, 0xF075, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_6A
|
|
{0x406C, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_6C
|
|
{0x406E, 0x4070, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_6E
|
|
{0x4070, 0x216D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_70
|
|
{0x4072, 0x1CF6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_72
|
|
{0x4074, 0x8B00, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_74
|
|
{0x4076, 0x5186, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_76
|
|
{0x4078, 0x1300, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_78
|
|
{0x407A, 0x0205, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_7A
|
|
{0x407C, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_7C
|
|
{0x407E, 0x9FB7, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_7E
|
|
{0x4080, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_80
|
|
{0x4082, 0x8387, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_82
|
|
{0x4084, 0xF006, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_84
|
|
{0x4086, 0x8702, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_86
|
|
{0x4088, 0x0D02, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_88
|
|
{0x408A, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_8A
|
|
{0x408C, 0x0383, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_8C
|
|
{0x408E, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_8E
|
|
{0x4090, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_90
|
|
{0x4092, 0x0336, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_92
|
|
{0x4094, 0xD887, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_94
|
|
{0x4096, 0x020D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_96
|
|
{0x4098, 0xF14F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_98
|
|
{0x409A, 0xB79F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_9A
|
|
{0x409C, 0x1300, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_9C
|
|
{0x409E, 0xF012, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_9E
|
|
{0x40A0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A0
|
|
{0x40A2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A2
|
|
{0x40A4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A4
|
|
{0x40A6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A6
|
|
{0x40A8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_A8
|
|
{0x40AA, 0x0401, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_AA
|
|
{0x40AC, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_AC
|
|
{0x40AE, 0x82F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_AE
|
|
{0x40B0, 0x0883, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B0
|
|
{0x40B2, 0xF009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B2
|
|
{0x40B4, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B4
|
|
{0x40B6, 0x2985, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B6
|
|
{0x40B8, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_B8
|
|
{0x40BA, 0x2A87, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_BA
|
|
{0x40BC, 0xF63E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_BC
|
|
{0x40BE, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_BE
|
|
{0x40C0, 0x0801, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C0
|
|
{0x40C2, 0x40F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C2
|
|
{0x40C4, 0x0800, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C4
|
|
{0x40C6, 0x48F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C6
|
|
{0x40C8, 0x0882, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_C8
|
|
{0x40CA, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_CA
|
|
{0x40CC, 0x0401, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_CC
|
|
{0x40CE, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_CE
|
|
{0x40D0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D0
|
|
{0x40D2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D2
|
|
{0x40D4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D4
|
|
{0x40D6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D6
|
|
{0x40D8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_D8
|
|
{0x40DA, 0x0401, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_DA
|
|
{0x40DC, 0xF015, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_DC
|
|
{0x40DE, 0x002C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_DE
|
|
{0x40E0, 0xF00E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E0
|
|
{0x40E2, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E2
|
|
{0x40E4, 0x0687, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E4
|
|
{0x40E6, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E6
|
|
{0x40E8, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_E8
|
|
{0x40EA, 0x61E8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_EA
|
|
{0x40EC, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_EC
|
|
{0x40EE, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_EE
|
|
{0x40F0, 0x3480, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F0
|
|
{0x40F2, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F2
|
|
{0x40F4, 0x3240, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F4
|
|
{0x40F6, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F6
|
|
{0x40F8, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_F8
|
|
{0x40FA, 0xF00E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_FA
|
|
{0x40FC, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_FC
|
|
{0x40FE, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_FE
|
|
{0x4100, 0x3240, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_100
|
|
{0x4102, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_102
|
|
{0x4104, 0x3480, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_104
|
|
{0x4106, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_106
|
|
{0x4108, 0xC0EE, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_108
|
|
{0x410A, 0xF004, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10A
|
|
{0x410C, 0x3900, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10C
|
|
{0x410E, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_10E
|
|
{0x4110, 0xB0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_110
|
|
{0x4112, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_112
|
|
{0x4114, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_114
|
|
{0x4116, 0x86F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_116
|
|
{0x4118, 0x0086, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_118
|
|
{0x411A, 0xF089, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_11A
|
|
{0x411C, 0xB0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_11C
|
|
{0x411E, 0x00E9, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_11E
|
|
{0x4120, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_120
|
|
{0x4122, 0x8AF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_122
|
|
{0x4124, 0x0000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_124
|
|
{0x4126, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_126
|
|
{0x4128, 0x00E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_128
|
|
{0x412A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12A
|
|
{0x412C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12C
|
|
{0x412E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_12E
|
|
{0x4130, 0x0A35, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_130
|
|
{0x4132, 0x10EF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_132
|
|
{0x4134, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_134
|
|
{0x4136, 0x30D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_136
|
|
{0x4138, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_138
|
|
{0x413A, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_13A
|
|
{0x413C, 0x049A, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_13C
|
|
{0x413E, 0x89F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_13E
|
|
{0x4140, 0x0099, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_140
|
|
{0x4142, 0x97F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_142
|
|
{0x4144, 0x0030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_144
|
|
{0x4146, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_146
|
|
{0x4148, 0x0082, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_148
|
|
{0x414A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14A
|
|
{0x414C, 0x3018, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14C
|
|
{0x414E, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_14E
|
|
{0x4150, 0xB520, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_150
|
|
{0x4152, 0x58F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_152
|
|
{0x4154, 0x089C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_154
|
|
{0x4156, 0xF010, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_156
|
|
{0x4158, 0x99B6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_158
|
|
{0x415A, 0xF003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_15A
|
|
{0x415C, 0xB498, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_15C
|
|
{0x415E, 0xA096, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_15E
|
|
{0x4160, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_160
|
|
{0x4162, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_162
|
|
{0x4164, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_164
|
|
{0x4166, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_166
|
|
{0x4168, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_168
|
|
{0x416A, 0x209D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16A
|
|
{0x416C, 0x8C08, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16C
|
|
{0x416E, 0x08F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_16E
|
|
{0x4170, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_170
|
|
{0x4172, 0x008F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_172
|
|
{0x4174, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_174
|
|
{0x4176, 0x0188, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_176
|
|
{0x4178, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_178
|
|
{0x417A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_17A
|
|
{0x417C, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_17C
|
|
{0x417E, 0x0290, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_17E
|
|
{0x4180, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_180
|
|
{0x4182, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_182
|
|
{0x4184, 0x2DA3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_184
|
|
{0x4186, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_186
|
|
{0x4188, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_188
|
|
{0x418A, 0x089D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18A
|
|
{0x418C, 0xF06D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18C
|
|
{0x418E, 0x4070, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_18E
|
|
{0x4190, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_190
|
|
{0x4192, 0x214D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_192
|
|
{0x4194, 0x1FF6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_194
|
|
{0x4196, 0x0851, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_196
|
|
{0x4198, 0x0245, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_198
|
|
{0x419A, 0x20A0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_19A
|
|
{0x419C, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_19C
|
|
{0x419E, 0xB783, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_19E
|
|
{0x41A0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A0
|
|
{0x41A2, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A2
|
|
{0x41A4, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A4
|
|
{0x41A6, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A6
|
|
{0x41A8, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1A8
|
|
{0x41AA, 0x020D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1AA
|
|
{0x41AC, 0x0205, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1AC
|
|
{0x41AE, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1AE
|
|
{0x41B0, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B0
|
|
{0x41B2, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B2
|
|
{0x41B4, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B4
|
|
{0x41B6, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B6
|
|
{0x41B8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1B8
|
|
{0x41BA, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1BA
|
|
{0x41BC, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1BC
|
|
{0x41BE, 0xD802, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1BE
|
|
{0x41C0, 0x0D02, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C0
|
|
{0x41C2, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C2
|
|
{0x41C4, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C4
|
|
{0x41C6, 0xD8F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C6
|
|
{0x41C8, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1C8
|
|
{0x41CA, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1CA
|
|
{0x41CC, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1CC
|
|
{0x41CE, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1CE
|
|
{0x41D0, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D0
|
|
{0x41D2, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D2
|
|
{0x41D4, 0x020D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D4
|
|
{0x41D6, 0x0205, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D6
|
|
{0x41D8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1D8
|
|
{0x41DA, 0x36D8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1DA
|
|
{0x41DC, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1DC
|
|
{0x41DE, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1DE
|
|
{0x41E0, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E0
|
|
{0x41E2, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E2
|
|
{0x41E4, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E4
|
|
{0x41E6, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E6
|
|
{0x41E8, 0xD802, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1E8
|
|
{0x41EA, 0x0DF1, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1EA
|
|
{0x41EC, 0x4FB7, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1EC
|
|
{0x41EE, 0x9F13, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1EE
|
|
{0x41F0, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F0
|
|
{0x41F2, 0x12E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F2
|
|
{0x41F4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F4
|
|
{0x41F6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F6
|
|
{0x41F8, 0x9F13, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1F8
|
|
{0x41FA, 0x0041, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1FA
|
|
{0x41FC, 0x80F1, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1FC
|
|
{0x41FE, 0x30B8, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_1FE
|
|
{0x4200, 0xF00D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_200
|
|
{0x4202, 0x1300, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_202
|
|
{0x4204, 0xF03D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_204
|
|
{0x4206, 0x9FF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_206
|
|
{0x4208, 0x00B7, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_208
|
|
{0x420A, 0xF006, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20A
|
|
{0x420C, 0x0035, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20C
|
|
{0x420E, 0x10AF, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_20E
|
|
{0x4210, 0x3003, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_210
|
|
{0x4212, 0x30C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_212
|
|
{0x4214, 0xB2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_214
|
|
{0x4216, 0x01B5, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_216
|
|
{0x4218, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_218
|
|
{0x421A, 0x85F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_21A
|
|
{0x421C, 0x0292, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_21C
|
|
{0x421E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_21E
|
|
{0x4220, 0x9A8B, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_220
|
|
{0x4222, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_222
|
|
{0x4224, 0x9997, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_224
|
|
{0x4226, 0xF007, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_226
|
|
{0x4228, 0xB6F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_228
|
|
{0x422A, 0x0020, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22A
|
|
{0x422C, 0x5830, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22C
|
|
{0x422E, 0xC040, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_22E
|
|
{0x4230, 0x1282, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_230
|
|
{0x4232, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_232
|
|
{0x4234, 0x9CF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_234
|
|
{0x4236, 0x01B2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_236
|
|
{0x4238, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_238
|
|
{0x423A, 0xB8F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_23A
|
|
{0x423C, 0x0799, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_23C
|
|
{0x423E, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_23E
|
|
{0x4240, 0x98F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_240
|
|
{0x4242, 0x0296, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_242
|
|
{0x4244, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_244
|
|
{0x4246, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_246
|
|
{0x4248, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_248
|
|
{0x424A, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24A
|
|
{0x424C, 0x02A1, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24C
|
|
{0x424E, 0xF01F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_24E
|
|
{0x4250, 0x1009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_250
|
|
{0x4252, 0x2220, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_252
|
|
{0x4254, 0x0808, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_254
|
|
{0x4256, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_256
|
|
{0x4258, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_258
|
|
{0x425A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_25A
|
|
{0x425C, 0x88F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_25C
|
|
{0x425E, 0x0788, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_25E
|
|
{0x4260, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_260
|
|
{0x4262, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_262
|
|
{0x4264, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_264
|
|
{0x4266, 0x0290, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_266
|
|
{0x4268, 0xF016, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_268
|
|
{0x426A, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26A
|
|
{0x426C, 0x11A3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26C
|
|
{0x426E, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_26E
|
|
{0x4270, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_270
|
|
{0x4272, 0x089D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_272
|
|
{0x4274, 0xF002, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_274
|
|
{0x4276, 0xA1F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_276
|
|
{0x4278, 0x20A1, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_278
|
|
{0x427A, 0xF006, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_27A
|
|
{0x427C, 0x4300, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_27C
|
|
{0x427E, 0xF049, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_27E
|
|
{0x4280, 0x4014, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_280
|
|
{0x4282, 0x8B8E, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_282
|
|
{0x4284, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_284
|
|
{0x4286, 0x0802, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_286
|
|
{0x4288, 0x02F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_288
|
|
{0x428A, 0x00A6, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28A
|
|
{0x428C, 0xF013, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28C
|
|
{0x428E, 0xB283, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_28E
|
|
{0x4290, 0x9C36, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_290
|
|
{0x4292, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_292
|
|
{0x4294, 0x0636, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_294
|
|
{0x4296, 0x009C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_296
|
|
{0x4298, 0xF008, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_298
|
|
{0x429A, 0x8BF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_29A
|
|
{0x429C, 0x0083, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_29C
|
|
{0x429E, 0xA0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_29E
|
|
{0x42A0, 0x0630, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A0
|
|
{0x42A2, 0x18F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A2
|
|
{0x42A4, 0x02A3, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A4
|
|
{0x42A6, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A6
|
|
{0x42A8, 0xA3F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2A8
|
|
{0x42AA, 0x0243, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2AA
|
|
{0x42AC, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2AC
|
|
{0x42AE, 0x049D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2AE
|
|
{0x42B0, 0xF078, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B0
|
|
{0x42B2, 0x3018, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B2
|
|
{0x42B4, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B4
|
|
{0x42B6, 0x9D82, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B6
|
|
{0x42B8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2B8
|
|
{0x42BA, 0x9030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2BA
|
|
{0x42BC, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2BC
|
|
{0x42BE, 0x1130, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2BE
|
|
{0x42C0, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C0
|
|
{0x42C2, 0x0082, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C2
|
|
{0x42C4, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C4
|
|
{0x42C6, 0x1009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C6
|
|
{0x42C8, 0xF02A, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2C8
|
|
{0x42CA, 0xA2F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2CA
|
|
{0x42CC, 0x00A2, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2CC
|
|
{0x42CE, 0x3018, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2CE
|
|
{0x42D0, 0xF007, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D0
|
|
{0x42D2, 0x9DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D2
|
|
{0x42D4, 0x1C8C, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D4
|
|
{0x42D6, 0xF005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D6
|
|
{0x42D8, 0x301F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2D8
|
|
{0x42DA, 0x216D, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2DA
|
|
{0x42DC, 0x0A51, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2DC
|
|
{0x42DE, 0x1FEA, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2DE
|
|
{0x42E0, 0x8640, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E0
|
|
{0x42E2, 0xE29F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E2
|
|
{0x42E4, 0xF009, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E4
|
|
{0x42E6, 0x0005, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E6
|
|
{0x42E8, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2E8
|
|
{0x42EA, 0x30C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2EA
|
|
{0x42EC, 0xF001, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2EC
|
|
{0x42EE, 0x83F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2EE
|
|
{0x42F0, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F0
|
|
{0x42F2, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F2
|
|
{0x42F4, 0x0087, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F4
|
|
{0x42F6, 0xF007, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F6
|
|
{0x42F8, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2F8
|
|
{0x42FA, 0x0036, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2FA
|
|
{0x42FC, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2FC
|
|
{0x42FE, 0x0000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_2FE
|
|
{0x4300, 0x0DF0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_300
|
|
{0x4302, 0x0000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_302
|
|
{0x4304, 0x05F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_304
|
|
{0x4306, 0x0030, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_306
|
|
{0x4308, 0xC0F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_308
|
|
{0x430A, 0x0183, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30A
|
|
{0x430C, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30C
|
|
{0x430E, 0x3600, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_30E
|
|
{0x4310, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_310
|
|
{0x4312, 0x87F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_312
|
|
{0x4314, 0x0787, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_314
|
|
{0x4316, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_316
|
|
{0x4318, 0x36C0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_318
|
|
{0x431A, 0xF000, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_31A
|
|
{0x431C, 0x000F, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_31C
|
|
{0x431E, 0xF153, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_31E
|
|
{0x4320, 0x4180, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_320
|
|
{0x4322, 0x9F13, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_322
|
|
{0x4324, 0x00F0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_324
|
|
{0x4326, 0x00E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_326
|
|
{0x4328, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_328
|
|
{0x432A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32A
|
|
{0x432C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32C
|
|
{0x432E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_32E
|
|
{0x4330, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_330
|
|
{0x4332, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_332
|
|
{0x4334, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_334
|
|
{0x4336, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_336
|
|
{0x4338, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_338
|
|
{0x433A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_33A
|
|
{0x433C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_33C
|
|
{0x433E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_33E
|
|
{0x4340, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_340
|
|
{0x4342, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_342
|
|
{0x4344, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_344
|
|
{0x4346, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_346
|
|
{0x4348, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_348
|
|
{0x434A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34A
|
|
{0x434C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34C
|
|
{0x434E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_34E
|
|
{0x4350, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_350
|
|
{0x4352, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_352
|
|
{0x4354, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_354
|
|
{0x4356, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_356
|
|
{0x4358, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_358
|
|
{0x435A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_35A
|
|
{0x435C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_35C
|
|
{0x435E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_35E
|
|
{0x4360, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_360
|
|
{0x4362, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_362
|
|
{0x4364, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_364
|
|
{0x4366, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_366
|
|
{0x4368, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_368
|
|
{0x436A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36A
|
|
{0x436C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36C
|
|
{0x436E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_36E
|
|
{0x4370, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_370
|
|
{0x4372, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_372
|
|
{0x4374, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_374
|
|
{0x4376, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_376
|
|
{0x4378, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_378
|
|
{0x437A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_37A
|
|
{0x437C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_37C
|
|
{0x437E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_37E
|
|
{0x4380, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_380
|
|
{0x4382, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_382
|
|
{0x4384, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_384
|
|
{0x4386, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_386
|
|
{0x4388, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_388
|
|
{0x438A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38A
|
|
{0x438C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38C
|
|
{0x438E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_38E
|
|
{0x4390, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_390
|
|
{0x4392, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_392
|
|
{0x4394, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_394
|
|
{0x4396, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_396
|
|
{0x4398, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_398
|
|
{0x439A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_39A
|
|
{0x439C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_39C
|
|
{0x439E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_39E
|
|
{0x43A0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A0
|
|
{0x43A2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A2
|
|
{0x43A4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A4
|
|
{0x43A6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A6
|
|
{0x43A8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3A8
|
|
{0x43AA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3AA
|
|
{0x43AC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3AC
|
|
{0x43AE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3AE
|
|
{0x43B0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B0
|
|
{0x43B2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B2
|
|
{0x43B4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B4
|
|
{0x43B6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B6
|
|
{0x43B8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3B8
|
|
{0x43BA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3BA
|
|
{0x43BC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3BC
|
|
{0x43BE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3BE
|
|
{0x43C0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C0
|
|
{0x43C2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C2
|
|
{0x43C4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C4
|
|
{0x43C6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C6
|
|
{0x43C8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3C8
|
|
{0x43CA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3CA
|
|
{0x43CC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3CC
|
|
{0x43CE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3CE
|
|
{0x43D0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D0
|
|
{0x43D2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D2
|
|
{0x43D4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D4
|
|
{0x43D6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D6
|
|
{0x43D8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3D8
|
|
{0x43DA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3DA
|
|
{0x43DC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3DC
|
|
{0x43DE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3DE
|
|
{0x43E0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E0
|
|
{0x43E2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E2
|
|
{0x43E4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E4
|
|
{0x43E6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E6
|
|
{0x43E8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3E8
|
|
{0x43EA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3EA
|
|
{0x43EC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3EC
|
|
{0x43EE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3EE
|
|
{0x43F0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F0
|
|
{0x43F2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F2
|
|
{0x43F4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F4
|
|
{0x43F6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F6
|
|
{0x43F8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3F8
|
|
{0x43FA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3FA
|
|
{0x43FC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3FC
|
|
{0x43FE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_3FE
|
|
{0x4400, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_400
|
|
{0x4402, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_402
|
|
{0x4404, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_404
|
|
{0x4406, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_406
|
|
{0x4408, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_408
|
|
{0x440A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40A
|
|
{0x440C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40C
|
|
{0x440E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_40E
|
|
{0x4410, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_410
|
|
{0x4412, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_412
|
|
{0x4414, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_414
|
|
{0x4416, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_416
|
|
{0x4418, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_418
|
|
{0x441A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_41A
|
|
{0x441C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_41C
|
|
{0x441E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_41E
|
|
{0x4420, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_420
|
|
{0x4422, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_422
|
|
{0x4424, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_424
|
|
{0x4426, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_426
|
|
{0x4428, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_428
|
|
{0x442A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42A
|
|
{0x442C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42C
|
|
{0x442E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_42E
|
|
{0x4430, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_430
|
|
{0x4432, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_432
|
|
{0x4434, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_434
|
|
{0x4436, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_436
|
|
{0x4438, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_438
|
|
{0x443A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_43A
|
|
{0x443C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_43C
|
|
{0x443E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_43E
|
|
{0x4440, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_440
|
|
{0x4442, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_442
|
|
{0x4444, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_444
|
|
{0x4446, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_446
|
|
{0x4448, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_448
|
|
{0x444A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44A
|
|
{0x444C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44C
|
|
{0x444E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_44E
|
|
{0x4450, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_450
|
|
{0x4452, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_452
|
|
{0x4454, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_454
|
|
{0x4456, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_456
|
|
{0x4458, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_458
|
|
{0x445A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_45A
|
|
{0x445C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_45C
|
|
{0x445E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_45E
|
|
{0x4460, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_460
|
|
{0x4462, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_462
|
|
{0x4464, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_464
|
|
{0x4466, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_466
|
|
{0x4468, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_468
|
|
{0x446A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46A
|
|
{0x446C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46C
|
|
{0x446E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_46E
|
|
{0x4470, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_470
|
|
{0x4472, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_472
|
|
{0x4474, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_474
|
|
{0x4476, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_476
|
|
{0x4478, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_478
|
|
{0x447A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_47A
|
|
{0x447C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_47C
|
|
{0x447E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_47E
|
|
{0x4480, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_480
|
|
{0x4482, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_482
|
|
{0x4484, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_484
|
|
{0x4486, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_486
|
|
{0x4488, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_488
|
|
{0x448A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48A
|
|
{0x448C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48C
|
|
{0x448E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_48E
|
|
{0x4490, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_490
|
|
{0x4492, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_492
|
|
{0x4494, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_494
|
|
{0x4496, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_496
|
|
{0x4498, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_498
|
|
{0x449A, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_49A
|
|
{0x449C, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_49C
|
|
{0x449E, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_49E
|
|
{0x44A0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A0
|
|
{0x44A2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A2
|
|
{0x44A4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A4
|
|
{0x44A6, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A6
|
|
{0x44A8, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4A8
|
|
{0x44AA, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4AA
|
|
{0x44AC, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4AC
|
|
{0x44AE, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4AE
|
|
{0x44B0, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4B0
|
|
{0x44B2, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4B2
|
|
{0x44B4, 0xE0E0, AR2020_REG_VALUE_16BIT},//DYNAMIC_SEQRAM_4B4
|
|
{0x5500, 0x0000, AR2020_REG_VALUE_16BIT},//AGAIN_LUT0
|
|
{0x5502, 0x0002, AR2020_REG_VALUE_16BIT},//AGAIN_LUT1
|
|
{0x5504, 0x0006, AR2020_REG_VALUE_16BIT},//AGAIN_LUT2
|
|
{0x5506, 0x0009, AR2020_REG_VALUE_16BIT},//AGAIN_LUT3
|
|
{0x5508, 0x000F, AR2020_REG_VALUE_16BIT},//AGAIN_LUT4
|
|
{0x550A, 0x0010, AR2020_REG_VALUE_16BIT},//AGAIN_LUT5
|
|
{0x550C, 0x0011, AR2020_REG_VALUE_16BIT},//AGAIN_LUT6
|
|
{0x550E, 0x0012, AR2020_REG_VALUE_16BIT},//AGAIN_LUT7
|
|
{0x5510, 0x0019, AR2020_REG_VALUE_16BIT},//AGAIN_LUT8
|
|
{0x5512, 0x0020, AR2020_REG_VALUE_16BIT},//AGAIN_LUT9
|
|
{0x5514, 0x0021, AR2020_REG_VALUE_16BIT},//AGAIN_LUT10
|
|
{0x5516, 0x0023, AR2020_REG_VALUE_16BIT},//AGAIN_LUT11
|
|
{0x5518, 0x0026, AR2020_REG_VALUE_16BIT},//AGAIN_LUT12
|
|
{0x551A, 0x002B, AR2020_REG_VALUE_16BIT},//AGAIN_LUT13
|
|
{0x551C, 0x002F, AR2020_REG_VALUE_16BIT},//AGAIN_LUT14
|
|
{0x551E, 0x0030, AR2020_REG_VALUE_16BIT},//AGAIN_LUT15
|
|
{0x5400, 0x0100, AR2020_REG_VALUE_16BIT},//GT1_COARSE0
|
|
{0x5402, 0x2106, AR2020_REG_VALUE_16BIT},//GT1_COARSE1
|
|
{0x5404, 0x1101, AR2020_REG_VALUE_16BIT},//GT1_COARSE2
|
|
{0x5406, 0x3106, AR2020_REG_VALUE_16BIT},//GT1_COARSE3
|
|
{0x5408, 0x7100, AR2020_REG_VALUE_16BIT},//GT1_COARSE4
|
|
{0x540A, 0x8107, AR2020_REG_VALUE_16BIT},//GT1_COARSE5
|
|
{0x540C, 0xB101, AR2020_REG_VALUE_16BIT},//GT1_COARSE6
|
|
{0x540E, 0xD101, AR2020_REG_VALUE_16BIT},//GT1_COARSE7
|
|
{0x5410, 0xF12E, AR2020_REG_VALUE_16BIT},//GT1_COARSE8
|
|
{0x5412, 0xF112, AR2020_REG_VALUE_16BIT},//GT1_COARSE9
|
|
{0x5414, 0xF184, AR2020_REG_VALUE_16BIT},//GT1_COARSE10
|
|
{0x5416, 0xF224, AR2020_REG_VALUE_16BIT},//GT1_COARSE11
|
|
{0x5418, 0xF306, AR2020_REG_VALUE_16BIT},//GT1_COARSE12
|
|
{0x541A, 0xF446, AR2020_REG_VALUE_16BIT},//GT1_COARSE13
|
|
{0x541C, 0xF609, AR2020_REG_VALUE_16BIT},//GT1_COARSE14
|
|
{0x541E, 0xF887, AR2020_REG_VALUE_16BIT},//GT1_COARSE15
|
|
{0x5420, 0xFC0B, AR2020_REG_VALUE_16BIT},//GT1_COARSE16
|
|
{0x5422, 0xFC0B, AR2020_REG_VALUE_16BIT},//GT1_COARSE17
|
|
{0x5424, 0xFFFA, AR2020_REG_VALUE_16BIT},//GT1_DCG_ATTN_SET0
|
|
{0x5426, 0x5557, AR2020_REG_VALUE_16BIT},//GT1_DCG_ATTN_SET1
|
|
{0x5428, 0x0005, AR2020_REG_VALUE_16BIT},//GT1_DCG_ATTN_SET2
|
|
{0x542A, 0xA550, AR2020_REG_VALUE_16BIT},//GT1_ZONE_SET0
|
|
{0x542C, 0xAAAA, AR2020_REG_VALUE_16BIT},//GT1_ZONE_SET1
|
|
{0x542E, 0x000A, AR2020_REG_VALUE_16BIT},//GT1_ZONE_SET2
|
|
{0x5460, 0x2269, AR2020_REG_VALUE_16BIT},//ZT1_REG0_ADDR
|
|
{0x5462, 0x0B87, AR2020_REG_VALUE_16BIT},//ZT1_REG0_VALUE0
|
|
{0x5464, 0x0B87, AR2020_REG_VALUE_16BIT},//ZT1_REG0_VALUE1
|
|
{0x5466, 0x0983, AR2020_REG_VALUE_16BIT},//ZT1_REG0_VALUE2
|
|
{0x5498, 0x225E, AR2020_REG_VALUE_16BIT},//ZT1_REG7_ADDR
|
|
{0x549A, 0xBCAA, AR2020_REG_VALUE_16BIT},//ZT1_REG7_VALUE0
|
|
{0x549C, 0xBCAA, AR2020_REG_VALUE_16BIT},//ZT1_REG7_VALUE1
|
|
{0x549E, 0xBDAA, AR2020_REG_VALUE_16BIT},//ZT1_REG7_VALUE2
|
|
{0x3060, 0xFF01, AR2020_REG_VALUE_16BIT},//GAIN_TABLE_CTRL
|
|
{0x44BA, 0x0050, AR2020_REG_VALUE_16BIT},//DAC_LD_4_5
|
|
{0x44BC, 0xBCAA, AR2020_REG_VALUE_16BIT},//DAC_LD_6_7
|
|
{0x44C0, 0x4070, AR2020_REG_VALUE_16BIT},//DAC_LD_10_11
|
|
{0x44C4, 0x04D0, AR2020_REG_VALUE_16BIT},//DAC_LD_14_15
|
|
{0x44C6, 0x17E2, AR2020_REG_VALUE_16BIT},//DAC_LD_16_17
|
|
{0x44C8, 0xEA43, AR2020_REG_VALUE_16BIT},//DAC_LD_18_19
|
|
{0x44CA, 0x000E, AR2020_REG_VALUE_16BIT},//DAC_LD_20_21
|
|
{0x44CC, 0x7777, AR2020_REG_VALUE_16BIT},//DAC_LD_22_23
|
|
{0x44CE, 0x8BA4, AR2020_REG_VALUE_16BIT},//DAC_LD_24_25
|
|
{0x44D0, 0x1735, AR2020_REG_VALUE_16BIT},//DAC_LD_26_27
|
|
{0x44D2, 0x0B87, AR2020_REG_VALUE_16BIT},//DAC_LD_28_29
|
|
{0x44D4, 0x0000, AR2020_REG_VALUE_16BIT},//DAC_LD_30_31
|
|
{0x44D6, 0xF206, AR2020_REG_VALUE_16BIT},//DAC_LD_32_33
|
|
{0x44D8, 0xAAFA, AR2020_REG_VALUE_16BIT},//DAC_LD_34_35
|
|
{0x44DA, 0xE001, AR2020_REG_VALUE_16BIT},//DAC_LD_36_37
|
|
{0x44DE, 0x9BBC, AR2020_REG_VALUE_16BIT},//DAC_LD_40_41
|
|
{0x44E0, 0x283C, AR2020_REG_VALUE_16BIT},//DAC_LD_42_43
|
|
{0x44E2, 0x2821, AR2020_REG_VALUE_16BIT},//DAC_LD_44_45
|
|
{0x44E4, 0x8000, AR2020_REG_VALUE_16BIT},//DAC_LD_46_47
|
|
{0x44E6, 0x503F, AR2020_REG_VALUE_16BIT},//DAC_LD_48_49
|
|
{0x32A4, 0x0000, AR2020_REG_VALUE_16BIT},//CRM_CTRL
|
|
{0x328E, 0x0004, AR2020_REG_VALUE_16BIT},//ADDR_CTRL
|
|
{0x333C, 0x0001, AR2020_REG_VALUE_16BIT},//DYNAMIC_CTRL
|
|
{0x301A, 0x0000, AR2020_REG_VALUE_16BIT},//RESET_REGISTER
|
|
{0x3600, 0x94DF, AR2020_REG_VALUE_16BIT},//FDOC_CTRL
|
|
{0x3616, 0x0000, AR2020_REG_VALUE_16BIT},//FDOC_CTRL2
|
|
{0x3700, 0x0001, AR2020_REG_VALUE_16BIT},//PIX_DEF_ID
|
|
{0x3980, 0x0003, AR2020_REG_VALUE_16BIT},//PIX_DEF_CORR
|
|
{0x36C0, 0x0001, AR2020_REG_VALUE_16BIT},//DIGITAL_GAIN_CTRL
|
|
{0x36DE, 0x002A, AR2020_REG_VALUE_16BIT},//DATA_PEDESTAL1
|
|
{0x301A, 0x0008, AR2020_REG_VALUE_16BIT},//RESET_REGISTER
|
|
{0x3060, 0x0000, AR2020_REG_VALUE_16BIT},//GAIN_TABLE_CTRL
|
|
{0x3982, 0xAC70, AR2020_REG_VALUE_16BIT},//PDC_DYN_EDGE_THRES
|
|
{0x3984, 0xFA98, AR2020_REG_VALUE_16BIT},//PDC_DYN_LO_DEFECT_THRES
|
|
{0x3986, 0xFC3F, AR2020_REG_VALUE_16BIT},//PDC_DYN_HI_DEFECT_THRES
|
|
{0x3988, 0xAC70, AR2020_REG_VALUE_16BIT},//PDC_DYN_EDGE_THRES_T2
|
|
{0x398A, 0xFA98, AR2020_REG_VALUE_16BIT},//PDC_DYN_LO_DEFECT_THRES_T2
|
|
{0x398C, 0xFC3F, AR2020_REG_VALUE_16BIT},//PDC_DYN_HI_DEFECT_THRES_T2
|
|
{0x3980, 0x0003, AR2020_REG_VALUE_16BIT},//PIX_DEF_CORR
|
|
{0x3060, 0xFF01, AR2020_REG_VALUE_16BIT},//GAIN_TABLE_CTRL
|
|
{0x3340, 0x0C60, AR2020_REG_VALUE_16BIT},//OTPM_CTRL
|
|
{0x3340, 0x1C60, AR2020_REG_VALUE_16BIT},//OTPM_CTRL
|
|
{0x0101, 0x01, AR2020_REG_VALUE_08BIT},//Bing added, this is for H mirror FLIP.
|
|
{0x0100, 0x01, AR2020_REG_VALUE_08BIT},//MODE_SELECT
|
|
{0x44D6, 0xB206, AR2020_REG_VALUE_16BIT},//DAC_LD_32_33
|
|
|
|
{REG_NULL, 0x00, AR2020_REG_VALUE_16BIT},
|
|
};
|
|
|
|
|
|
static const s64 link_freq_menu_items[] = {
|
|
MIPI_FREQ_600M,
|
|
MIPI_FREQ_860M,
|
|
};
|
|
|
|
#define MIPI_FREQ_600M_INDEX 0
|
|
#define MIPI_FREQ_860M_INDEX 1
|
|
#define MIPI_FREQ_MAX_INDEX 2
|
|
/*
|
|
* The width and height must be configured to be
|
|
* the same as the current output resolution of the sensor.
|
|
* The input width of the isp needs to be 16 aligned.
|
|
* The input height of the isp needs to be 8 aligned.
|
|
* If the width or height does not meet the alignment rules,
|
|
* you can configure the cropping parameters with the following function to
|
|
* crop out the appropriate resolution.
|
|
* struct v4l2_subdev_pad_ops {
|
|
* .get_selection
|
|
* }
|
|
*/
|
|
|
|
/* Config resolution ,LLPCLK, FLL, exposure time,fps, MIPI channel config, HDR mode , open.k */
|
|
static const struct ar2020_mode supported_modes[] = {
|
|
{
|
|
.bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,//H mirrored, so color format changed.
|
|
.width = 5120,
|
|
.height = 3840,
|
|
.max_fps = {
|
|
.numerator = 10000,
|
|
.denominator = 300000,
|
|
},
|
|
.exp_def = 0x0240,
|
|
//reg 0342,for linear mode,hblank is 4*LINE_LENGTH_PCK_-WIDTH,so hts is 4*LINE_LENGTH_PCK_
|
|
.hts_def = 0x2DF0,
|
|
.vts_def = 0x0F28,//reg 0340
|
|
.reg_list = ar2020_linear_5120x3840_30fps_regs,
|
|
.hdr_mode = NO_HDR,
|
|
.mipi_freq = MIPI_FREQ_860M_INDEX,
|
|
.mipi_rate = MIPI_FREQ_860M / AR2020_BPP * 2 * AR2020_LANES,
|
|
.reg_mode = INITIAL_STREAMING,
|
|
.mclk = AR2020_XVCLK_FREQ_20M,
|
|
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
|
|
},
|
|
{
|
|
.bus_fmt = MEDIA_BUS_FMT_SGRBG12_1X12,
|
|
.width = 5120,
|
|
.height = 3840,
|
|
.max_fps = {
|
|
.numerator = 10000,
|
|
.denominator = 300000,
|
|
},
|
|
.exp_def = 0x0240,
|
|
//for HDR,hblank is 4*LINE_LENGTH_PCK_-WIDTH*2,so hts is 4*LINE_LENGTH_PCK_-WIDTH.
|
|
.hts_def = 0x2e30,
|
|
.vts_def = 0x0f1e,
|
|
.reg_list = ar2020_edr12bit_5120x3840_30fps_8lane_regs,
|
|
.hdr_mode = NO_HDR,
|
|
.mipi_freq = MIPI_FREQ_860M_INDEX,
|
|
.mipi_rate = MIPI_FREQ_860M / AR2020_BPP * 2 * AR2020_LANES,
|
|
.mclk = AR2020_XVCLK_FREQ_27M,
|
|
.reg_mode = INITIAL_STREAMING,
|
|
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
|
|
},
|
|
{
|
|
.bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
|
|
.width = 5120,
|
|
.height = 3840,
|
|
.max_fps = {
|
|
.numerator = 10000,
|
|
.denominator = 440000,
|
|
},
|
|
.exp_def = 0x0240,
|
|
//for linear mode, hblank is 4*LINE_LENGTH_PCK_-WIDTH,so hts is 4*LINE_LENGTH_PCK_.
|
|
.hts_def = 0x4790,
|
|
.vts_def = 0x0F1E,
|
|
.reg_list = ar2020_linear_8lane_global_regs,
|
|
.hdr_mode = NO_HDR,
|
|
.mipi_freq = MIPI_FREQ_600M_INDEX,
|
|
.mipi_rate = MIPI_FREQ_600M / AR2020_BPP * 2 * AR2020_LANES,
|
|
.mclk = AR2020_XVCLK_FREQ_20M,
|
|
.reg_mode = INITIAL_STREAMING,
|
|
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
|
|
},
|
|
{
|
|
.bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
|
|
.width = 5120,
|
|
.height = 3840,
|
|
.max_fps = {
|
|
.numerator = 10000,
|
|
.denominator = 300000,
|
|
},
|
|
.exp_def = 0x0240,
|
|
//for HDR,hblank is 4*LINE_LENGTH_PCK_-WIDTH*2,so hts is 4*LINE_LENGTH_PCK_-WIDTH.
|
|
.hts_def = 0x1718,
|
|
.vts_def = 0x1E3C,
|
|
.reg_list = ar2020_hdr10bit_5120x3840_30fps_8lane_regs,
|
|
.hdr_mode = HDR_X2,
|
|
.mipi_freq = MIPI_FREQ_860M_INDEX,
|
|
.mipi_rate = MIPI_FREQ_860M / AR2020_BPP * 2 * AR2020_LANES,
|
|
.mclk = AR2020_XVCLK_FREQ_27M,
|
|
.reg_mode = INITIAL_STREAMING,
|
|
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
|
|
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
|
|
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
|
|
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
|
|
},
|
|
{
|
|
.bus_fmt = MEDIA_BUS_FMT_SGRBG10_1X10,
|
|
.width = 5120,
|
|
.height = 3840,
|
|
.max_fps = {
|
|
.numerator = 10000,
|
|
.denominator = 220000,
|
|
},
|
|
.exp_def = 0x0240,
|
|
//for HDR,hblank is 4*LINE_LENGTH_PCK_-WIDTH*2,so hts is 4*LINE_LENGTH_PCK_-WIDTH.
|
|
.hts_def = 0x4790,
|
|
.vts_def = 0x1E3C,
|
|
.reg_list = ar2020_hdr10bit_5120x3840_22fps_8lane_regs,
|
|
.hdr_mode = HDR_X2,
|
|
.mipi_freq = MIPI_FREQ_600M_INDEX,
|
|
.mipi_rate = MIPI_FREQ_600M / AR2020_BPP * 2 * AR2020_LANES,
|
|
.mclk = AR2020_XVCLK_FREQ_20M,
|
|
.reg_mode = INITIAL_STREAMING,
|
|
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
|
|
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
|
|
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
|
|
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
|
|
},
|
|
};
|
|
|
|
|
|
/* use ar2020_enable_test_pattern to config test pattern mode here, open.k */
|
|
static const char * const ar2020_test_pattern_menu[] = {
|
|
"Disabled",
|
|
"Vertical Color Bar Type 1",
|
|
"Vertical Color Bar Type 2",
|
|
"Vertical Color Bar Type 3",
|
|
"Vertical Color Bar Type 4"
|
|
};
|
|
|
|
static int __ar2020_power_on(struct ar2020 *ar2020);
|
|
static int ar2020_set_mclk(struct ar2020 *ar2020)
|
|
{
|
|
int ret = 0;
|
|
struct device *dev = &ar2020->client->dev;
|
|
|
|
ret = clk_set_rate(ar2020->xvclk, ar2020->cur_mode->mclk);
|
|
if (ret < 0)
|
|
dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
|
|
if (clk_get_rate(ar2020->xvclk) != ar2020->cur_mode->mclk) {
|
|
dev_err(dev, "xvclk set mclk failed, value still %ld\n",
|
|
clk_get_rate(ar2020->xvclk));
|
|
ret = -EINVAL;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/* Write registers up to 4 at a time */
|
|
static int ar2020_write_reg(struct i2c_client *client, u16 reg,
|
|
u32 len, u32 val)
|
|
{
|
|
u32 buf_i, val_i;
|
|
u8 buf[6];
|
|
u8 *val_p;
|
|
__be32 val_be;
|
|
|
|
if (len > 4)
|
|
return -EINVAL;
|
|
|
|
buf[0] = reg >> 8;
|
|
buf[1] = reg & 0xff;
|
|
|
|
val_be = cpu_to_be32(val);
|
|
val_p = (u8 *)&val_be;
|
|
buf_i = 2;
|
|
val_i = 4 - len;
|
|
|
|
while (val_i < 4)
|
|
buf[buf_i++] = val_p[val_i++];
|
|
|
|
if (i2c_master_send(client, buf, len + 2) != len + 2)
|
|
return -EIO;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ar2020_write_array(struct i2c_client *client,
|
|
const struct regval *regs)
|
|
{
|
|
u32 i;
|
|
int ret = 0;
|
|
|
|
for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
|
|
if (unlikely(regs[i].addr == REG_DELAY))
|
|
usleep_range(regs[i].val * 200, regs[i].val * 250);
|
|
else
|
|
ret |= ar2020_write_reg(client, regs[i].addr,
|
|
regs[i].bits, regs[i].val);
|
|
|
|
if (ret != 0)
|
|
dev_err(&client->dev, "write reg %x with val %x failed, ret: %d\n",
|
|
regs[i].addr, regs[i].val, ret);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/* Read registers up to 4 at a time */
|
|
static int ar2020_read_reg(struct i2c_client *client,
|
|
u16 reg,
|
|
unsigned int len,
|
|
u32 *val)
|
|
{
|
|
struct i2c_msg msgs[2];
|
|
u8 *data_be_p;
|
|
__be32 data_be = 0;
|
|
__be16 reg_addr_be = cpu_to_be16(reg);
|
|
int ret;
|
|
|
|
if (len > 4 || !len)
|
|
return -EINVAL;
|
|
|
|
data_be_p = (u8 *)&data_be;
|
|
/* Write register address */
|
|
msgs[0].addr = client->addr;
|
|
msgs[0].flags = 0;
|
|
msgs[0].len = 2;
|
|
msgs[0].buf = (u8 *)®_addr_be;
|
|
|
|
/* Read data from register */
|
|
msgs[1].addr = client->addr;
|
|
msgs[1].flags = I2C_M_RD;
|
|
msgs[1].len = len;
|
|
msgs[1].buf = &data_be_p[4 - len];
|
|
|
|
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
|
|
if (ret != ARRAY_SIZE(msgs))
|
|
return -EIO;
|
|
|
|
*val = be32_to_cpu(data_be);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ar2020_get_reso_dist(const struct ar2020_mode *mode,
|
|
struct v4l2_mbus_framefmt *framefmt)
|
|
{
|
|
return abs(mode->width - framefmt->width) +
|
|
abs(mode->height - framefmt->height);
|
|
}
|
|
|
|
static const struct ar2020_mode *
|
|
ar2020_find_best_fit(struct ar2020 *ar2020, struct v4l2_subdev_format *fmt)
|
|
{
|
|
struct v4l2_mbus_framefmt *framefmt = &fmt->format;
|
|
int dist;
|
|
int cur_best_fit = 0;
|
|
int cur_best_fit_dist = -1;
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ar2020->cfg_num; i++) {
|
|
dist = ar2020_get_reso_dist(&supported_modes[i], framefmt);
|
|
if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) &&
|
|
(supported_modes[i].bus_fmt == framefmt->code)) {
|
|
cur_best_fit_dist = dist;
|
|
cur_best_fit = i;
|
|
}
|
|
}
|
|
|
|
return &supported_modes[cur_best_fit];
|
|
}
|
|
static int ar2020_set_rates(struct ar2020 *ar2020)
|
|
{
|
|
const struct ar2020_mode *mode = ar2020->cur_mode;
|
|
s64 h_blank, vblank_def;
|
|
int ret = 0;
|
|
|
|
h_blank = mode->hts_def - mode->width;
|
|
__v4l2_ctrl_modify_range(ar2020->hblank, h_blank,
|
|
h_blank, 1, h_blank);
|
|
vblank_def = mode->vts_def - mode->height;
|
|
__v4l2_ctrl_modify_range(ar2020->vblank, vblank_def,
|
|
AR2020_VTS_MAX - mode->height,
|
|
1, vblank_def);
|
|
|
|
__v4l2_ctrl_s_ctrl_int64(ar2020->pixel_rate,
|
|
mode->mipi_rate);
|
|
__v4l2_ctrl_s_ctrl(ar2020->link_freq,
|
|
mode->mipi_freq);
|
|
|
|
return ret;
|
|
}
|
|
/* setup sensor work format to determine the MIPI speed, open.k */
|
|
static int ar2020_set_fmt(struct v4l2_subdev *sd,
|
|
struct v4l2_subdev_pad_config *cfg,
|
|
struct v4l2_subdev_format *fmt)
|
|
{
|
|
struct ar2020 *ar2020 = to_ar2020(sd);
|
|
const struct ar2020_mode *mode;
|
|
|
|
mutex_lock(&ar2020->mutex);
|
|
|
|
mode = ar2020_find_best_fit(ar2020, fmt);
|
|
fmt->format.code = mode->bus_fmt;
|
|
fmt->format.width = mode->width;
|
|
fmt->format.height = mode->height;
|
|
fmt->format.field = V4L2_FIELD_NONE;
|
|
if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
|
|
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
|
|
*v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
|
|
#else
|
|
mutex_unlock(&ar2020->mutex);
|
|
return -ENOTTY;
|
|
#endif
|
|
} else {
|
|
ar2020->cur_mode = mode;
|
|
if (ar2020->cur_mclk != mode->mclk) {
|
|
if (ar2020_set_mclk(ar2020) == 0)
|
|
ar2020->cur_mclk = mode->mclk;
|
|
}
|
|
ar2020_set_rates(ar2020);
|
|
}
|
|
|
|
mutex_unlock(&ar2020->mutex);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ar2020_get_fmt(struct v4l2_subdev *sd,
|
|
struct v4l2_subdev_pad_config *cfg,
|
|
struct v4l2_subdev_format *fmt)
|
|
{
|
|
struct ar2020 *ar2020 = to_ar2020(sd);
|
|
const struct ar2020_mode *mode = ar2020->cur_mode;
|
|
|
|
mutex_lock(&ar2020->mutex);
|
|
if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
|
|
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
|
|
fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
|
|
#else
|
|
mutex_unlock(&ar2020->mutex);
|
|
return -ENOTTY;
|
|
#endif
|
|
} else {
|
|
fmt->format.width = mode->width;
|
|
fmt->format.height = mode->height;
|
|
fmt->format.code = mode->bus_fmt;
|
|
fmt->format.field = V4L2_FIELD_NONE;
|
|
if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
|
|
fmt->reserved[0] = mode->vc[fmt->pad];
|
|
else
|
|
fmt->reserved[0] = mode->vc[PAD0];
|
|
}
|
|
mutex_unlock(&ar2020->mutex);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ar2020_enum_mbus_code(struct v4l2_subdev *sd,
|
|
struct v4l2_subdev_pad_config *cfg,
|
|
struct v4l2_subdev_mbus_code_enum *code)
|
|
{
|
|
struct ar2020 *ar2020 = to_ar2020(sd);
|
|
|
|
if (code->index >= ar2020->cfg_num)
|
|
return -EINVAL;
|
|
code->code = supported_modes[code->index].bus_fmt;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ar2020_enum_frame_sizes(struct v4l2_subdev *sd,
|
|
struct v4l2_subdev_pad_config *cfg,
|
|
struct v4l2_subdev_frame_size_enum *fse)
|
|
{
|
|
struct ar2020 *ar2020 = to_ar2020(sd);
|
|
|
|
if (fse->index >= ar2020->cfg_num)
|
|
return -EINVAL;
|
|
|
|
if (fse->code != supported_modes[fse->index].bus_fmt)
|
|
return -EINVAL;
|
|
|
|
fse->min_width = supported_modes[fse->index].width;
|
|
fse->max_width = supported_modes[fse->index].width;
|
|
fse->max_height = supported_modes[fse->index].height;
|
|
fse->min_height = supported_modes[fse->index].height;
|
|
|
|
return 0;
|
|
}
|
|
/* use ar2020_enable_test_pattern to config test pattern mode here, open.k */
|
|
static int ar2020_enable_test_pattern(struct ar2020 *ar2020, u32 pattern)
|
|
{
|
|
int ret = 0;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ar2020_g_frame_interval(struct v4l2_subdev *sd,
|
|
struct v4l2_subdev_frame_interval *fi)
|
|
{
|
|
struct ar2020 *ar2020 = to_ar2020(sd);
|
|
const struct ar2020_mode *mode = ar2020->cur_mode;
|
|
|
|
mutex_lock(&ar2020->mutex);
|
|
fi->interval = mode->max_fps;
|
|
mutex_unlock(&ar2020->mutex);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ar2020_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
|
|
struct v4l2_mbus_config *config)
|
|
{
|
|
struct ar2020 *ar2020 = to_ar2020(sd);
|
|
const struct ar2020_mode *mode = ar2020->cur_mode;
|
|
u32 val = 0;
|
|
|
|
val = 1 << (AR2020_LANES - 1) |
|
|
V4L2_MBUS_CSI2_CHANNEL_0 |
|
|
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
|
|
if (mode->hdr_mode != NO_HDR)
|
|
val |= V4L2_MBUS_CSI2_CHANNEL_1;
|
|
if (mode->hdr_mode == HDR_X3)
|
|
val |= V4L2_MBUS_CSI2_CHANNEL_2;
|
|
|
|
config->type = V4L2_MBUS_CSI2_DPHY;
|
|
config->flags = val;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static void ar2020_get_module_inf(struct ar2020 *ar2020,
|
|
struct rkmodule_inf *inf)
|
|
{
|
|
memset(inf, 0, sizeof(*inf));
|
|
strscpy(inf->base.sensor, AR2020_NAME, sizeof(inf->base.sensor));
|
|
strscpy(inf->base.module, ar2020->module_name,
|
|
sizeof(inf->base.module));
|
|
strscpy(inf->base.lens, ar2020->len_name, sizeof(inf->base.lens));
|
|
}
|
|
|
|
static int ar2020_set_hdrae(struct ar2020 *ar2020,
|
|
struct preisp_hdrae_exp_s *ae)
|
|
{
|
|
u32 l_exp_time, m_exp_time, s_exp_time;
|
|
u32 l_a_gain, m_a_gain, s_a_gain;
|
|
int ret = 0;
|
|
u32 gain_val = 0;
|
|
|
|
if (!ar2020->has_init_exp && !ar2020->streaming) {
|
|
ar2020->init_hdrae_exp = *ae;
|
|
ar2020->has_init_exp = true;
|
|
dev_err(&ar2020->client->dev, "ar2020 don't stream, record exp for hdr!\n");
|
|
return ret;
|
|
}
|
|
l_exp_time = ae->long_exp_reg;
|
|
m_exp_time = ae->middle_exp_reg;
|
|
s_exp_time = ae->short_exp_reg;
|
|
l_a_gain = ae->long_gain_reg;
|
|
m_a_gain = ae->middle_gain_reg;
|
|
s_a_gain = ae->short_gain_reg;
|
|
dev_dbg(&ar2020->client->dev,
|
|
"Bing irev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
|
|
l_exp_time, l_a_gain,
|
|
m_exp_time, m_a_gain,
|
|
s_exp_time, s_a_gain);
|
|
|
|
if (ar2020->cur_mode->hdr_mode == HDR_X2) {
|
|
//2 stagger
|
|
l_a_gain = m_a_gain;
|
|
l_exp_time = m_exp_time;
|
|
m_a_gain = s_a_gain;
|
|
m_exp_time = s_exp_time;
|
|
}
|
|
|
|
l_a_gain = (l_a_gain > AR2020_GAIN_MAX) ? AR2020_GAIN_MAX : l_a_gain;
|
|
m_a_gain = (m_a_gain > AR2020_GAIN_MAX) ? AR2020_GAIN_MAX : m_a_gain;
|
|
|
|
l_exp_time = (l_exp_time > AR2020_CIT_MAX_T1)?AR2020_CIT_MAX_T1:l_exp_time;
|
|
m_exp_time = (m_exp_time > AR2020_CIT_MAX_T2)?AR2020_CIT_MAX_T2:m_exp_time;
|
|
|
|
ret |= ar2020_write_reg(ar2020->client,
|
|
AR2020_GROUP_UPDATE_ADDRESS,
|
|
AR2020_REG_VALUE_08BIT,
|
|
AR2020_GROUP_UPDATE_START_DATA);
|
|
|
|
|
|
gain_val = (m_a_gain << 8) + l_a_gain;
|
|
ret |= ar2020_write_reg(ar2020->client,
|
|
AR2020_REG_GAIN2,
|
|
AR2020_REG_VALUE_16BIT, gain_val);
|
|
|
|
ret |= ar2020_write_reg(ar2020->client,
|
|
AR2020_REG_EXP,
|
|
AR2020_REG_VALUE_16BIT,
|
|
l_exp_time);//T1/T2 ratio is not used here.
|
|
ret |= ar2020_write_reg(ar2020->client,
|
|
AR2020_REG_EXP_T2,
|
|
AR2020_REG_VALUE_16BIT,
|
|
m_exp_time);
|
|
ret |= ar2020_write_reg(ar2020->client,
|
|
AR2020_GROUP_UPDATE_ADDRESS,
|
|
AR2020_REG_VALUE_08BIT,
|
|
AR2020_GROUP_UPDATE_END_DATA);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ar2020_get_channel_info(struct ar2020 *ar2020, struct rkmodule_channel_info *ch_info)
|
|
{
|
|
if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
|
|
return -EINVAL;
|
|
|
|
ch_info->vc = ar2020->cur_mode->vc[ch_info->index];
|
|
ch_info->width = ar2020->cur_mode->width;
|
|
ch_info->height = ar2020->cur_mode->height;
|
|
ch_info->bus_fmt = ar2020->cur_mode->bus_fmt;
|
|
return 0;
|
|
}
|
|
|
|
static long ar2020_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
|
|
{
|
|
struct ar2020 *ar2020 = to_ar2020(sd);
|
|
struct rkmodule_hdr_cfg *hdr_cfg;
|
|
struct rkmodule_channel_info *ch_info;
|
|
long ret = 0;
|
|
u32 i, h, w;
|
|
u32 stream = 0;
|
|
struct rkmodule_capture_info *capture_info;
|
|
|
|
switch (cmd) {
|
|
case PREISP_CMD_SET_HDRAE_EXP:
|
|
ar2020_set_hdrae(ar2020, arg);
|
|
break;
|
|
case RKMODULE_SET_HDR_CFG:
|
|
hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
|
|
w = ar2020->cur_mode->width;
|
|
h = ar2020->cur_mode->height;
|
|
for (i = 0; i < ar2020->cfg_num; i++) {
|
|
if (w == supported_modes[i].width &&
|
|
h == supported_modes[i].height &&
|
|
supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
|
|
ar2020->cur_mode = &supported_modes[i];
|
|
break;
|
|
}
|
|
}
|
|
if (i == ar2020->cfg_num) {
|
|
dev_err(&ar2020->client->dev,
|
|
"not find hdr mode:%d %dx%d config\n",
|
|
hdr_cfg->hdr_mode, w, h);
|
|
ret = -EINVAL;
|
|
} else {
|
|
w = ar2020->cur_mode->hts_def - ar2020->cur_mode->width;
|
|
h = ar2020->cur_mode->vts_def - ar2020->cur_mode->height;
|
|
__v4l2_ctrl_modify_range(ar2020->hblank, w, w, 1, w);
|
|
__v4l2_ctrl_modify_range(ar2020->vblank, h,
|
|
AR2020_VTS_MAX - ar2020->cur_mode->height,
|
|
1, h);
|
|
}
|
|
if (ar2020->cur_mclk != ar2020->cur_mode->mclk) {
|
|
if (ar2020_set_mclk(ar2020) == 0)
|
|
ar2020->cur_mclk = ar2020->cur_mode->mclk;
|
|
}
|
|
ar2020_set_rates(ar2020);
|
|
break;
|
|
case RKMODULE_GET_MODULE_INFO:
|
|
ar2020_get_module_inf(ar2020, (struct rkmodule_inf *)arg);
|
|
break;
|
|
case RKMODULE_GET_HDR_CFG:
|
|
hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
|
|
hdr_cfg->esp.mode = HDR_NORMAL_VC;
|
|
hdr_cfg->hdr_mode = ar2020->cur_mode->hdr_mode;
|
|
break;
|
|
case RKMODULE_SET_QUICK_STREAM:
|
|
|
|
stream = *((u32 *)arg);
|
|
|
|
if (stream)
|
|
ret = ar2020_write_reg(ar2020->client, AR2020_REG_CTRL_MODE,
|
|
AR2020_REG_VALUE_16BIT, AR2020_MODE_STREAMING);
|
|
else
|
|
ret = ar2020_write_reg(ar2020->client, AR2020_REG_CTRL_MODE,
|
|
AR2020_REG_VALUE_16BIT, AR2020_MODE_SW_STANDBY);
|
|
break;
|
|
case RKMODULE_GET_CHANNEL_INFO:
|
|
ch_info = (struct rkmodule_channel_info *)arg;
|
|
ret = ar2020_get_channel_info(ar2020, ch_info);
|
|
break;
|
|
case RKMODULE_GET_CAPTURE_MODE:
|
|
capture_info = (struct rkmodule_capture_info *)arg;
|
|
if (ar2020->csi_lanes_in_use == 8) {
|
|
dev_info(&ar2020->client->dev, "8 lanes in use, set dual mipi mode\n");
|
|
capture_info->mode = RKMODULE_MULTI_DEV_COMBINE_ONE;
|
|
capture_info->multi_dev = ar2020->multi_dev_info;
|
|
} else {
|
|
capture_info->mode = 0;
|
|
}
|
|
break;
|
|
default:
|
|
ret = -ENOIOCTLCMD;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
static long ar2020_compat_ioctl32(struct v4l2_subdev *sd,
|
|
unsigned int cmd, unsigned long arg)
|
|
{
|
|
void __user *up = compat_ptr(arg);
|
|
struct rkmodule_inf *inf;
|
|
struct rkmodule_awb_cfg *cfg;
|
|
struct rkmodule_hdr_cfg *hdr;
|
|
struct preisp_hdrae_exp_s *hdrae;
|
|
struct rkmodule_channel_info *ch_info;
|
|
long ret;
|
|
u32 stream = 0;
|
|
struct rkmodule_capture_info *capture_info;
|
|
|
|
switch (cmd) {
|
|
case RKMODULE_GET_MODULE_INFO:
|
|
inf = kzalloc(sizeof(*inf), GFP_KERNEL);
|
|
if (!inf) {
|
|
ret = -ENOMEM;
|
|
return ret;
|
|
}
|
|
|
|
ret = ar2020_ioctl(sd, cmd, inf);
|
|
if (!ret) {
|
|
ret = copy_to_user(up, inf, sizeof(*inf));
|
|
if (ret)
|
|
ret = -EFAULT;
|
|
}
|
|
kfree(inf);
|
|
break;
|
|
case RKMODULE_AWB_CFG:
|
|
cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
|
|
if (!cfg) {
|
|
ret = -ENOMEM;
|
|
return ret;
|
|
}
|
|
|
|
ret = copy_from_user(cfg, up, sizeof(*cfg));
|
|
if (!ret)
|
|
ret = ar2020_ioctl(sd, cmd, cfg);
|
|
else
|
|
ret = -EFAULT;
|
|
kfree(cfg);
|
|
break;
|
|
case RKMODULE_GET_HDR_CFG:
|
|
hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
|
|
if (!hdr) {
|
|
ret = -ENOMEM;
|
|
return ret;
|
|
}
|
|
|
|
ret = ar2020_ioctl(sd, cmd, hdr);
|
|
if (!ret) {
|
|
ret = copy_to_user(up, hdr, sizeof(*hdr));
|
|
if (ret)
|
|
ret = -EFAULT;
|
|
} else {
|
|
ret = -EFAULT;
|
|
}
|
|
kfree(hdr);
|
|
break;
|
|
case RKMODULE_SET_HDR_CFG:
|
|
hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
|
|
if (!hdr) {
|
|
ret = -ENOMEM;
|
|
return ret;
|
|
}
|
|
|
|
ret = copy_from_user(hdr, up, sizeof(*hdr));
|
|
if (!ret)
|
|
ret = ar2020_ioctl(sd, cmd, hdr);
|
|
else
|
|
ret = -EFAULT;
|
|
kfree(hdr);
|
|
break;
|
|
case PREISP_CMD_SET_HDRAE_EXP:
|
|
hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
|
|
if (!hdrae) {
|
|
ret = -ENOMEM;
|
|
return ret;
|
|
}
|
|
|
|
ret = copy_from_user(hdrae, up, sizeof(*hdrae));
|
|
if (!ret)
|
|
ret = ar2020_ioctl(sd, cmd, hdrae);
|
|
else
|
|
ret = -EFAULT;
|
|
kfree(hdrae);
|
|
break;
|
|
case RKMODULE_SET_QUICK_STREAM:
|
|
ret = copy_from_user(&stream, up, sizeof(u32));
|
|
if (!ret)
|
|
ret = ar2020_ioctl(sd, cmd, &stream);
|
|
else
|
|
ret = -EFAULT;
|
|
break;
|
|
case RKMODULE_GET_CHANNEL_INFO:
|
|
ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
|
|
if (!ch_info) {
|
|
ret = -ENOMEM;
|
|
return ret;
|
|
}
|
|
|
|
ret = ar2020_ioctl(sd, cmd, ch_info);
|
|
if (!ret) {
|
|
ret = copy_to_user(up, ch_info, sizeof(*ch_info));
|
|
if (ret)
|
|
ret = -EFAULT;
|
|
}
|
|
kfree(ch_info);
|
|
break;
|
|
case RKMODULE_GET_CAPTURE_MODE:
|
|
capture_info = kzalloc(sizeof(*capture_info), GFP_KERNEL);
|
|
if (!capture_info) {
|
|
ret = -ENOMEM;
|
|
return ret;
|
|
}
|
|
ret = ar2020_ioctl(sd, cmd, capture_info);
|
|
if (!ret) {
|
|
ret = copy_to_user(up, capture_info, sizeof(*capture_info));
|
|
if (ret)
|
|
ret = -EFAULT;
|
|
}
|
|
kfree(capture_info);
|
|
break;
|
|
default:
|
|
ret = -ENOIOCTLCMD;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
static int __ar2020_start_stream(struct ar2020 *ar2020)
|
|
{
|
|
int ret = 0;
|
|
|
|
if (!ar2020->is_thunderboot) {
|
|
ret = ar2020_write_reg(ar2020->client,
|
|
AR2020_SOFTWARE_RESET_REG,
|
|
AR2020_REG_VALUE_08BIT,
|
|
0x0001);
|
|
usleep_range(100000, 200000);
|
|
|
|
ret |= ar2020_write_array(ar2020->client, ar2020->cur_mode->reg_list);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/* In case these controls are set before streaming */
|
|
ret = __v4l2_ctrl_handler_setup(&ar2020->ctrl_handler);
|
|
if (ret)
|
|
return ret;
|
|
if (ar2020->has_init_exp && ar2020->cur_mode->hdr_mode != NO_HDR) {
|
|
ret = ar2020_ioctl(&ar2020->subdev,
|
|
PREISP_CMD_SET_HDRAE_EXP,
|
|
&ar2020->init_hdrae_exp);
|
|
if (ret) {
|
|
dev_err(&ar2020->client->dev,
|
|
"init exp fail in hdr mode\n");
|
|
return ret;
|
|
}
|
|
}
|
|
if (ar2020->cur_mode->reg_mode == INITIAL_STREAMING)
|
|
return ret;
|
|
return ar2020_write_reg(ar2020->client, AR2020_REG_CTRL_MODE,
|
|
AR2020_REG_VALUE_08BIT, AR2020_MODE_STREAMING);
|
|
}
|
|
|
|
static int __ar2020_stop_stream(struct ar2020 *ar2020)
|
|
{
|
|
ar2020->has_init_exp = false;
|
|
if (ar2020->is_thunderboot)
|
|
ar2020->is_first_streamoff = true;
|
|
return ar2020_write_reg(ar2020->client, AR2020_REG_CTRL_MODE,
|
|
AR2020_REG_VALUE_16BIT, AR2020_MODE_SW_STANDBY);
|
|
}
|
|
|
|
static int ar2020_s_stream(struct v4l2_subdev *sd, int on)
|
|
{
|
|
struct ar2020 *ar2020 = to_ar2020(sd);
|
|
struct i2c_client *client = ar2020->client;
|
|
int ret = 0;
|
|
|
|
mutex_lock(&ar2020->mutex);
|
|
on = !!on;
|
|
if (on == ar2020->streaming)
|
|
goto unlock_and_return;
|
|
|
|
if (on) {
|
|
if (ar2020->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
|
|
ar2020->is_thunderboot = false;
|
|
__ar2020_power_on(ar2020);
|
|
}
|
|
ret = pm_runtime_get_sync(&client->dev);
|
|
if (ret < 0) {
|
|
pm_runtime_put_noidle(&client->dev);
|
|
goto unlock_and_return;
|
|
}
|
|
|
|
ret = __ar2020_start_stream(ar2020);
|
|
if (ret) {
|
|
v4l2_err(sd, "start stream failed while write regs\n");
|
|
pm_runtime_put(&client->dev);
|
|
goto unlock_and_return;
|
|
}
|
|
} else {
|
|
__ar2020_stop_stream(ar2020);
|
|
pm_runtime_put(&client->dev);
|
|
}
|
|
dev_dbg(&ar2020->client->dev, "s streaming well\n");
|
|
ar2020->streaming = on;
|
|
|
|
unlock_and_return:
|
|
mutex_unlock(&ar2020->mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ar2020_s_power(struct v4l2_subdev *sd, int on)
|
|
{
|
|
struct ar2020 *ar2020 = to_ar2020(sd);
|
|
struct i2c_client *client = ar2020->client;
|
|
int ret = 0;
|
|
|
|
mutex_lock(&ar2020->mutex);
|
|
/* If the power state is not modified - no work to do. */
|
|
if (ar2020->power_on == !!on)
|
|
goto unlock_and_return;
|
|
|
|
if (on) {
|
|
ret = pm_runtime_get_sync(&client->dev);
|
|
if (ret < 0) {
|
|
pm_runtime_put_noidle(&client->dev);
|
|
goto unlock_and_return;
|
|
}
|
|
|
|
if (!ar2020->is_thunderboot) {
|
|
ret |= ar2020_write_reg(ar2020->client,
|
|
AR2020_SOFTWARE_RESET_REG,
|
|
AR2020_REG_VALUE_16BIT,
|
|
0x0001);
|
|
usleep_range(100, 200);
|
|
}
|
|
|
|
ar2020->power_on = true;
|
|
} else {
|
|
pm_runtime_put(&client->dev);
|
|
ar2020->power_on = false;
|
|
}
|
|
|
|
unlock_and_return:
|
|
mutex_unlock(&ar2020->mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* Calculate the delay in us by clock rate and clock cycles */
|
|
static inline u32 ar2020_cal_delay(u32 cycles, struct ar2020 *ar2020)
|
|
{
|
|
return DIV_ROUND_UP(cycles, ar2020->cur_mclk / 1000 / 1000);
|
|
}
|
|
|
|
/*
|
|
* sensor power on config, need check power, MCLK, GPIO etc,,,
|
|
* need go to .dts file to change the config;
|
|
* open.k
|
|
*/
|
|
static int __ar2020_power_on(struct ar2020 *ar2020)
|
|
{
|
|
int ret;
|
|
u32 delay_us;
|
|
struct device *dev = &ar2020->client->dev;
|
|
|
|
if (ar2020->is_thunderboot)
|
|
return 0;
|
|
|
|
if (!IS_ERR_OR_NULL(ar2020->pins_default)) {
|
|
ret = pinctrl_select_state(ar2020->pinctrl,
|
|
ar2020->pins_default);
|
|
if (ret < 0)
|
|
dev_err(dev, "could not set pins\n");
|
|
}
|
|
ret = clk_set_rate(ar2020->xvclk, /*AR2020_XVCLK_FREQ*/ ar2020->cur_mode->mclk);
|
|
if (ret < 0)
|
|
dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
|
|
if (clk_get_rate(ar2020->xvclk) != ar2020->cur_mode->mclk)
|
|
dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
|
|
ret = clk_prepare_enable(ar2020->xvclk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to enable xvclk\n");
|
|
return ret;
|
|
}
|
|
ar2020->cur_mclk = ar2020->cur_mode->mclk;
|
|
|
|
ret = regulator_bulk_enable(AR2020_NUM_SUPPLIES, ar2020->supplies);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to enable regulators\n");
|
|
goto disable_clk;
|
|
}
|
|
|
|
usleep_range(500, 1000);
|
|
if (!IS_ERR(ar2020->pwdn_gpio))
|
|
gpiod_direction_output(ar2020->pwdn_gpio, 1);
|
|
/*
|
|
* There is no need to wait for the delay of RC circuit
|
|
* if the reset signal is directly controlled by GPIO.
|
|
*/
|
|
if (!IS_ERR(ar2020->reset_gpio))
|
|
usleep_range(6000, 8000);
|
|
else
|
|
usleep_range(12000, 16000);
|
|
|
|
/* 8192 cycles prior to first SCCB transaction */
|
|
delay_us = ar2020_cal_delay(8192, ar2020);
|
|
usleep_range(delay_us, delay_us * 2);
|
|
|
|
return 0;
|
|
|
|
disable_clk:
|
|
clk_disable_unprepare(ar2020->xvclk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __ar2020_power_off(struct ar2020 *ar2020)
|
|
{
|
|
int ret;
|
|
struct device *dev = &ar2020->client->dev;
|
|
|
|
if (ar2020->is_thunderboot) {
|
|
if (ar2020->is_first_streamoff) {
|
|
ar2020->is_thunderboot = false;
|
|
ar2020->is_first_streamoff = false;
|
|
} else {
|
|
return;
|
|
}
|
|
}
|
|
|
|
if (!IS_ERR(ar2020->pwdn_gpio))
|
|
gpiod_direction_output(ar2020->pwdn_gpio, 0);
|
|
|
|
clk_disable_unprepare(ar2020->xvclk);
|
|
|
|
if (!IS_ERR(ar2020->reset_gpio))
|
|
gpiod_direction_output(ar2020->reset_gpio, 0);
|
|
if (!IS_ERR_OR_NULL(ar2020->pins_sleep)) {
|
|
ret = pinctrl_select_state(ar2020->pinctrl,
|
|
ar2020->pins_sleep);
|
|
if (ret < 0)
|
|
dev_dbg(dev, "could not set pins\n");
|
|
}
|
|
|
|
if (ar2020->is_thunderboot_ng) {
|
|
ar2020->is_thunderboot_ng = false;
|
|
regulator_bulk_disable(AR2020_NUM_SUPPLIES, ar2020->supplies);
|
|
}
|
|
}
|
|
|
|
static int ar2020_runtime_resume(struct device *dev)
|
|
{
|
|
struct i2c_client *client = to_i2c_client(dev);
|
|
struct v4l2_subdev *sd = i2c_get_clientdata(client);
|
|
struct ar2020 *ar2020 = to_ar2020(sd);
|
|
|
|
return __ar2020_power_on(ar2020);
|
|
}
|
|
|
|
static int ar2020_runtime_suspend(struct device *dev)
|
|
{
|
|
struct i2c_client *client = to_i2c_client(dev);
|
|
struct v4l2_subdev *sd = i2c_get_clientdata(client);
|
|
struct ar2020 *ar2020 = to_ar2020(sd);
|
|
|
|
__ar2020_power_off(ar2020);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
|
|
static int ar2020_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
|
|
{
|
|
struct ar2020 *ar2020 = to_ar2020(sd);
|
|
struct v4l2_mbus_framefmt *try_fmt =
|
|
v4l2_subdev_get_try_format(sd, fh->pad, 0);
|
|
const struct ar2020_mode *def_mode = &supported_modes[0];
|
|
|
|
mutex_lock(&ar2020->mutex);
|
|
/* Initialize try_fmt */
|
|
try_fmt->width = def_mode->width;
|
|
try_fmt->height = def_mode->height;
|
|
try_fmt->code = def_mode->bus_fmt;
|
|
try_fmt->field = V4L2_FIELD_NONE;
|
|
|
|
mutex_unlock(&ar2020->mutex);
|
|
/* No crop or compose */
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static int ar2020_enum_frame_interval(struct v4l2_subdev *sd,
|
|
struct v4l2_subdev_pad_config *cfg,
|
|
struct v4l2_subdev_frame_interval_enum *fie)
|
|
{
|
|
struct ar2020 *ar2020 = to_ar2020(sd);
|
|
|
|
if (fie->index >= ar2020->cfg_num)
|
|
return -EINVAL;
|
|
|
|
fie->code = supported_modes[fie->index].bus_fmt;
|
|
fie->width = supported_modes[fie->index].width;
|
|
fie->height = supported_modes[fie->index].height;
|
|
fie->interval = supported_modes[fie->index].max_fps;
|
|
fie->reserved[0] = supported_modes[fie->index].hdr_mode;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops ar2020_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(ar2020_runtime_suspend,
|
|
ar2020_runtime_resume, NULL)
|
|
};
|
|
|
|
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
|
|
static const struct v4l2_subdev_internal_ops ar2020_internal_ops = {
|
|
.open = ar2020_open,
|
|
};
|
|
#endif
|
|
|
|
static const struct v4l2_subdev_core_ops ar2020_core_ops = {
|
|
.s_power = ar2020_s_power,
|
|
.ioctl = ar2020_ioctl,
|
|
#ifdef CONFIG_COMPAT
|
|
.compat_ioctl32 = ar2020_compat_ioctl32,
|
|
#endif
|
|
};
|
|
|
|
static const struct v4l2_subdev_video_ops ar2020_video_ops = {
|
|
.s_stream = ar2020_s_stream,
|
|
.g_frame_interval = ar2020_g_frame_interval,
|
|
};
|
|
|
|
static const struct v4l2_subdev_pad_ops ar2020_pad_ops = {
|
|
.enum_mbus_code = ar2020_enum_mbus_code,
|
|
.enum_frame_size = ar2020_enum_frame_sizes,
|
|
.enum_frame_interval = ar2020_enum_frame_interval,
|
|
.get_fmt = ar2020_get_fmt,
|
|
.set_fmt = ar2020_set_fmt,
|
|
.get_mbus_config = ar2020_g_mbus_config,
|
|
};
|
|
|
|
static const struct v4l2_subdev_ops ar2020_subdev_ops = {
|
|
.core = &ar2020_core_ops,
|
|
.video = &ar2020_video_ops,
|
|
.pad = &ar2020_pad_ops,
|
|
};
|
|
|
|
|
|
static int ar2020_set_ctrl(struct v4l2_ctrl *ctrl)
|
|
{
|
|
struct ar2020 *ar2020 = container_of(ctrl->handler,
|
|
struct ar2020, ctrl_handler);
|
|
struct i2c_client *client = ar2020->client;
|
|
s64 max;
|
|
int ret = 0;
|
|
u32 val = 0;
|
|
|
|
/* Propagate change of current control to all related controls */
|
|
switch (ctrl->id) {
|
|
case V4L2_CID_VBLANK:
|
|
/* Update max exposure while meeting expected vblanking */
|
|
max = ar2020->cur_mode->height + ctrl->val - 4;
|
|
__v4l2_ctrl_modify_range(ar2020->exposure,
|
|
ar2020->exposure->minimum, max,
|
|
ar2020->exposure->step,
|
|
ar2020->exposure->default_value);
|
|
break;
|
|
}
|
|
|
|
if (!pm_runtime_get_if_in_use(&client->dev))
|
|
return 0;
|
|
|
|
switch (ctrl->id) {
|
|
case V4L2_CID_EXPOSURE:
|
|
ret = ar2020_write_reg(ar2020->client,
|
|
AR2020_REG_EXP,
|
|
AR2020_REG_VALUE_16BIT,
|
|
ctrl->val);
|
|
dev_dbg(&client->dev, "set exposure 0x%x\n",
|
|
ctrl->val);
|
|
break;
|
|
case V4L2_CID_ANALOGUE_GAIN:
|
|
|
|
ret = ar2020_write_reg(ar2020->client,
|
|
AR2020_REG_GAIN,
|
|
AR2020_REG_VALUE_16BIT,
|
|
ctrl->val);
|
|
|
|
dev_dbg(&client->dev, "set analog gain 0x%x\n",
|
|
ctrl->val);
|
|
break;
|
|
case V4L2_CID_VBLANK:
|
|
ret = ar2020_write_reg(ar2020->client, AR2020_REG_VTS,
|
|
AR2020_REG_VALUE_16BIT,
|
|
ctrl->val + ar2020->cur_mode->height);
|
|
dev_dbg(&client->dev, "set vblank 0x%x\n",
|
|
ctrl->val);
|
|
break;
|
|
case V4L2_CID_TEST_PATTERN:
|
|
ret = ar2020_enable_test_pattern(ar2020, ctrl->val);
|
|
break;
|
|
case V4L2_CID_HFLIP:
|
|
ret = ar2020_read_reg(ar2020->client, AR2020_FLIP_REG,
|
|
AR2020_REG_VALUE_16BIT,
|
|
&val);
|
|
if (ctrl->val)
|
|
val |= MIRROR_BIT_MASK;
|
|
else
|
|
val &= ~MIRROR_BIT_MASK;
|
|
ret |= ar2020_write_reg(ar2020->client, AR2020_FLIP_REG,
|
|
AR2020_REG_VALUE_16BIT,
|
|
val);
|
|
if (ret == 0)
|
|
ar2020->flip = val;
|
|
break;
|
|
case V4L2_CID_VFLIP:
|
|
ret = ar2020_read_reg(ar2020->client, AR2020_FLIP_REG,
|
|
AR2020_REG_VALUE_16BIT,
|
|
&val);
|
|
if (ctrl->val)
|
|
val |= FLIP_BIT_MASK;
|
|
else
|
|
val &= ~FLIP_BIT_MASK;
|
|
ret |= ar2020_write_reg(ar2020->client, AR2020_FLIP_REG,
|
|
AR2020_REG_VALUE_16BIT,
|
|
val);
|
|
if (ret == 0)
|
|
ar2020->flip = val;
|
|
break;
|
|
default:
|
|
dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
|
|
__func__, ctrl->id, ctrl->val);
|
|
break;
|
|
}
|
|
|
|
pm_runtime_put(&client->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct v4l2_ctrl_ops ar2020_ctrl_ops = {
|
|
.s_ctrl = ar2020_set_ctrl,
|
|
};
|
|
|
|
static int ar2020_initialize_controls(struct ar2020 *ar2020)
|
|
{
|
|
const struct ar2020_mode *mode;
|
|
struct v4l2_ctrl_handler *handler;
|
|
s64 exposure_max, vblank_def;
|
|
u32 h_blank;
|
|
int ret;
|
|
u64 dst_link_freq = 0;
|
|
u64 dst_pixel_rate = 0;
|
|
|
|
handler = &ar2020->ctrl_handler;
|
|
mode = ar2020->cur_mode;
|
|
ret = v4l2_ctrl_handler_init(handler, 9);
|
|
if (ret)
|
|
return ret;
|
|
handler->lock = &ar2020->mutex;
|
|
|
|
ar2020->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
|
|
V4L2_CID_LINK_FREQ,
|
|
MIPI_FREQ_MAX_INDEX, 0, link_freq_menu_items);
|
|
|
|
dst_link_freq = mode->mipi_freq;
|
|
dst_pixel_rate = mode->mipi_rate;
|
|
/* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
|
|
ar2020->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
|
|
V4L2_CID_PIXEL_RATE,
|
|
0, PIXEL_RATE_MAX,
|
|
1, dst_pixel_rate);
|
|
|
|
__v4l2_ctrl_s_ctrl(ar2020->link_freq,
|
|
dst_link_freq);
|
|
|
|
h_blank = mode->hts_def - mode->width;
|
|
ar2020->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
|
|
h_blank, h_blank, 1, h_blank);
|
|
if (ar2020->hblank)
|
|
ar2020->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
|
|
|
|
vblank_def = mode->vts_def - mode->height;
|
|
ar2020->vblank = v4l2_ctrl_new_std(handler, &ar2020_ctrl_ops,
|
|
V4L2_CID_VBLANK, vblank_def,
|
|
AR2020_VTS_MAX - mode->height,
|
|
1, vblank_def);
|
|
|
|
exposure_max = mode->vts_def - 4;
|
|
ar2020->exposure = v4l2_ctrl_new_std(handler, &ar2020_ctrl_ops,
|
|
V4L2_CID_EXPOSURE, AR2020_EXPOSURE_MIN,
|
|
exposure_max, AR2020_EXPOSURE_STEP,
|
|
mode->exp_def);
|
|
|
|
ar2020->anal_gain = v4l2_ctrl_new_std(handler, &ar2020_ctrl_ops,
|
|
V4L2_CID_ANALOGUE_GAIN, AR2020_GAIN_MIN,
|
|
AR2020_GAIN_MAX, AR2020_GAIN_STEP,
|
|
AR2020_GAIN_DEFAULT);
|
|
|
|
ar2020->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
|
|
&ar2020_ctrl_ops, V4L2_CID_TEST_PATTERN,
|
|
ARRAY_SIZE(ar2020_test_pattern_menu) - 1,
|
|
0, 0, ar2020_test_pattern_menu);
|
|
|
|
ar2020->h_flip = v4l2_ctrl_new_std(handler, &ar2020_ctrl_ops,
|
|
V4L2_CID_HFLIP, 0, 1, 1, 0);
|
|
|
|
ar2020->v_flip = v4l2_ctrl_new_std(handler, &ar2020_ctrl_ops,
|
|
V4L2_CID_VFLIP, 0, 1, 1, 0);
|
|
ar2020->flip = 0;
|
|
if (handler->error) {
|
|
ret = handler->error;
|
|
dev_err(&ar2020->client->dev,
|
|
"Failed to init controls(%d)\n", ret);
|
|
goto err_free_handler;
|
|
}
|
|
|
|
ar2020->subdev.ctrl_handler = handler;
|
|
ar2020->has_init_exp = false;
|
|
ar2020->long_hcg = false;
|
|
ar2020->middle_hcg = false;
|
|
ar2020->short_hcg = false;
|
|
|
|
return 0;
|
|
|
|
err_free_handler:
|
|
v4l2_ctrl_handler_free(handler);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ar2020_check_sensor_id(struct ar2020 *ar2020,
|
|
struct i2c_client *client)
|
|
{
|
|
struct device *dev = &ar2020->client->dev;
|
|
u32 id = 0;
|
|
int ret;
|
|
|
|
if (ar2020->is_thunderboot) {
|
|
dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
|
|
return 0;
|
|
}
|
|
|
|
ret = ar2020_read_reg(client, AR2020_REG_CHIP_ID,
|
|
AR2020_REG_VALUE_16BIT, &id);
|
|
if (id != CHIP_ID) {
|
|
dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
|
|
return -ENODEV;
|
|
}
|
|
|
|
dev_info(dev, "Detected ar2020-%04x sensor\n", CHIP_ID);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ar2020_configure_regulators(struct ar2020 *ar2020)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < AR2020_NUM_SUPPLIES; i++)
|
|
ar2020->supplies[i].supply = ar2020_supply_names[i];
|
|
|
|
return devm_regulator_bulk_get(&ar2020->client->dev,
|
|
AR2020_NUM_SUPPLIES,
|
|
ar2020->supplies);
|
|
}
|
|
|
|
static int ar2020_probe(struct i2c_client *client,
|
|
const struct i2c_device_id *id)
|
|
{
|
|
struct device *dev = &client->dev;
|
|
struct device_node *node = dev->of_node;
|
|
struct ar2020 *ar2020;
|
|
struct v4l2_subdev *sd;
|
|
char facing[2];
|
|
int ret;
|
|
u32 i, hdr_mode = 0;
|
|
|
|
dev_dbg(dev, "driver version: %02x.%02x.%02x",
|
|
DRIVER_VERSION >> 16,
|
|
(DRIVER_VERSION & 0xff00) >> 8,
|
|
DRIVER_VERSION & 0x00ff);
|
|
|
|
ar2020 = devm_kzalloc(dev, sizeof(*ar2020), GFP_KERNEL);
|
|
if (!ar2020)
|
|
return -ENOMEM;
|
|
|
|
ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
|
|
&ar2020->module_index);
|
|
ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
|
|
&ar2020->module_facing);
|
|
ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
|
|
&ar2020->module_name);
|
|
ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
|
|
&ar2020->len_name);
|
|
if (ret) {
|
|
dev_err(dev, "could not get module information!\n");
|
|
return -EINVAL;
|
|
}
|
|
#if USE_8LANE
|
|
/*dual mipi settings, should move to dts in future*/
|
|
ar2020->csi_lanes_in_use = LANE_NUM_8;
|
|
ar2020->multi_dev_info.dev_idx[0] = 0;//0;
|
|
ar2020->multi_dev_info.dev_idx[1] = 1;//device num, dcphy0->0, dcphy1->1,csi0->2,csi1->4;
|
|
ar2020->multi_dev_info.combine_idx[0] = 1;//main dev,default right sight image
|
|
ar2020->multi_dev_info.pixel_offset = 24;//the overlapped pixel number of L&R frame.
|
|
ar2020->multi_dev_info.dev_num = 2;//two mipi dev, each 4 lanes;
|
|
/*dual mipi setting over*/
|
|
#endif
|
|
ar2020->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
|
|
ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
|
|
&hdr_mode);
|
|
if (ret) {
|
|
hdr_mode = NO_HDR;
|
|
dev_warn(dev, " Get hdr mode failed! no hdr default\n");
|
|
}
|
|
ar2020->cfg_num = ARRAY_SIZE(supported_modes);
|
|
if (ar2020->cfg_num == 0) {
|
|
dev_err(dev, "no any supported mode providec, force exit probe!\n");
|
|
return -EINVAL;
|
|
}
|
|
ar2020->cur_mode = &supported_modes[0];//initialize.
|
|
for (i = 0; i < ar2020->cfg_num; i++) {
|
|
if (hdr_mode == supported_modes[i].hdr_mode) {
|
|
ar2020->cur_mode = &supported_modes[i];
|
|
break;
|
|
}
|
|
}
|
|
ar2020->client = client;
|
|
|
|
ar2020->xvclk = devm_clk_get(dev, "xvclk");
|
|
if (IS_ERR(ar2020->xvclk)) {
|
|
dev_err(dev, "Failed to get xvclk\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ar2020->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
|
|
if (IS_ERR(ar2020->pwdn_gpio))
|
|
dev_warn(dev, "Failed to get pwdn-gpios\n");
|
|
|
|
ar2020->pinctrl = devm_pinctrl_get(dev);
|
|
if (!IS_ERR(ar2020->pinctrl)) {
|
|
ar2020->pins_default =
|
|
pinctrl_lookup_state(ar2020->pinctrl,
|
|
OF_CAMERA_PINCTRL_STATE_DEFAULT);
|
|
if (IS_ERR(ar2020->pins_default))
|
|
dev_err(dev, "could not get default pinstate\n");
|
|
|
|
ar2020->pins_sleep =
|
|
pinctrl_lookup_state(ar2020->pinctrl,
|
|
OF_CAMERA_PINCTRL_STATE_SLEEP);
|
|
if (IS_ERR(ar2020->pins_sleep))
|
|
dev_err(dev, "could not get sleep pinstate\n");
|
|
} else {
|
|
dev_err(dev, "no pinctrl\n");
|
|
}
|
|
|
|
ret = ar2020_configure_regulators(ar2020);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to get power regulators\n");
|
|
return ret;
|
|
}
|
|
|
|
mutex_init(&ar2020->mutex);
|
|
|
|
sd = &ar2020->subdev;
|
|
v4l2_i2c_subdev_init(sd, client, &ar2020_subdev_ops);
|
|
ret = ar2020_initialize_controls(ar2020);
|
|
if (ret)
|
|
goto err_destroy_mutex;
|
|
|
|
ret = __ar2020_power_on(ar2020);
|
|
if (ret)
|
|
goto err_free_handler;
|
|
|
|
ret = ar2020_check_sensor_id(ar2020, client);
|
|
if (ret)
|
|
goto err_power_off;
|
|
|
|
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
|
|
sd->internal_ops = &ar2020_internal_ops;
|
|
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
|
|
#endif
|
|
#if defined(CONFIG_MEDIA_CONTROLLER)
|
|
ar2020->pad.flags = MEDIA_PAD_FL_SOURCE;
|
|
sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
|
|
ret = media_entity_pads_init(&sd->entity, 1, &ar2020->pad);
|
|
if (ret < 0)
|
|
goto err_power_off;
|
|
#endif
|
|
|
|
memset(facing, 0, sizeof(facing));
|
|
if (strcmp(ar2020->module_facing, "back") == 0)
|
|
facing[0] = 'b';
|
|
else
|
|
facing[0] = 'f';
|
|
|
|
snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
|
|
ar2020->module_index, facing,
|
|
AR2020_NAME, dev_name(sd->dev));
|
|
ret = v4l2_async_register_subdev_sensor_common(sd);
|
|
if (ret) {
|
|
dev_err(dev, "v4l2 async register subdev failed\n");
|
|
goto err_clean_entity;
|
|
}
|
|
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_enable(dev);
|
|
pm_runtime_idle(dev);
|
|
|
|
return 0;
|
|
|
|
err_clean_entity:
|
|
#if defined(CONFIG_MEDIA_CONTROLLER)
|
|
media_entity_cleanup(&sd->entity);
|
|
#endif
|
|
err_power_off:
|
|
__ar2020_power_off(ar2020);
|
|
err_free_handler:
|
|
v4l2_ctrl_handler_free(&ar2020->ctrl_handler);
|
|
err_destroy_mutex:
|
|
mutex_destroy(&ar2020->mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ar2020_remove(struct i2c_client *client)
|
|
{
|
|
struct v4l2_subdev *sd = i2c_get_clientdata(client);
|
|
struct ar2020 *ar2020 = to_ar2020(sd);
|
|
|
|
v4l2_async_unregister_subdev(sd);
|
|
#if defined(CONFIG_MEDIA_CONTROLLER)
|
|
media_entity_cleanup(&sd->entity);
|
|
#endif
|
|
v4l2_ctrl_handler_free(&ar2020->ctrl_handler);
|
|
mutex_destroy(&ar2020->mutex);
|
|
|
|
pm_runtime_disable(&client->dev);
|
|
if (!pm_runtime_status_suspended(&client->dev))
|
|
__ar2020_power_off(ar2020);
|
|
pm_runtime_set_suspended(&client->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if IS_ENABLED(CONFIG_OF)
|
|
static const struct of_device_id ar2020_of_match[] = {
|
|
{ .compatible = "onsemi,ar2020" },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ar2020_of_match);
|
|
#endif
|
|
|
|
static const struct i2c_device_id ar2020_match_id[] = {
|
|
{ "onsemi,ar2020", 0 },
|
|
{ },
|
|
};
|
|
|
|
static struct i2c_driver ar2020_i2c_driver = {
|
|
.driver = {
|
|
.name = AR2020_NAME,
|
|
.pm = &ar2020_pm_ops,
|
|
.of_match_table = of_match_ptr(ar2020_of_match),
|
|
},
|
|
.probe = &ar2020_probe,
|
|
.remove = &ar2020_remove,
|
|
.id_table = ar2020_match_id,
|
|
};
|
|
|
|
#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
|
|
module_i2c_driver(ar2020_i2c_driver);
|
|
#else
|
|
static int __init sensor_mod_init(void)
|
|
{
|
|
return i2c_add_driver(&ar2020_i2c_driver);
|
|
}
|
|
|
|
static void __exit sensor_mod_exit(void)
|
|
{
|
|
i2c_del_driver(&ar2020_i2c_driver);
|
|
}
|
|
|
|
device_initcall_sync(sensor_mod_init);
|
|
module_exit(sensor_mod_exit);
|
|
#endif
|
|
|
|
MODULE_DESCRIPTION("Onsemi ar2020 sensor driver");
|
|
MODULE_LICENSE("GPL");
|