271 lines
7.1 KiB
C
Executable File
271 lines
7.1 KiB
C
Executable File
/*
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* Copyright (C) 2010-2017 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained from Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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/**
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* @file mali_pmu.c
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* Mali driver functions for Mali 400 PMU hardware
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*/
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#include "mali_hw_core.h"
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#include "mali_pmu.h"
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#include "mali_pp.h"
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#include "mali_kernel_common.h"
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#include "mali_osk.h"
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#include "mali_pm.h"
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#include "mali_osk_mali.h"
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struct mali_pmu_core *mali_global_pmu_core = NULL;
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static _mali_osk_errcode_t mali_pmu_wait_for_command_finish(
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struct mali_pmu_core *pmu);
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struct mali_pmu_core *mali_pmu_create(_mali_osk_resource_t *resource)
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{
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struct mali_pmu_core *pmu;
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MALI_DEBUG_ASSERT(NULL == mali_global_pmu_core);
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MALI_DEBUG_PRINT(2, ("Mali PMU: Creating Mali PMU core\n"));
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pmu = (struct mali_pmu_core *)_mali_osk_malloc(
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sizeof(struct mali_pmu_core));
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if (NULL != pmu) {
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pmu->registered_cores_mask = 0; /* to be set later */
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if (_MALI_OSK_ERR_OK == mali_hw_core_create(&pmu->hw_core,
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resource, PMU_REGISTER_ADDRESS_SPACE_SIZE)) {
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pmu->switch_delay = _mali_osk_get_pmu_switch_delay();
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mali_global_pmu_core = pmu;
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return pmu;
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}
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_mali_osk_free(pmu);
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}
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return NULL;
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}
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void mali_pmu_delete(struct mali_pmu_core *pmu)
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{
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MALI_DEBUG_ASSERT_POINTER(pmu);
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MALI_DEBUG_ASSERT(pmu == mali_global_pmu_core);
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MALI_DEBUG_PRINT(2, ("Mali PMU: Deleting Mali PMU core\n"));
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mali_global_pmu_core = NULL;
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mali_hw_core_delete(&pmu->hw_core);
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_mali_osk_free(pmu);
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}
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void mali_pmu_set_registered_cores_mask(struct mali_pmu_core *pmu, u32 mask)
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{
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pmu->registered_cores_mask = mask;
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}
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void mali_pmu_reset(struct mali_pmu_core *pmu)
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{
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MALI_DEBUG_ASSERT_POINTER(pmu);
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MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0);
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/* Setup the desired defaults */
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mali_hw_core_register_write_relaxed(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_INT_MASK, 0);
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mali_hw_core_register_write_relaxed(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_SW_DELAY, pmu->switch_delay);
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}
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void mali_pmu_power_up_all(struct mali_pmu_core *pmu)
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{
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u32 stat;
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MALI_DEBUG_ASSERT_POINTER(pmu);
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MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0);
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mali_pm_exec_lock();
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mali_pmu_reset(pmu);
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/* Now simply power up the domains which are marked as powered down */
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stat = mali_hw_core_register_read(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_STATUS);
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mali_pmu_power_up(pmu, stat);
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mali_pm_exec_unlock();
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}
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void mali_pmu_power_down_all(struct mali_pmu_core *pmu)
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{
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u32 stat;
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MALI_DEBUG_ASSERT_POINTER(pmu);
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MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0);
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mali_pm_exec_lock();
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/* Now simply power down the domains which are marked as powered up */
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stat = mali_hw_core_register_read(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_STATUS);
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mali_pmu_power_down(pmu, (~stat) & pmu->registered_cores_mask);
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mali_pm_exec_unlock();
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}
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_mali_osk_errcode_t mali_pmu_power_down(struct mali_pmu_core *pmu, u32 mask)
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{
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u32 stat;
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_mali_osk_errcode_t err;
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MALI_DEBUG_ASSERT_POINTER(pmu);
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MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0);
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MALI_DEBUG_ASSERT(mask <= pmu->registered_cores_mask);
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MALI_DEBUG_ASSERT(0 == (mali_hw_core_register_read(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_INT_RAWSTAT) &
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PMU_REG_VAL_IRQ));
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MALI_DEBUG_PRINT(3,
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("PMU power down: ...................... [%s]\n",
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mali_pm_mask_to_string(mask)));
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stat = mali_hw_core_register_read(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_STATUS);
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/*
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* Assert that we are not powering down domains which are already
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* powered down.
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*/
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MALI_DEBUG_ASSERT(0 == (stat & mask));
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mask &= ~(0x1 << MALI_DOMAIN_INDEX_DUMMY);
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if (0 == mask || 0 == ((~stat) & mask)) return _MALI_OSK_ERR_OK;
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mali_hw_core_register_write(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_POWER_DOWN, mask);
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/*
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* Do not wait for interrupt on Mali-300/400 if all domains are
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* powered off by our power down command, because the HW will simply
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* not generate an interrupt in this case.
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*/
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if (mali_is_mali450() || mali_is_mali470() || pmu->registered_cores_mask != (mask | stat)) {
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err = mali_pmu_wait_for_command_finish(pmu);
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if (_MALI_OSK_ERR_OK != err) {
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return err;
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}
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} else {
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mali_hw_core_register_write(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_INT_CLEAR, PMU_REG_VAL_IRQ);
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}
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#if defined(DEBUG)
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/* Verify power status of domains after power down */
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stat = mali_hw_core_register_read(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_STATUS);
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MALI_DEBUG_ASSERT(mask == (stat & mask));
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#endif
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return _MALI_OSK_ERR_OK;
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}
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_mali_osk_errcode_t mali_pmu_power_up(struct mali_pmu_core *pmu, u32 mask)
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{
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u32 stat;
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_mali_osk_errcode_t err;
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#if !defined(CONFIG_MALI_PMU_PARALLEL_POWER_UP)
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u32 current_domain;
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#endif
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MALI_DEBUG_ASSERT_POINTER(pmu);
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MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0);
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MALI_DEBUG_ASSERT(mask <= pmu->registered_cores_mask);
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MALI_DEBUG_ASSERT(0 == (mali_hw_core_register_read(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_INT_RAWSTAT) &
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PMU_REG_VAL_IRQ));
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MALI_DEBUG_PRINT(3,
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("PMU power up: ........................ [%s]\n",
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mali_pm_mask_to_string(mask)));
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stat = mali_hw_core_register_read(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_STATUS);
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stat &= pmu->registered_cores_mask;
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mask &= ~(0x1 << MALI_DOMAIN_INDEX_DUMMY);
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if (0 == mask || 0 == (stat & mask)) return _MALI_OSK_ERR_OK;
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/*
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* Assert that we are only powering up domains which are currently
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* powered down.
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*/
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MALI_DEBUG_ASSERT(mask == (stat & mask));
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#if defined(CONFIG_MALI_PMU_PARALLEL_POWER_UP)
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mali_hw_core_register_write(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_POWER_UP, mask);
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err = mali_pmu_wait_for_command_finish(pmu);
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if (_MALI_OSK_ERR_OK != err) {
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return err;
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}
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#else
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for (current_domain = 1;
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current_domain <= pmu->registered_cores_mask;
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current_domain <<= 1) {
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if (current_domain & mask & stat) {
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mali_hw_core_register_write(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_POWER_UP,
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current_domain);
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err = mali_pmu_wait_for_command_finish(pmu);
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if (_MALI_OSK_ERR_OK != err) {
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return err;
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}
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}
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}
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#endif
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#if defined(DEBUG)
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/* Verify power status of domains after power up */
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stat = mali_hw_core_register_read(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_STATUS);
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MALI_DEBUG_ASSERT(0 == (stat & mask));
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#endif /* defined(DEBUG) */
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return _MALI_OSK_ERR_OK;
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}
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static _mali_osk_errcode_t mali_pmu_wait_for_command_finish(
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struct mali_pmu_core *pmu)
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{
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u32 rawstat;
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u32 timeout = MALI_REG_POLL_COUNT_SLOW;
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MALI_DEBUG_ASSERT(pmu);
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/* Wait for the command to complete */
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do {
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rawstat = mali_hw_core_register_read(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_INT_RAWSTAT);
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--timeout;
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} while (0 == (rawstat & PMU_REG_VAL_IRQ) && 0 < timeout);
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MALI_DEBUG_ASSERT(0 < timeout);
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if (0 == timeout) {
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return _MALI_OSK_ERR_TIMEOUT;
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}
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mali_hw_core_register_write(&pmu->hw_core,
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PMU_REG_ADDR_MGMT_INT_CLEAR, PMU_REG_VAL_IRQ);
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return _MALI_OSK_ERR_OK;
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}
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