673 lines
17 KiB
C
673 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2010-2024 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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/*
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* Base kernel device APIs
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*/
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#include <linux/debugfs.h>
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#include <linux/dma-mapping.h>
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#include <linux/seq_file.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/types.h>
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#include <linux/oom.h>
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#include <mali_kbase.h>
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#include <mali_kbase_defs.h>
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#include <mali_kbase_hwaccess_instr.h>
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#include <mali_kbase_hwaccess_time.h>
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#include <mali_kbase_hw.h>
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#include <mali_kbase_config_defaults.h>
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#include <linux/priority_control_manager.h>
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#include <tl/mali_kbase_timeline.h>
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#include "mali_kbase_kinstr_prfcnt.h"
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#include "hwcnt/mali_kbase_hwcnt_context.h"
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#include "hwcnt/mali_kbase_hwcnt_virtualizer.h"
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#include "mali_kbase_device.h"
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#include "mali_kbase_device_internal.h"
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#include "backend/gpu/mali_kbase_pm_internal.h"
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#include "backend/gpu/mali_kbase_irq_internal.h"
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#include "mali_kbase_regs_history_debugfs.h"
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#include "mali_kbase_pbha.h"
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#include "arbiter/mali_kbase_arbiter_pm.h"
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#if defined(CONFIG_DEBUG_FS) && !IS_ENABLED(CONFIG_MALI_BIFROST_NO_MALI)
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/* Number of register accesses for the buffer that we allocate during
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* initialization time. The buffer size can be changed later via debugfs.
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*/
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#define KBASEP_DEFAULT_REGISTER_HISTORY_SIZE ((u16)512)
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#endif /* defined(CONFIG_DEBUG_FS) && !IS_ENABLED(CONFIG_MALI_BIFROST_NO_MALI) */
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static DEFINE_MUTEX(kbase_dev_list_lock);
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static LIST_HEAD(kbase_dev_list);
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static unsigned int kbase_dev_nr;
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static unsigned int mma_wa_id;
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static int set_mma_wa_id(const char *val, const struct kernel_param *kp)
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{
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return kbase_param_set_uint_minmax(val, kp, 1, 15);
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}
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static const struct kernel_param_ops mma_wa_id_ops = {
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.set = set_mma_wa_id,
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.get = param_get_uint,
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};
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module_param_cb(mma_wa_id, &mma_wa_id_ops, &mma_wa_id, 0444);
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__MODULE_PARM_TYPE(mma_wa_id, "uint");
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MODULE_PARM_DESC(mma_wa_id, "PBHA ID for MMA workaround. Valid range is from 1 to 15.");
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struct kbase_device *kbase_device_alloc(void)
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{
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return vzalloc(sizeof(struct kbase_device));
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}
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/**
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* kbase_device_all_as_init() - Initialise address space objects of the device.
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*
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* @kbdev: Pointer to kbase device.
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*
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* Return: 0 on success otherwise non-zero.
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*/
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static int kbase_device_all_as_init(struct kbase_device *kbdev)
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{
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unsigned int i;
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int err = 0;
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for (i = 0; i < (unsigned int)kbdev->nr_hw_address_spaces; i++) {
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err = kbase_mmu_as_init(kbdev, i);
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if (err)
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break;
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}
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if (err) {
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while (i-- > 0)
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kbase_mmu_as_term(kbdev, i);
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}
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return err;
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}
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static void kbase_device_all_as_term(struct kbase_device *kbdev)
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{
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unsigned int i;
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for (i = 0; i < (unsigned int)kbdev->nr_hw_address_spaces; i++)
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kbase_mmu_as_term(kbdev, i);
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}
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static int pcm_prioritized_process_cb(struct notifier_block *nb, unsigned long action, void *data)
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{
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#if MALI_USE_CSF
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struct kbase_device *const kbdev =
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container_of(nb, struct kbase_device, pcm_prioritized_process_nb);
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struct pcm_prioritized_process_notifier_data *const notifier_data = data;
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int ret = -EINVAL;
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switch (action) {
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case ADD_PRIORITIZED_PROCESS:
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if (kbasep_adjust_prioritized_process(kbdev, true, notifier_data->pid))
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ret = 0;
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break;
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case REMOVE_PRIORITIZED_PROCESS:
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if (kbasep_adjust_prioritized_process(kbdev, false, notifier_data->pid))
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ret = 0;
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break;
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}
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return ret;
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#endif /* MALI_USE_CSF */
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return 0;
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}
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int kbase_device_pcm_dev_init(struct kbase_device *const kbdev)
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{
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int err = 0;
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#if IS_ENABLED(CONFIG_OF)
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struct device_node *prio_ctrl_node;
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/* Check to see whether or not a platform specific priority control manager
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* is available.
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*/
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prio_ctrl_node = of_parse_phandle(kbdev->dev->of_node, "priority-control-manager", 0);
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if (!prio_ctrl_node) {
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dev_info(kbdev->dev, "No priority control manager is configured");
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} else {
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struct platform_device *const pdev = of_find_device_by_node(prio_ctrl_node);
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if (!pdev) {
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dev_err(kbdev->dev,
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"The configured priority control manager was not found");
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} else {
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struct priority_control_manager_device *pcm_dev =
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platform_get_drvdata(pdev);
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if (!pcm_dev) {
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dev_info(kbdev->dev, "Priority control manager is not ready");
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err = -EPROBE_DEFER;
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} else if (!try_module_get(pcm_dev->owner)) {
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dev_err(kbdev->dev,
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"Failed to get priority control manager module");
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err = -ENODEV;
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} else {
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dev_info(kbdev->dev,
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"Priority control manager successfully loaded");
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kbdev->pcm_dev = pcm_dev;
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kbdev->pcm_prioritized_process_nb = (struct notifier_block){
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.notifier_call = &pcm_prioritized_process_cb,
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};
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if (pcm_dev->ops.pcm_prioritized_process_notifier_register !=
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NULL) {
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if (pcm_dev->ops.pcm_prioritized_process_notifier_register(
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pcm_dev, &kbdev->pcm_prioritized_process_nb))
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dev_warn(
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kbdev->dev,
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"Failed to register for changes in prioritized processes");
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}
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}
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}
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of_node_put(prio_ctrl_node);
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}
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#endif /* CONFIG_OF */
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return err;
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}
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void kbase_device_pcm_dev_term(struct kbase_device *const kbdev)
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{
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struct priority_control_manager_device *const pcm_dev = kbdev->pcm_dev;
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if (pcm_dev) {
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if (pcm_dev->ops.pcm_prioritized_process_notifier_unregister != NULL)
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pcm_dev->ops.pcm_prioritized_process_notifier_unregister(
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pcm_dev, &kbdev->pcm_prioritized_process_nb);
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module_put(pcm_dev->owner);
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}
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}
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#define KBASE_PAGES_TO_KIB(pages) (((unsigned int)pages) << (PAGE_SHIFT - 10))
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/**
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* mali_oom_notifier_handler - Mali driver out-of-memory handler
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*
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* @nb: notifier block - used to retrieve kbdev pointer
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* @action: action (unused)
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* @data: data pointer (unused)
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*
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* This function simply lists memory usage by the Mali driver, per GPU device,
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* for diagnostic purposes.
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*
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* Return: NOTIFY_OK on success, NOTIFY_BAD otherwise.
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*/
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static int mali_oom_notifier_handler(struct notifier_block *nb, unsigned long action, void *data)
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{
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struct kbase_device *kbdev;
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struct kbase_context *kctx = NULL;
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unsigned long kbdev_alloc_total;
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CSTD_UNUSED(action);
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CSTD_UNUSED(data);
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if (WARN_ON(nb == NULL))
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return NOTIFY_BAD;
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kbdev = container_of(nb, struct kbase_device, oom_notifier_block);
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kbdev_alloc_total = KBASE_PAGES_TO_KIB(atomic_read(&(kbdev->memdev.used_pages)));
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dev_err(kbdev->dev, "OOM notifier: dev %s %lu kB\n", kbdev->devname, kbdev_alloc_total);
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mutex_lock(&kbdev->kctx_list_lock);
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list_for_each_entry(kctx, &kbdev->kctx_list, kctx_list_link) {
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struct task_struct *task = kctx->task;
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struct pid *tgid_struct;
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struct task_struct *tgid_task;
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unsigned long task_alloc_total =
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KBASE_PAGES_TO_KIB(atomic_read(&(kctx->used_pages)));
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rcu_read_lock();
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tgid_struct = find_get_pid(kctx->tgid);
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tgid_task = pid_task(tgid_struct, PIDTYPE_PID);
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dev_err(kbdev->dev,
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"OOM notifier: tsk %s:%s tgid (%u) pid (%u) %lu kB\n",
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tgid_task ? tgid_task->comm : "[null task]",
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task ? task->comm : "[null task]",
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kctx->tgid,
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kctx->pid,
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task_alloc_total);
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put_pid(tgid_struct);
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rcu_read_unlock();
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}
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mutex_unlock(&kbdev->kctx_list_lock);
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return NOTIFY_OK;
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}
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int kbase_device_misc_init(struct kbase_device *const kbdev)
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{
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int err;
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#if IS_ENABLED(CONFIG_ARM64)
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struct device_node *np = NULL;
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#endif /* CONFIG_ARM64 */
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spin_lock_init(&kbdev->mmu_mask_change);
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mutex_init(&kbdev->mmu_hw_mutex);
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#if IS_ENABLED(CONFIG_ARM64)
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np = kbdev->dev->of_node;
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if (np != NULL) {
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/* Read "-" versions of the properties and fallback to "_"
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* if these are not found
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*/
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if (of_property_read_u32(np, "snoop-enable-smc", &kbdev->snoop_enable_smc) &&
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of_property_read_u32(np, "snoop_enable_smc", &kbdev->snoop_enable_smc))
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kbdev->snoop_enable_smc = 0;
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if (of_property_read_u32(np, "snoop-disable-smc", &kbdev->snoop_disable_smc) &&
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of_property_read_u32(np, "snoop_disable_smc", &kbdev->snoop_disable_smc))
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kbdev->snoop_disable_smc = 0;
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/* Either both or none of the calls should be provided. */
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if (!((kbdev->snoop_disable_smc == 0 && kbdev->snoop_enable_smc == 0) ||
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(kbdev->snoop_disable_smc != 0 && kbdev->snoop_enable_smc != 0))) {
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WARN_ON(1);
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return -EINVAL;
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}
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}
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#endif /* CONFIG_ARM64 */
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/* Workaround a pre-3.13 Linux issue, where dma_mask is NULL when our
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* device structure was created by device-tree
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*/
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if (!kbdev->dev->dma_mask)
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kbdev->dev->dma_mask = &kbdev->dev->coherent_dma_mask;
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err = dma_set_mask(kbdev->dev, DMA_BIT_MASK(kbdev->gpu_props.mmu.pa_bits));
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if (err)
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goto dma_set_mask_failed;
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err = dma_set_coherent_mask(kbdev->dev, DMA_BIT_MASK(kbdev->gpu_props.mmu.pa_bits));
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if (err)
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goto dma_set_mask_failed;
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/* There is no limit for Mali, so set to max. */
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if (kbdev->dev->dma_parms)
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err = dma_set_max_seg_size(kbdev->dev, UINT_MAX);
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if (err)
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goto dma_set_mask_failed;
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kbdev->nr_hw_address_spaces = (s8)kbdev->gpu_props.num_address_spaces;
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err = kbase_device_all_as_init(kbdev);
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if (err)
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goto dma_set_mask_failed;
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/* Set mma_wa_id if it has been passed in as a module parameter */
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if ((kbdev->gpu_props.gpu_id.arch_id >= GPU_ID_ARCH_MAKE(14, 8, 0)) && mma_wa_id != 0)
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kbdev->mma_wa_id = mma_wa_id;
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err = kbase_pbha_read_dtb(kbdev);
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if (err)
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goto term_as;
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init_waitqueue_head(&kbdev->cache_clean_wait);
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kbase_debug_assert_register_hook(&kbase_ktrace_hook_wrapper, kbdev);
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kbdev->pm.dvfs_period = DEFAULT_PM_DVFS_PERIOD;
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#if MALI_USE_CSF
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kbdev->reset_timeout_ms = kbase_get_timeout_ms(kbdev, CSF_GPU_RESET_TIMEOUT);
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#else /* MALI_USE_CSF */
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kbdev->reset_timeout_ms = JM_DEFAULT_RESET_TIMEOUT_MS;
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#endif /* !MALI_USE_CSF */
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kbdev->mmu_mode = kbase_mmu_mode_get_aarch64();
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mutex_init(&kbdev->kctx_list_lock);
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INIT_LIST_HEAD(&kbdev->kctx_list);
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dev_dbg(kbdev->dev, "Registering mali_oom_notifier_handlern");
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kbdev->oom_notifier_block.notifier_call = mali_oom_notifier_handler;
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err = register_oom_notifier(&kbdev->oom_notifier_block);
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if (err) {
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dev_err(kbdev->dev,
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"Unable to register OOM notifier for Mali - but will continue\n");
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kbdev->oom_notifier_block.notifier_call = NULL;
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}
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#if !MALI_USE_CSF
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spin_lock_init(&kbdev->quick_reset_lock);
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kbdev->quick_reset_enabled = true;
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kbdev->num_of_atoms_hw_completed = 0;
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#endif
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#if MALI_USE_CSF
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atomic_set(&kbdev->fence_signal_timeout_enabled, 1);
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#endif
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return 0;
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term_as:
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kbase_device_all_as_term(kbdev);
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dma_set_mask_failed:
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return err;
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}
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void kbase_device_misc_term(struct kbase_device *kbdev)
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{
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KBASE_DEBUG_ASSERT(kbdev);
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WARN_ON(!list_empty(&kbdev->kctx_list));
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#if KBASE_KTRACE_ENABLE
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kbase_debug_assert_register_hook(NULL, NULL);
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#endif
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kbase_device_all_as_term(kbdev);
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if (kbdev->oom_notifier_block.notifier_call)
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unregister_oom_notifier(&kbdev->oom_notifier_block);
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#if MALI_USE_CSF && IS_ENABLED(CONFIG_SYNC_FILE)
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if (atomic_read(&kbdev->live_fence_metadata) > 0)
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dev_warn(kbdev->dev, "Terminating Kbase device with live fence metadata!");
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#endif
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}
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#if !MALI_USE_CSF
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void kbase_enable_quick_reset(struct kbase_device *kbdev)
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{
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unsigned long flags;
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spin_lock_irqsave(&kbdev->quick_reset_lock, flags);
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kbdev->quick_reset_enabled = true;
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kbdev->num_of_atoms_hw_completed = 0;
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spin_unlock_irqrestore(&kbdev->quick_reset_lock, flags);
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}
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void kbase_disable_quick_reset(struct kbase_device *kbdev)
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{
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unsigned long flags;
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spin_lock_irqsave(&kbdev->quick_reset_lock, flags);
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kbdev->quick_reset_enabled = false;
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kbdev->num_of_atoms_hw_completed = 0;
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spin_unlock_irqrestore(&kbdev->quick_reset_lock, flags);
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}
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bool kbase_is_quick_reset_enabled(struct kbase_device *kbdev)
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{
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return kbdev->quick_reset_enabled;
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}
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#endif
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void kbase_device_free(struct kbase_device *kbdev)
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{
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vfree(kbdev);
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}
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void kbase_device_id_init(struct kbase_device *kbdev)
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{
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scnprintf(kbdev->devname, DEVNAME_SIZE, "%s%d", KBASE_DRV_NAME, kbase_dev_nr);
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kbdev->id = kbase_dev_nr;
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}
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void kbase_increment_device_id(void)
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{
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kbase_dev_nr++;
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}
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int kbase_device_hwcnt_context_init(struct kbase_device *kbdev)
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{
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return kbase_hwcnt_context_init(&kbdev->hwcnt_gpu_iface, &kbdev->hwcnt_gpu_ctx);
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}
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void kbase_device_hwcnt_context_term(struct kbase_device *kbdev)
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{
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kbase_hwcnt_context_term(kbdev->hwcnt_gpu_ctx);
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}
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int kbase_device_hwcnt_virtualizer_init(struct kbase_device *kbdev)
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{
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return kbase_hwcnt_virtualizer_init(kbdev->hwcnt_gpu_ctx,
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KBASE_HWCNT_GPU_VIRTUALIZER_DUMP_THRESHOLD_NS,
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&kbdev->hwcnt_gpu_virt);
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}
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void kbase_device_hwcnt_virtualizer_term(struct kbase_device *kbdev)
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{
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kbase_hwcnt_virtualizer_term(kbdev->hwcnt_gpu_virt);
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}
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int kbase_device_timeline_init(struct kbase_device *kbdev)
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{
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return kbase_timeline_init(&kbdev->timeline, &kbdev->timeline_flags);
|
|
}
|
|
|
|
void kbase_device_timeline_term(struct kbase_device *kbdev)
|
|
{
|
|
kbase_timeline_term(kbdev->timeline);
|
|
}
|
|
|
|
int kbase_device_kinstr_prfcnt_init(struct kbase_device *kbdev)
|
|
{
|
|
return kbase_kinstr_prfcnt_init(kbdev->hwcnt_gpu_virt, &kbdev->kinstr_prfcnt_ctx);
|
|
}
|
|
|
|
void kbase_device_kinstr_prfcnt_term(struct kbase_device *kbdev)
|
|
{
|
|
kbase_kinstr_prfcnt_term(kbdev->kinstr_prfcnt_ctx);
|
|
}
|
|
|
|
int kbase_device_io_history_init(struct kbase_device *kbdev)
|
|
{
|
|
return kbase_io_history_init(&kbdev->io_history, KBASEP_DEFAULT_REGISTER_HISTORY_SIZE);
|
|
}
|
|
|
|
void kbase_device_io_history_term(struct kbase_device *kbdev)
|
|
{
|
|
kbase_io_history_term(&kbdev->io_history);
|
|
}
|
|
|
|
int kbase_device_misc_register(struct kbase_device *kbdev)
|
|
{
|
|
return misc_register(&kbdev->mdev);
|
|
}
|
|
|
|
void kbase_device_misc_deregister(struct kbase_device *kbdev)
|
|
{
|
|
misc_deregister(&kbdev->mdev);
|
|
}
|
|
|
|
int kbase_device_list_init(struct kbase_device *kbdev)
|
|
{
|
|
const struct list_head *dev_list;
|
|
|
|
dev_list = kbase_device_get_list();
|
|
list_add(&kbdev->entry, &kbase_dev_list);
|
|
kbase_device_put_list(dev_list);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void kbase_device_list_term(struct kbase_device *kbdev)
|
|
{
|
|
const struct list_head *dev_list;
|
|
|
|
dev_list = kbase_device_get_list();
|
|
list_del(&kbdev->entry);
|
|
kbase_device_put_list(dev_list);
|
|
}
|
|
|
|
const struct list_head *kbase_device_get_list(void)
|
|
{
|
|
mutex_lock(&kbase_dev_list_lock);
|
|
return &kbase_dev_list;
|
|
}
|
|
KBASE_EXPORT_TEST_API(kbase_device_get_list);
|
|
|
|
void kbase_device_put_list(const struct list_head *dev_list)
|
|
{
|
|
CSTD_UNUSED(dev_list);
|
|
mutex_unlock(&kbase_dev_list_lock);
|
|
}
|
|
KBASE_EXPORT_TEST_API(kbase_device_put_list);
|
|
|
|
int kbase_device_early_init(struct kbase_device *kbdev)
|
|
{
|
|
int err;
|
|
|
|
err = kbase_ktrace_init(kbdev);
|
|
if (err)
|
|
return err;
|
|
|
|
err = kbasep_platform_device_init(kbdev);
|
|
if (err)
|
|
goto ktrace_term;
|
|
|
|
err = kbase_pm_runtime_init(kbdev);
|
|
if (err)
|
|
goto platform_device_term;
|
|
|
|
/* This spinlock is initialized before doing the first access to GPU
|
|
* registers and installing interrupt handlers.
|
|
*/
|
|
spin_lock_init(&kbdev->hwaccess_lock);
|
|
|
|
/* Ensure we can access the GPU registers */
|
|
kbase_pm_register_access_enable(kbdev);
|
|
|
|
/*
|
|
* If -EPERM is returned, it means the device backend is not supported, but
|
|
* device initialization can continue.
|
|
*/
|
|
err = kbase_device_backend_init(kbdev);
|
|
if (err != 0 && err != -EPERM)
|
|
goto pm_runtime_term;
|
|
|
|
/*
|
|
* Initialize register mapping LUTs. This would have been initialized on HW
|
|
* Arbitration but not on PV or non-arbitration devices.
|
|
*/
|
|
if (!kbase_reg_is_init(kbdev)) {
|
|
/* Initialize GPU_ID props */
|
|
kbase_gpuprops_parse_gpu_id(&kbdev->gpu_props.gpu_id, kbase_reg_get_gpu_id(kbdev));
|
|
|
|
err = kbase_regmap_init(kbdev);
|
|
if (err)
|
|
goto backend_term;
|
|
}
|
|
|
|
/* Set the list of features available on the current HW
|
|
* (identified by the GPU_ID register)
|
|
*/
|
|
kbase_hw_set_features_mask(kbdev);
|
|
|
|
/* Find out GPU properties based on the GPU feature registers. */
|
|
err = kbase_gpuprops_init(kbdev);
|
|
if (err)
|
|
goto backend_term;
|
|
|
|
/* Get the list of workarounds for issues on the current HW
|
|
* (identified by the GPU_ID register and impl_tech in THREAD_FEATURES)
|
|
*/
|
|
err = kbase_hw_set_issues_mask(kbdev);
|
|
if (err)
|
|
goto gpuprops_term;
|
|
|
|
/* We're done accessing the GPU registers for now. */
|
|
kbase_pm_register_access_disable(kbdev);
|
|
|
|
if (kbase_has_arbiter(kbdev)) {
|
|
if (kbdev->pm.arb_vm_state)
|
|
err = kbase_arbiter_pm_install_interrupts(kbdev);
|
|
} else {
|
|
err = kbase_install_interrupts(kbdev);
|
|
}
|
|
if (err)
|
|
goto gpuprops_term;
|
|
|
|
return 0;
|
|
|
|
gpuprops_term:
|
|
kbase_gpuprops_term(kbdev);
|
|
backend_term:
|
|
kbase_device_backend_term(kbdev);
|
|
kbase_regmap_term(kbdev);
|
|
pm_runtime_term:
|
|
if (kbdev->pm.backend.gpu_powered)
|
|
kbase_pm_register_access_disable(kbdev);
|
|
|
|
kbase_pm_runtime_term(kbdev);
|
|
platform_device_term:
|
|
kbasep_platform_device_term(kbdev);
|
|
ktrace_term:
|
|
kbase_ktrace_term(kbdev);
|
|
|
|
return err;
|
|
}
|
|
|
|
void kbase_device_early_term(struct kbase_device *kbdev)
|
|
{
|
|
if (kbase_has_arbiter(kbdev))
|
|
kbase_arbiter_pm_release_interrupts(kbdev);
|
|
else
|
|
kbase_release_interrupts(kbdev);
|
|
kbase_gpuprops_term(kbdev);
|
|
kbase_device_backend_term(kbdev);
|
|
kbase_regmap_term(kbdev);
|
|
kbase_pm_runtime_term(kbdev);
|
|
kbasep_platform_device_term(kbdev);
|
|
kbase_ktrace_term(kbdev);
|
|
}
|
|
|
|
int kbase_device_late_init(struct kbase_device *kbdev)
|
|
{
|
|
int err;
|
|
|
|
err = kbasep_platform_device_late_init(kbdev);
|
|
|
|
return err;
|
|
}
|
|
|
|
void kbase_device_late_term(struct kbase_device *kbdev)
|
|
{
|
|
kbasep_platform_device_late_term(kbdev);
|
|
}
|