2717 lines
55 KiB
Plaintext
2717 lines
55 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*
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*/
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/ {
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dsi2lvds_backlight1: dsi2lvds_backlight1 {
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compatible = "pwm-backlight";
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brightness-levels = <
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0 20 20 21 21 22 22 23
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23 24 24 25 25 26 26 27
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27 28 28 29 29 30 30 31
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31 32 32 33 33 34 34 35
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35 36 36 37 37 38 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255
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>;
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default-brightness-level = <200>;
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};
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dp2lvds_backlight0: dp2lvds_backlight0 {
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compatible = "pwm-backlight";
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brightness-levels = <
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0 20 20 21 21 22 22 23
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23 24 24 25 25 26 26 27
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27 28 28 29 29 30 30 31
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31 32 32 33 33 34 34 35
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35 36 36 37 37 38 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255
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>;
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default-brightness-level = <200>;
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};
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dp2lvds_backlight1: dp2lvds_backlight1 {
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compatible = "pwm-backlight";
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brightness-levels = <
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0 20 20 21 21 22 22 23
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23 24 24 25 25 26 26 27
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27 28 28 29 29 30 30 31
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31 32 32 33 33 34 34 35
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35 36 36 37 37 38 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255
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>;
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default-brightness-level = <200>;
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};
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edp2lvds_backlight0: edp2lvds_backlight0 {
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compatible = "pwm-backlight";
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brightness-levels = <
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0 20 20 21 21 22 22 23
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23 24 24 25 25 26 26 27
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27 28 28 29 29 30 30 31
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31 32 32 33 33 34 34 35
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35 36 36 37 37 38 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255
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>;
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default-brightness-level = <200>;
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};
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edp2lvds_backlight1: edp2lvds_backlight1 {
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compatible = "pwm-backlight";
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brightness-levels = <
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0 20 20 21 21 22 22 23
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23 24 24 25 25 26 26 27
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27 28 28 29 29 30 30 31
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31 32 32 33 33 34 34 35
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35 36 36 37 37 38 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255
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>;
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default-brightness-level = <200>;
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};
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dsi2lvds_panel0 {
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compatible = "simple-panel";
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backlight = <&backlight>;
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display-timings {
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native-mode = <&dsi2lvds0>;
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dsi2lvds0: timing0 {
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clock-frequency = <115200000>;//115200000/105573600
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hactive = <1920>;
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vactive = <720>;
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hfront-porch = <56>;
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hsync-len = <32>;
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hback-porch = <56>;
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vfront-porch = <200>;
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vsync-len = <2>;
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vback-porch = <8>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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panel0_in_i2c2_bu18rl82: endpoint {
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remote-endpoint = <&i2c2_bu18rl82_out_panel0>;
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};
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};
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};
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};
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dsi2lvds_panel1 {
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compatible = "simple-panel";
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backlight = <&dsi2lvds_backlight1>;
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display-timings {
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native-mode = <&dsi2lvds1>;
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dsi2lvds1: timing0 {
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clock-frequency = <115200000>;
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hactive = <1920>;
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vactive = <720>;
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hfront-porch = <56>;
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hsync-len = <32>;
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hback-porch = <56>;
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vfront-porch = <200>;
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vsync-len = <2>;
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vback-porch = <8>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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panel1_in_i2c6_bu18rl82: endpoint {
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remote-endpoint = <&i2c6_bu18rl82_out_panel1>;
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};
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};
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};
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};
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dp2lvds_panel0 {
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compatible = "simple-panel";
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backlight = <&dp2lvds_backlight0>;
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status = "okay";
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panel-timing {
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clock-frequency = <115200000>;
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hactive = <1920>;
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vactive = <720>;
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hfront-porch = <56>;
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hsync-len = <32>;
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hback-porch = <56>;
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vfront-porch = <200>;
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vsync-len = <2>;
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vback-porch = <8>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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port {
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panel0_in_i2c4_bu18rl82: endpoint {
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remote-endpoint = <&i2c4_bu18rl82_out_panel0>;
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};
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};
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};
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dp2lvds_panel1 {
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compatible = "simple-panel";
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backlight = <&dp2lvds_backlight1>;
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status = "disabled";
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panel-timing {
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clock-frequency = <148500000>;
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hactive = <1920>;
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vactive = <1080>;
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hfront-porch = <140>;
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hsync-len = <40>;
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hback-porch = <100>;
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vfront-porch = <15>;
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vsync-len = <20>;
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vback-porch = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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port {
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panel1_in_i2c8_bu18rl82: endpoint {
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remote-endpoint = <&i2c8_bu18rl82_out_panel1>;
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};
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};
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};
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edp2lvds_panel0 {
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compatible = "simple-panel";
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backlight = <&edp2lvds_backlight0>;
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status = "okay";
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panel-timing {
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clock-frequency = <148500000>;
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hactive = <1920>;
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vactive = <1080>;
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hfront-porch = <140>;
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hsync-len = <40>;
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hback-porch = <100>;
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vfront-porch = <15>;
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vsync-len = <20>;
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vback-porch = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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port {
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panel0_in_i2c5_bu18rl82: endpoint {
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remote-endpoint = <&i2c5_bu18rl82_out_panel0>;
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};
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};
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};
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edp2lvds_panel1 {
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compatible = "simple-panel";
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backlight = <&edp2lvds_backlight1>;
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status = "disabled";
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panel-timing {
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clock-frequency = <148500000>;
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hactive = <1920>;
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vactive = <1080>;
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hfront-porch = <140>;
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hsync-len = <40>;
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hback-porch = <100>;
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vfront-porch = <15>;
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vsync-len = <20>;
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vback-porch = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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port {
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panel1_in_i2c7_bu18rl82: endpoint {
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remote-endpoint = <&i2c7_bu18rl82_out_panel1>;
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};
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};
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};
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};
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&backlight {
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pwms = <&pwm0 0 25000 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&bl0_enable_pin>;
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enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&dsi2lvds_backlight1 {
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pwms = <&pwm13 0 25000 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&bl1_enable_pin>;
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enable-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&dp0 {
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//rockchip,split-mode;
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force-hpd;
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status = "okay";
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ports {
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port@1 {
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reg = <1>;
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dp0_out_i2c4_bu18tl82: endpoint {
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link-frequencies = /bits/ 64 <1620000000>;
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remote-endpoint = <&i2c4_bu18tl82_in_dp0>;
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};
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};
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};
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};
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&dp0_in_vp0 {
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status = "okay";
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};
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&dp0_in_vp1 {
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status = "disabled";
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};
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&dp0_in_vp2 {
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status = "disabled";
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};
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&dp1 {
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force-hpd;
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status = "disabled";
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ports {
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port@1 {
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reg = <1>;
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dp1_out_i2c8_bu18tl82: endpoint {
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remote-endpoint = <&i2c8_bu18tl82_in_dp1>;
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};
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};
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};
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};
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&dp1_in_vp0 {
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status = "okay";
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};
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&dp1_in_vp1 {
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status = "disabled";
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};
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&dp1_in_vp2 {
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status = "disabled";
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};
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&dp2lvds_backlight0 {
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pwms = <&pwm10 0 25000 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&bl2_enable_pin>;
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enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&dp2lvds_backlight1 {
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pwms = <&pwm14 0 25000 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&bl3_enable_pin>;
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enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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/*
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* mipi_dcphy0 needs to be enabled
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* when dsi0 is enabled
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*/
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&dsi0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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dsi0_out_i2c2_bu18tl82: endpoint {
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remote-endpoint = <&i2c2_bu18tl82_in_dsi0>;
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};
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};
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};
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};
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&dsi0_in_vp2 {
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status = "okay";
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};
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&dsi0_in_vp3 {
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status = "disabled";
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};
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/*
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* mipi_dcphy1 needs to be enabled
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* when dsi1 is enabled
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*/
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&dsi1 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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dsi1_out_i2c6_bu18tl82: endpoint {
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remote-endpoint = <&i2c6_bu18tl82_in_dsi1>;
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};
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};
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};
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};
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&dsi1_in_vp2 {
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status = "disabled";
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};
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&dsi1_in_vp3 {
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status = "okay";
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};
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&edp0 {
|
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//rockchip,split-mode;
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force-hpd;
|
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status = "okay";
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ports {
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port@1 {
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reg = <1>;
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edp0_out_i2c5_bu18tl82: endpoint {
|
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remote-endpoint = <&i2c5_bu18tl82_in_edp0>;
|
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};
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};
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};
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};
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&edp0_in_vp0 {
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status = "disabled";
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};
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&edp0_in_vp1 {
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status = "okay";
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};
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&edp0_in_vp2 {
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status = "disabled";
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};
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&edp1 {
|
|
force-hpd;
|
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status = "disabled";
|
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|
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ports {
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port@1 {
|
|
reg = <1>;
|
|
|
|
edp1_out_i2c7_bu18tl82: endpoint {
|
|
remote-endpoint = <&i2c7_bu18tl82_in_edp1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&edp1_in_vp0 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&edp1_in_vp1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&edp1_in_vp2 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&edp2lvds_backlight0 {
|
|
pwms = <&pwm7 0 25000 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&bl4_enable_pin>;
|
|
enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
|
|
status = "okay";
|
|
};
|
|
|
|
&edp2lvds_backlight1 {
|
|
pwms = <&pwm11 0 25000 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&bl5_enable_pin>;
|
|
enable-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
|
|
status = "okay";
|
|
};
|
|
|
|
&hdmi0 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&hdmi1 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&hdptxphy0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&hdptxphy1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&hdptxphy_hdmi0 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&hdptxphy_hdmi1 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&i2c2 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2m4_xfer>;
|
|
clock-frequency = <400000>;
|
|
|
|
i2c2_bu18tl82: i2c2-bu18tl82@10 {
|
|
compatible = "rohm,bu18tl82";
|
|
reg = <0x10>;
|
|
sel-mipi;
|
|
status = "okay";
|
|
|
|
serdes-init-sequence = [
|
|
0013 0019
|
|
0014 0008 //014h[3]-lane1 enable
|
|
0021 0008
|
|
0023 0009
|
|
0024 0009
|
|
022b 0038
|
|
022c 0072
|
|
022d 0023 //VPLL=75MHZS
|
|
//022b 00d8
|
|
//022c 0089
|
|
//022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M
|
|
022e 0080
|
|
027c 0048
|
|
027d 0048 //i2c addr 0x48
|
|
0296 0004
|
|
0297 0009 //CLLTX0_PLL_GAIN 297h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane
|
|
//0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane
|
|
0018 00a5
|
|
0019 0069
|
|
0267 003d
|
|
0268 002c
|
|
0269 002c
|
|
026a 002c
|
|
026b 002c
|
|
0367 003d
|
|
0368 002c
|
|
0369 002c
|
|
036a 002c
|
|
036b 002c
|
|
0018 0000
|
|
0019 0000
|
|
//002a 0018 //gpio0 input lcd_bl_pwm
|
|
//002d 0018 //gpio1 input lcd_pwr_en
|
|
|
|
//0030 0018 //gpio2 input lcd_rst
|
|
//0033 0018 //gpio3 input tp_rst
|
|
//0034 0005 //bypass des gpio3
|
|
//0036 0000 //gpio4 output tp_int
|
|
//0037 0006 //bypass des gpio4
|
|
|
|
02a7 0002
|
|
02a8 0003
|
|
02a9 0004
|
|
02aa 0005
|
|
02af 0002 //gpio0 1MHZ
|
|
0045 0080
|
|
0046 0007 //1920
|
|
004b 00d0
|
|
004c 0002 //720
|
|
004d 00d0
|
|
004e 0002 //720
|
|
0051 0080
|
|
0052 0007 //1920
|
|
0053 0024 //CLLCH2_EN 53h[5] 0:1 Clock Tx lane/1:2 Clock Tx lanes
|
|
0054 0080
|
|
024d 0061
|
|
0252 0005
|
|
0274 0030 //I2C slave address of BU18RL82 for accessing via BU18TL82
|
|
0275 0020
|
|
0396 0004
|
|
0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.31 Gbps/lane
|
|
//0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.60 Gbps/lane
|
|
0061 0003 //CLLTX0 enable CLLTX1 enable
|
|
0060 0003 //CLLTX0/1 RGB data output Enable
|
|
/* TL82 Pattern Gen Set 1
|
|
* Horizontal Gray Scale 256 steps
|
|
*/
|
|
040A 0010
|
|
040B 0080
|
|
040C 0080
|
|
040D 0080
|
|
0444 0090
|
|
0446 00d2
|
|
];
|
|
|
|
i2c2_bu18tl82_pinctrl: i2c2-bu18tl82-pinctrl {
|
|
compatible = "rohm,bu18tl82-pinctrl";
|
|
pinctrl-names = "default","sleep";
|
|
pinctrl-0 = <&i2c2_bu18tl82_panel_pins>;
|
|
pinctrl-1 = <&i2c2_bu18tl82_panel_pins>;
|
|
status = "okay";
|
|
|
|
i2c2_bu18tl82_panel_pins: panel-pins {
|
|
lcd-bl-pwm {
|
|
pins = "BU18TL82_GPIO0";
|
|
function = "SER_TO_DES_GPIO0";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18TL82_GPIO1";
|
|
function = "SER_TO_DES_GPIO1";
|
|
};
|
|
|
|
ser-irq {
|
|
pins = "BU18TL82_GPIO2";
|
|
function = "DES_GPIO2_TO_SER";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18TL82_GPIO3";
|
|
function = "DES_GPIO4_TO_SER";
|
|
};
|
|
};
|
|
|
|
i2c2_bu18tl82_gpio: i2c2-bu18tl82-gpio {
|
|
compatible = "rohm,bu18tl82-gpio";
|
|
status = "okay";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c2_bu18tl82_pinctrl 0 160 8>;
|
|
};
|
|
};
|
|
|
|
i2c2_bu18tl82_bridge: i2c2-bu18tl82-bridge {
|
|
compatible = "rohm,bu18tl82-bridge";
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c2_bu18tl82_in_dsi0: endpoint {
|
|
remote-endpoint = <&dsi0_out_i2c2_bu18tl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c2_bu18tl82_out_i2c2_bu18rl82: endpoint {
|
|
remote-endpoint = <&i2c2_bu18rl82_in_i2c2_bu18tl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
i2c2_bu18rl82: i2c2-bu18rl82@30 {
|
|
compatible = "rohm,bu18rl82";
|
|
reg = <0x30>;
|
|
status = "okay";
|
|
|
|
serdes-init-sequence = [
|
|
0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA
|
|
0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB
|
|
0013 0000
|
|
001d 0008
|
|
001f 0002 //LVDSTX0_REFSEL
|
|
0020 0002 //LVDSTX1_REFSEL
|
|
0031 0048
|
|
0032 0048 //i2c addr 0x48
|
|
0423 0000
|
|
0424 0000
|
|
0425 0020
|
|
0426 0080
|
|
0057 0000 //rl gpio0 output lcd_bl_pwm
|
|
0058 0000 //bypass ser gpio0
|
|
005a 0000 //rl gpio1 output lcd_pwr_en
|
|
005b 0000 //bypass ser gpio1
|
|
005d 0000 //rl gpio2 output lcd_rst
|
|
005e 0000 //bypass ser gpio2
|
|
0060 0000 //rl gpio3 output tp-rst
|
|
0061 0000 //bypass ser gpio3
|
|
0063 0018 //rl gpio4 input tp-int
|
|
0064 0006 //bypass ser gpio4
|
|
0066 0000 //rl gpio5 output
|
|
0067 0000 //set gpio5 high
|
|
|
|
0073 0080
|
|
0074 0007 //0x0780 = 1920
|
|
0075 0080
|
|
0076 0007 //0x0780 = 1920
|
|
0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane
|
|
007b 00d0
|
|
007c 0002 //0x02d0 = 720
|
|
007d 00d0
|
|
007e 0002 //0x02d0 = 720
|
|
0081 0003 //01---> Sync OFF
|
|
0082 0010 //Hsync=16clk
|
|
0084 001c //HBP=28clk
|
|
0086 0002 //Vsync=2lines
|
|
0087 0008 //VBP=8lines
|
|
0088 0000 //VSYNC_CHG=0CLK
|
|
0089 0010 //Hsync = 16?
|
|
008b 001c //HFP=28clk?
|
|
008d 0002 //Vsync=2lines?
|
|
008e 0008 //VFP=8line?
|
|
008f 0000 //VSYNC_CHG=0CLK?
|
|
00d0 0040 //[3]FixHtotalEN
|
|
00d8 00c0
|
|
00d9 0003 //DE=960
|
|
0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz
|
|
045d 0001
|
|
0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz
|
|
055d 0001
|
|
0091 0003
|
|
0090 0001
|
|
/* RL82 Pattern Gen Set
|
|
* Vertical Gray Scale Color Bar
|
|
*/
|
|
060A 00B0
|
|
060B 00FF
|
|
060C 00FF
|
|
060D 00FF
|
|
0644 0090
|
|
0646 00d2
|
|
];
|
|
|
|
i2c2_bu18rl82_pinctrl: i2c2-bu18rl82-pinctrl {
|
|
compatible = "rohm,bu18rl82-pinctrl";
|
|
pinctrl-names = "default","init","sleep";
|
|
pinctrl-0 = <&i2c2_bu18rl82_panel_pins>;
|
|
pinctrl-1 = <&i2c2_bu18rl82_panel_pins>;
|
|
pinctrl-2 = <&i2c2_bu18rl82_panel_sleep_pins>;
|
|
status = "okay";
|
|
|
|
i2c2_bu18rl82_panel_pins: panel-pins {
|
|
lcd-otp-pin {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-rst {
|
|
pins = "BU18RL82_GPIO3";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
lcd-rst {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18RL82_GPIO4";
|
|
function = "DES_TO_SER_GPIO3";
|
|
};
|
|
|
|
40ms-delay {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "DELAY_40MS";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
lcd-bl-pwm {
|
|
pins = "BU18RL82_GPIO0";
|
|
function = "SER_GPIO0_TO_DES";
|
|
};
|
|
};
|
|
|
|
i2c2_bu18rl82_panel_sleep_pins: panel-sleep-pins {
|
|
lcd-rst-sleep {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
|
|
tp-rst-sleep {
|
|
pins = "BU18RL82_GPIO3";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
|
|
lcd-otp-pin-sleep {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
};
|
|
|
|
i2c2_bu18rl82_gpio: i2c2-bu18rl82-gpio {
|
|
compatible = "rohm,bu18rl82-gpio";
|
|
status = "okay";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c2_bu18rl82_pinctrl 0 169 8>;
|
|
};
|
|
};
|
|
|
|
i2c2_bu18rl82_bridge: i2c2-bu18rl82-bridge {
|
|
compatible = "rohm,bu18rl82-bridge";
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c2_bu18rl82_in_i2c2_bu18tl82: endpoint {
|
|
remote-endpoint = <&i2c2_bu18tl82_out_i2c2_bu18rl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c2_bu18rl82_out_panel0: endpoint {
|
|
remote-endpoint = <&panel0_in_i2c2_bu18rl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
himax@48 {
|
|
compatible = "himax,hxcommon";
|
|
reg = <0x48>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&touch_gpio_dsi0>;
|
|
pinctrl-1 = <&touch_gpio_dsi0>;
|
|
himax,location = "himax-touch-dsi0";
|
|
//himax,irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_FALLING>;
|
|
himax,rst-gpio = <&i2c2_bu18rl82_gpio 3 GPIO_ACTIVE_LOW>;
|
|
himax,panel-coords = <0 1920 0 720>;
|
|
himax,display-coords = <0 1920 0 720>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&i2c4 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4m2_xfer>;
|
|
clock-frequency = <400000>;
|
|
status = "okay";
|
|
|
|
i2c4_bu18tl82: i2c4-bu18tl82@10 {
|
|
compatible = "rohm,bu18tl82";
|
|
reg = <0x10>;
|
|
status = "okay";
|
|
|
|
serdes-init-sequence = [
|
|
0013 001a //013h[3]1-lane1 enable 013h[3] 1-LVDS Receiver Port-A
|
|
0014 000a //014h[3]1-lane1 enable 014h[3] 1-LVDS Receiver Port-B
|
|
0021 0008
|
|
0023 0009
|
|
0024 0009
|
|
022b 0038
|
|
022c 0072
|
|
022d 0023 //VPLL=75MHZS
|
|
//022b 00d8
|
|
//022c 0089
|
|
//022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M
|
|
022e 0080
|
|
ffff 1000 //delay 0x1000us
|
|
027c 0048
|
|
027d 0048 //i2c addr 0x48
|
|
0296 0004
|
|
0297 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.31 Gbps/lane
|
|
//0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.60 Gbps/lane
|
|
0018 00a5
|
|
0019 0069
|
|
0267 003d
|
|
0268 002c
|
|
0269 002c
|
|
026a 002c
|
|
026b 002c
|
|
0367 003d
|
|
0368 002c
|
|
0369 002c
|
|
036a 002c
|
|
036b 002c
|
|
0018 0000
|
|
0019 0000
|
|
//002a 0018 //gpio0 input lcd_bl_pwm
|
|
//002d 0018 //gpio1 input lcd_pwr_en
|
|
|
|
//0030 0018 //gpio2 input lcd_rst
|
|
//0033 0018 //gpio3 input tp_rst
|
|
//0034 0005 //bypass des gpio3
|
|
//0036 0000 //gpio4 output tp_int
|
|
//0037 0006 //bypass des gpio4
|
|
|
|
02a7 0002
|
|
02a8 0003
|
|
02a9 0004
|
|
02aa 0005
|
|
02af 0002 //gpio0 1MHZ
|
|
0045 0080
|
|
0046 0007 //1920
|
|
004b 00d0
|
|
004c 0002 //720
|
|
004d 00d0
|
|
004e 0002 //720
|
|
0051 0080
|
|
0052 0007 //1920
|
|
0053 0064 //0053h[6]1:2 Rx ports CLLCH2_EN 53h[5] 1:2 Clock Tx lanes
|
|
024d 0061
|
|
0252 0005
|
|
0274 0030
|
|
0275 0020
|
|
0396 0004
|
|
0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane
|
|
//0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane
|
|
0061 0003 //CLLTX0 enable CLLTX1 enable
|
|
0060 0003 //CLLTX0/1 RGB data output Enable
|
|
/* TL82 Pattern Gen Set 1
|
|
* Horizontal Gray Scale 256 steps
|
|
*/
|
|
040A 0010
|
|
040B 0080
|
|
040C 0080
|
|
040D 0080
|
|
0444 0090 //h_blank=144
|
|
0446 00d2 //v_blank=210
|
|
];
|
|
|
|
i2c4_bu18tl82_pinctrl: i2c4-bu18tl82-pinctrl {
|
|
compatible = "rohm,bu18tl82-pinctrl";
|
|
pinctrl-names = "default","sleep";
|
|
pinctrl-0 = <&i2c4_bu18tl82_panel_pins>;
|
|
pinctrl-1 = <&i2c4_bu18tl82_panel_pins>;
|
|
status = "okay";
|
|
|
|
i2c4_bu18tl82_panel_pins: panel-pins {
|
|
lcd-bl-pwm {
|
|
pins = "BU18TL82_GPIO0";
|
|
function = "SER_TO_DES_GPIO0";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18TL82_GPIO1";
|
|
function = "SER_TO_DES_GPIO1";
|
|
};
|
|
|
|
ser-irq {
|
|
pins = "BU18TL82_GPIO2";
|
|
function = "DES_GPIO2_TO_SER";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18TL82_GPIO3";
|
|
function = "DES_GPIO4_TO_SER";
|
|
};
|
|
|
|
};
|
|
|
|
i2c4_bu18tl82_gpio: i2c4-bu18tl82-gpio {
|
|
compatible = "rohm,bu18tl82-gpio";
|
|
status = "okay";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c4_bu18tl82_pinctrl 0 178 8>;
|
|
};
|
|
};
|
|
|
|
i2c4_bu18tl82_bridge: i2c4-bu18tl82-bridge {
|
|
compatible = "rohm,bu18tl82-bridge";
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c4_bu18tl82_in_dp0: endpoint {
|
|
remote-endpoint = <&dp0_out_i2c4_bu18tl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c4_bu18tl82_out_i2c4_bu18rl82: endpoint {
|
|
remote-endpoint = <&i2c4_bu18rl82_in_i2c4_bu18tl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
i2c4_bu18rl82: i2c4-bu18rl82@30 {
|
|
compatible = "rohm,bu18rl82";
|
|
reg = <0x30>;
|
|
status = "okay";
|
|
|
|
serdes-init-sequence = [
|
|
0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA
|
|
0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB
|
|
0013 0000
|
|
001d 0008
|
|
001f 0002 //LVDSTX0_REFSEL
|
|
0020 0002 //LVDSTX1_REFSEL
|
|
0031 0048
|
|
0032 0048 //i2c addr 0x48
|
|
0423 0000
|
|
0424 0000
|
|
0425 0020
|
|
0426 0080
|
|
0057 0000 //rl gpio0 output lcd_bl_pwm
|
|
0058 0000 //set gpio0 low
|
|
005a 0000 //rl gpio1 output lcd_pwr_en
|
|
005b 0000 //set gpio1 low
|
|
005d 0000 //rl gpio2 output lcd_rst
|
|
005e 0000 //set gpio2 low
|
|
0060 0000 //rl gpio3 output tp-rst
|
|
0061 0000 //set gpio3 low
|
|
0063 0018 //rl gpio4 input tp-int
|
|
0064 0006 //bypass ser gpio4
|
|
0066 0000 //rl gpio5 output
|
|
0067 0000 //set gpio5 low
|
|
|
|
0073 0080
|
|
0074 0007 //0x0780 = 1920
|
|
0075 0080
|
|
0076 0007 //0x0780 = 1920
|
|
0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane
|
|
007b 00d0
|
|
007c 0002 //0x02d0 = 720
|
|
007d 00d0
|
|
007e 0002 //0x02d0 = 720
|
|
0081 0003 //01---> Sync OFF
|
|
0082 0010 //Hsync=16clk
|
|
0084 001c //HBP=28clk
|
|
0086 0002 //Vsync=2lines
|
|
0087 0008 //VBP=8lines
|
|
0088 0000 //VSYNC_CHG=0CLK
|
|
0089 0010 //Hsync = 16?
|
|
008b 001c //HFP=28clk?
|
|
008d 0002 //Vsync=2lines?
|
|
008e 0008 //VFP=8line?
|
|
008f 0000 //VSYNC_CHG=0CLK?
|
|
00d0 0040 //[3]FixHtotalEN
|
|
00d8 00c0
|
|
00d9 0003 //DE=960
|
|
0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz
|
|
045d 0001
|
|
0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz
|
|
055d 0001
|
|
0091 0003
|
|
0090 0001
|
|
/* RL82 Pattern Gen Set
|
|
* Vertical Gray Scale Color Bar
|
|
*/
|
|
060A 00B0
|
|
060B 00FF
|
|
060C 00FF
|
|
060D 00FF
|
|
0644 0090
|
|
0646 00d2
|
|
];
|
|
|
|
i2c4_bu18rl82_pinctrl: i2c4-bu18rl82-pinctrl {
|
|
compatible = "rohm,bu18rl82-pinctrl";
|
|
pinctrl-names = "default","init","sleep";
|
|
pinctrl-0 = <&i2c4_bu18rl82_panel_pins>;
|
|
pinctrl-1 = <&i2c4_bu18rl82_panel_pins>;
|
|
pinctrl-2 = <&i2c4_bu18rl82_panel_sleep_pins>;
|
|
status = "okay";
|
|
|
|
i2c4_bu18rl82_panel_pins: panel-pins {
|
|
lcd-otp-pin {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-rst {
|
|
pins = "BU18RL82_GPIO3";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
lcd-rst {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18RL82_GPIO4";
|
|
function = "DES_TO_SER_GPIO3";
|
|
};
|
|
|
|
40ms-delay {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "DELAY_40MS";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
lcd-bl-pwm {
|
|
pins = "BU18RL82_GPIO0";
|
|
function = "SER_GPIO0_TO_DES";
|
|
};
|
|
};
|
|
|
|
i2c4_bu18rl82_panel_sleep_pins: panel-sleep-pins {
|
|
lcd-rst-sleep {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
|
|
tp-rst-sleep {
|
|
pins = "BU18RL82_GPIO3";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
|
|
lcd-otp-pin-sleep {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
};
|
|
|
|
i2c4_bu18rl82_gpio: i2c4-bu18rl82-gpio {
|
|
compatible = "rohm,bu18rl82-gpio";
|
|
status = "okay";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c4_bu18rl82_pinctrl 0 187 8>;
|
|
};
|
|
};
|
|
|
|
i2c4_bu18rl82_bridge: i2c4-bu18rl82-bridge {
|
|
compatible = "rohm,bu18rl82-bridge";
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c4_bu18rl82_in_i2c4_bu18tl82: endpoint {
|
|
remote-endpoint = <&i2c4_bu18tl82_out_i2c4_bu18rl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c4_bu18rl82_out_panel0: endpoint {
|
|
remote-endpoint = <&panel0_in_i2c4_bu18rl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
himax@48 {
|
|
compatible = "himax,hxcommon";
|
|
reg = <0x48>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&touch_gpio_dp0>;
|
|
pinctrl-1 = <&touch_gpio_dp0>;
|
|
himax,location = "himax-touch-dp0";
|
|
himax,irq-gpio = <&gpio3 RK_PC5 IRQ_TYPE_EDGE_FALLING>;
|
|
himax,rst-gpio = <&i2c4_bu18rl82_gpio 3 GPIO_ACTIVE_LOW>;
|
|
himax,panel-coords = <0 1920 0 720>;
|
|
himax,display-coords = <0 1920 0 720>;
|
|
status = "okay";
|
|
};
|
|
|
|
lt7911d@2b {
|
|
compatible = "lontium,lt7911d-fb-notifier";
|
|
reg = <0x2b>;
|
|
reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&i2c5 {
|
|
clock-frequency = <400000>;
|
|
status = "okay";
|
|
|
|
i2c5_bu18tl82: i2c5-bu18tl82@10 {
|
|
compatible = "rohm,bu18tl82";
|
|
reg = <0x10>;
|
|
status = "okay";
|
|
|
|
serdes-init-sequence = [
|
|
0013 001a
|
|
0014 000a
|
|
0021 0008
|
|
0023 0009
|
|
0024 0009
|
|
//002a 0018 //gpio0 input lcd_bl_pwm
|
|
//002d 0018 //gpio1 input lcd_pwr_en
|
|
|
|
//0030 0018 //gpio2 input lcd_rst
|
|
//0033 0000 //gpio3 output tp_int
|
|
//0034 0005 //bypass des gpio3
|
|
//0036 0018 //gpio4 input tp_rst
|
|
//0037 0006 //bypass des gpio4
|
|
027c 0041
|
|
027d 0041
|
|
0045 0080
|
|
0046 0007
|
|
004b 0038
|
|
004c 0004
|
|
0053 0064
|
|
022b 0062
|
|
022c 0027
|
|
022d 002e
|
|
0274 0030
|
|
0275 0020
|
|
0296 0004
|
|
0297 000d
|
|
02af 0002 //gpio0 1MHZ
|
|
02b2 00c8
|
|
02b4 0001
|
|
02b8 00ff
|
|
02b9 000f
|
|
02ba 00ff
|
|
02bb 000f
|
|
02be 00ff
|
|
02bf 001f
|
|
02c2 00ff
|
|
02c3 001f
|
|
0396 0004
|
|
0397 000d
|
|
03b2 00c8
|
|
03b4 0001
|
|
03b8 00ff
|
|
03b9 000f
|
|
03ba 00ff
|
|
03bb 000f
|
|
03be 00ff
|
|
03bf 001f
|
|
03c2 00ff
|
|
03c3 001f
|
|
0060 0001
|
|
0061 0003
|
|
022e 0080
|
|
032e 0080
|
|
/* TL82 Pattern Gen Set 1
|
|
* Horizontal Gray Scale 256 steps
|
|
*/
|
|
040A 0010
|
|
040B 0080
|
|
040C 0080
|
|
040D 0080
|
|
0444 0019
|
|
0445 0020
|
|
0446 001f
|
|
];
|
|
|
|
i2c5_bu18tl82_pinctrl: i2c5-bu18tl82-pinctrl {
|
|
compatible = "rohm,bu18tl82-pinctrl";
|
|
pinctrl-names = "default","sleep";
|
|
pinctrl-0 = <&i2c5_bu18tl82_panel_pins>;
|
|
pinctrl-1 = <&i2c5_bu18tl82_panel_pins>;
|
|
status = "okay";
|
|
|
|
i2c5_bu18tl82_panel_pins: panel-pins {
|
|
lcd-bl-pwm {
|
|
pins = "BU18TL82_GPIO0";
|
|
function = "SER_TO_DES_GPIO0";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18TL82_GPIO1";
|
|
function = "SER_TO_DES_GPIO1";
|
|
};
|
|
|
|
ser-irq {
|
|
pins = "BU18TL82_GPIO2";
|
|
function = "DES_GPIO2_TO_SER";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18TL82_GPIO3";
|
|
function = "DES_GPIO3_TO_SER";
|
|
};
|
|
};
|
|
|
|
|
|
i2c5_bu18tl82_gpio: i2c5-bu18tl82-gpio {
|
|
compatible = "rohm,bu18tl82-gpio";
|
|
status = "okay";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c5_bu18tl82_pinctrl 0 196 8>;
|
|
};
|
|
};
|
|
|
|
i2c5_bu18tl82_bridge: i2c5-bu18tl82-bridge {
|
|
compatible = "rohm,bu18tl82-bridge";
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c5_bu18tl82_in_edp0: endpoint {
|
|
remote-endpoint = <&edp0_out_i2c5_bu18tl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c5_bu18tl82_out_i2c5_bu18rl82: endpoint {
|
|
remote-endpoint = <&i2c5_bu18rl82_in_i2c5_bu18tl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
i2c5_bu18rl82: i2c5-bu18rl82@30 {
|
|
compatible = "rohm,bu18rl82";
|
|
reg = <0x30>;
|
|
status = "okay";
|
|
|
|
serdes-init-sequence = [
|
|
0011 000b
|
|
0012 0003
|
|
0013 0001
|
|
001d 0008
|
|
001f 0002
|
|
0020 0002
|
|
0031 0041 //i2c addr 0x41
|
|
0032 0041 //i2c addr 0x41
|
|
0057 0000 //rl gpio0 output lcd_bl_pwm
|
|
0058 0000 //set gpio0 low
|
|
005a 0000 //rl gpio1 output lcd_pwr_en
|
|
005b 0000 //set gpio1 low
|
|
005d 0000 //rl gpio2 output lcd_rst
|
|
005e 0000 //set gpio2 low
|
|
0060 0000 //rl gpio3 output tp-rst
|
|
0061 0000 //set gpio3 low
|
|
0063 0018 //rl gpio4 input tp-int
|
|
0064 0006 //bypass ser gpio4
|
|
0066 0000 //rl gpio5 output
|
|
0067 0000 //set gpio5 low
|
|
0073 0080
|
|
0074 0007
|
|
0079 000a
|
|
007b 0038
|
|
007c 0004
|
|
0081 0003
|
|
0082 0010
|
|
0084 0020
|
|
0086 0002
|
|
0087 0002
|
|
0088 0010
|
|
0089 0010
|
|
008b 0020
|
|
008d 0002
|
|
008e 0002
|
|
008f 0010
|
|
00d0 0040
|
|
00d8 0042
|
|
00d9 0004
|
|
0423 0002
|
|
0424 00ec
|
|
0425 0027
|
|
0429 000a
|
|
045d 0001
|
|
0529 000a
|
|
055d 0003
|
|
0090 0001
|
|
0091 0003
|
|
0426 0080
|
|
042d 0004
|
|
/* RL82 Pattern Gen Set
|
|
* Vertical Gray Scale Color Bar
|
|
*/
|
|
060A 00B0
|
|
060B 00FF
|
|
060C 00FF
|
|
060D 00FF
|
|
0644 0019
|
|
0645 0020
|
|
0646 001f
|
|
];
|
|
|
|
i2c5_bu18rl82_pinctrl: i2c5-bu18rl82-pinctrl {
|
|
compatible = "rohm,bu18rl82-pinctrl";
|
|
pinctrl-names = "default","init","sleep";
|
|
pinctrl-0 = <&i2c5_bu18rl82_panel_pins>;
|
|
pinctrl-1 = <&i2c5_bu18rl82_panel_pins>;
|
|
pinctrl-2 = <&i2c5_bu18rl82_panel_sleep_pins>;
|
|
status = "okay";
|
|
|
|
i2c5_bu18rl82_panel_pins: panel-pins {
|
|
lcd-otp-pin {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-rst {
|
|
pins = "BU18RL82_GPIO3";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
lcd-rst {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18RL82_GPIO4";
|
|
function = "DES_TO_SER_GPIO3";
|
|
};
|
|
|
|
40ms-delay {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "DELAY_40MS";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
lcd-bl-pwm {
|
|
pins = "BU18RL82_GPIO0";
|
|
function = "SER_GPIO0_TO_DES";
|
|
};
|
|
};
|
|
|
|
i2c5_bu18rl82_panel_sleep_pins: panel-sleep-pins {
|
|
lcd-rst-sleep {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
|
|
tp-rst-sleep {
|
|
pins = "BU18RL82_GPIO4";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
|
|
lcd-otp-pin-sleep {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
};
|
|
|
|
i2c5_bu18rl82_gpio: i2c5-bu18rl82-gpio {
|
|
compatible = "rohm,bu18rl82-gpio";
|
|
status = "okay";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c5_bu18rl82_pinctrl 0 205 8>;
|
|
};
|
|
};
|
|
|
|
i2c5_bu18rl82_bridge: i2c5-bu18rl82-bridge {
|
|
compatible = "rohm,bu18rl82-bridge";
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c5_bu18rl82_in_i2c5_bu18tl82: endpoint {
|
|
remote-endpoint = <&i2c5_bu18tl82_out_i2c5_bu18rl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c5_bu18rl82_out_panel0: endpoint {
|
|
remote-endpoint = <&panel0_in_i2c5_bu18rl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
ilitek@41 {
|
|
compatible = "ilitek,ili251x";
|
|
reg = <0x41>;
|
|
interrupt-parent = <&gpio1>;
|
|
interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&touch_gpio_edp0>;
|
|
//reset-gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_LOW>;
|
|
ilitek,name = "ilitek_i2c";
|
|
status = "okay";
|
|
};
|
|
|
|
lt7911d@2b {
|
|
compatible = "lontium,lt7911d-fb-notifier";
|
|
reg = <0x2b>;
|
|
reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&i2c6 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c6m3_xfer>;
|
|
clock-frequency = <400000>;
|
|
|
|
i2c6_bu18tl82: i2c6-bu18tl82@10 {
|
|
compatible = "rohm,bu18tl82";
|
|
reg = <0x10>;
|
|
sel-mipi;
|
|
status = "okay";
|
|
|
|
serdes-init-sequence = [
|
|
0013 0019
|
|
0014 0008 //014h[3]-lane1 enable
|
|
0021 0008
|
|
0023 0009
|
|
0024 0009
|
|
022b 0038
|
|
022c 0072
|
|
022d 0023 //VPLL=75MHZS
|
|
//022b 00d8
|
|
//022c 0089
|
|
//022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M
|
|
022e 0080
|
|
027c 0048
|
|
027d 0048 //i2c addr 0x48
|
|
0296 0004
|
|
0297 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane
|
|
//0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane
|
|
0018 00a5
|
|
0019 0069
|
|
0267 003d
|
|
0268 002c
|
|
0269 002c
|
|
026a 002c
|
|
026b 002c
|
|
0367 003d
|
|
0368 002c
|
|
0369 002c
|
|
036a 002c
|
|
036b 002c
|
|
0018 0000
|
|
0019 0000
|
|
//002a 0018 //gpio0 input lcd_bl_pwm
|
|
//002d 0018 //gpio1 input lcd_pwr_en
|
|
|
|
//0030 0018 //gpio2 input lcd_rst
|
|
//0033 0018 //gpio3 input tp_rst
|
|
//0034 0005 //bypass des gpio3
|
|
//0036 0000 //gpio4 output tp_int
|
|
//0037 0006 //bypass des gpio4
|
|
|
|
02a7 0002
|
|
02a8 0003
|
|
02a9 0004
|
|
02aa 0005
|
|
02af 0002 //gpio0 1MHZ
|
|
0045 0080
|
|
0046 0007 //1920
|
|
004b 00d0
|
|
004c 0002 //720
|
|
004d 00d0
|
|
004e 0002 //720
|
|
0051 0080
|
|
0052 0007 //1920
|
|
0053 0024 //CLLCH2_EN 53h[5] 0:1 Clock Tx lane/1:2 Clock Tx lanes
|
|
0054 0080
|
|
024d 0061
|
|
0252 0005
|
|
0274 0030
|
|
0275 0020
|
|
0396 0004
|
|
0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane
|
|
//0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane
|
|
0061 0003 //CLLTX0 enable CLLTX1 enable
|
|
0060 0003 //CLLTX0/1 RGB data output Enable
|
|
/* TL82 Pattern Gen Set 1
|
|
* Horizontal Gray Scale 256 steps
|
|
*/
|
|
040A 0010
|
|
040B 0080
|
|
040C 0080
|
|
040D 0080
|
|
0444 0090 //h_blank=144
|
|
0446 00d2 //v_blank=210
|
|
|
|
|
|
];
|
|
|
|
i2c6_bu18tl82_pinctrl: i2c6-bu18tl82-pinctrl {
|
|
compatible = "rohm,bu18tl82-pinctrl";
|
|
pinctrl-names = "default","sleep";
|
|
pinctrl-0 = <&i2c6_bu18tl82_panel_pins>;
|
|
pinctrl-1 = <&i2c6_bu18tl82_panel_pins>;
|
|
status = "okay";
|
|
|
|
i2c6_bu18tl82_panel_pins: panel-pins {
|
|
lcd-bl-pwm {
|
|
pins = "BU18TL82_GPIO0";
|
|
function = "SER_TO_DES_GPIO0";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18TL82_GPIO1";
|
|
function = "SER_TO_DES_GPIO1";
|
|
};
|
|
|
|
ser-irq {
|
|
pins = "BU18TL82_GPIO2";
|
|
function = "DES_GPIO2_TO_SER";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18TL82_GPIO3";
|
|
function = "DES_GPIO4_TO_SER";
|
|
};
|
|
};
|
|
|
|
|
|
i2c6_bu18tl82_gpio: i2c6-bu18tl82-gpio {
|
|
compatible = "rohm,bu18tl82-gpio";
|
|
status = "okay";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c6_bu18tl82_pinctrl 0 214 8>;
|
|
};
|
|
};
|
|
|
|
i2c6_bu18tl82_bridge: i2c6-bu18tl82-bridge {
|
|
compatible = "rohm,bu18tl82-bridge";
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c6_bu18tl82_in_dsi1: endpoint {
|
|
remote-endpoint = <&dsi1_out_i2c6_bu18tl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c6_bu18tl82_out_i2c6_bu18rl82: endpoint {
|
|
remote-endpoint = <&i2c6_bu18rl82_in_i2c6_bu18tl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
i2c6_bu18rl82: i2c6-bu18rl82@30 {
|
|
compatible = "rohm,bu18rl82";
|
|
reg = <0x30>;
|
|
status = "okay";
|
|
|
|
serdes-init-sequence = [
|
|
0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA
|
|
0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB
|
|
0013 0000
|
|
001d 0008
|
|
001f 0002 //LVDSTX0_REFSEL
|
|
0020 0002 //LVDSTX1_REFSEL
|
|
0031 0048
|
|
0032 0048 //i2c addr 0x48
|
|
0423 0000
|
|
0424 0000
|
|
0425 0020
|
|
0426 0080
|
|
0057 0000 //rl gpio0 output lcd_bl_pwm
|
|
0058 0000 //set gpio0 low
|
|
005a 0000 //rl gpio1 output lcd_pwr_en
|
|
005b 0000 //set gpio1 low
|
|
005d 0000 //rl gpio2 output lcd_rst
|
|
005e 0000 //set gpio2 low
|
|
0060 0000 //rl gpio3 output tp-rst
|
|
0061 0000 //set gpio3 low
|
|
0063 0018 //rl gpio4 input tp-int
|
|
0064 0006 //bypass ser gpio4
|
|
0066 0000 //rl gpio5 output
|
|
0067 0000 //set gpio5 low
|
|
|
|
0073 0080
|
|
0074 0007 //0x0780 = 1920
|
|
0075 0080
|
|
0076 0007 //0x0780 = 1920
|
|
0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane
|
|
007b 00d0
|
|
007c 0002 //0x02d0 = 720
|
|
007d 00d0
|
|
007e 0002 //0x02d0 = 720
|
|
0081 0003 //01---> Sync OFF
|
|
0082 0010 //Hsync=16clk
|
|
0084 001c //HBP=28clk
|
|
0086 0002 //Vsync=2lines
|
|
0087 0008 //VBP=8lines
|
|
0088 0000 //VSYNC_CHG=0CLK
|
|
0089 0010 //Hsync = 16?
|
|
008b 001c //HFP=28clk?
|
|
008d 0002 //Vsync=2lines?
|
|
008e 0008 //VFP=8line?
|
|
008f 0000 //VSYNC_CHG=0CLK?
|
|
00d0 0040 //[3]FixHtotalEN
|
|
00d8 00c0
|
|
00d9 0003 //DE=960
|
|
0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz
|
|
045d 0001
|
|
0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz
|
|
055d 0001
|
|
0091 0003
|
|
0090 0001
|
|
/* RL82 Pattern Gen Set
|
|
* Vertical Gray Scale Color Bar
|
|
*/
|
|
060A 00B0
|
|
060B 00FF
|
|
060C 00FF
|
|
060D 00FF
|
|
0644 0090
|
|
0646 00d2
|
|
];
|
|
|
|
i2c6_bu18rl82_pinctrl: i2c6-bu18rl82-pinctrl {
|
|
compatible = "rohm,bu18rl82-pinctrl";
|
|
pinctrl-names = "default","init","sleep";
|
|
pinctrl-0 = <&i2c6_bu18rl82_panel_pins>;
|
|
pinctrl-1 = <&i2c6_bu18rl82_panel_pins>;
|
|
pinctrl-2 = <&i2c6_bu18rl82_panel_sleep_pins>;
|
|
status = "okay";
|
|
|
|
i2c6_bu18rl82_panel_pins: panel-pins {
|
|
lcd-otp-pin {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-rst {
|
|
pins = "BU18RL82_GPIO3";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
lcd-rst {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18RL82_GPIO4";
|
|
function = "DES_TO_SER_GPIO3";
|
|
};
|
|
|
|
40ms-delay {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "DELAY_40MS";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
lcd-bl-pwm {
|
|
pins = "BU18RL82_GPIO0";
|
|
function = "SER_GPIO0_TO_DES";
|
|
};
|
|
};
|
|
|
|
i2c6_bu18rl82_panel_sleep_pins: panel-sleep-pins {
|
|
lcd-rst-sleep {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
|
|
tp-rst-sleep {
|
|
pins = "BU18RL82_GPIO3";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
|
|
lcd-otp-pin-sleep {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
};
|
|
|
|
i2c6_bu18rl82_gpio: i2c6-bu18rl82-gpio {
|
|
compatible = "rohm,bu18rl82-gpio";
|
|
status = "okay";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c6_bu18rl82_pinctrl 0 223 8>;
|
|
};
|
|
};
|
|
|
|
i2c6_bu18rl82_bridge: i2c6-bu18rl82-bridge {
|
|
compatible = "rohm,bu18rl82-bridge";
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c6_bu18rl82_in_i2c6_bu18tl82: endpoint {
|
|
remote-endpoint = <&i2c6_bu18tl82_out_i2c6_bu18rl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c6_bu18rl82_out_panel1: endpoint {
|
|
remote-endpoint = <&panel1_in_i2c6_bu18rl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
himax@48 {
|
|
compatible = "himax,hxcommon";
|
|
reg = <0x48>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&touch_gpio_dsi1>;
|
|
pinctrl-1 = <&touch_gpio_dsi1>;
|
|
himax,location = "himax-touch-dsi1";
|
|
himax,irq-gpio = <&gpio1 RK_PB7 IRQ_TYPE_EDGE_FALLING>;
|
|
himax,rst-gpio = <&i2c6_bu18rl82_gpio 3 GPIO_ACTIVE_LOW>;
|
|
himax,panel-coords = <0 1920 0 720>;
|
|
himax,display-coords = <0 1920 0 720>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&i2c7 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c7m3_xfer>;
|
|
clock-frequency = <400000>;
|
|
|
|
i2c7_bu18tl82: i2c7-bu18tl82@10 {
|
|
compatible = "rohm,bu18tl82";
|
|
reg = <0x10>;
|
|
status = "disabled";
|
|
|
|
serdes-init-sequence = [
|
|
0013 001a
|
|
0014 000a
|
|
0021 0008
|
|
0023 0009
|
|
0024 0009
|
|
002a 0018 //gpio0 input lcd_bl_pwm
|
|
002d 0018 //gpio1 input lcd_pwr_en
|
|
|
|
0030 0018 //gpio2 input lcd_rst
|
|
0033 0000 //gpio3 output tp_int
|
|
0034 0005 //bypass des gpio3
|
|
0036 0018 //gpio4 input tp_rst
|
|
0037 0006 //bypass des gpio4
|
|
027c 0041
|
|
027d 0041
|
|
0045 0080
|
|
0046 0007
|
|
004b 0038
|
|
004c 0004
|
|
0053 0064
|
|
022b 0062
|
|
022c 0027
|
|
022d 002e
|
|
0274 0030
|
|
0275 0020
|
|
0296 0004
|
|
0297 000d
|
|
02af 0002 //gpio0 1MHZ
|
|
02b2 00c8
|
|
02b4 0001
|
|
02b8 00ff
|
|
02b9 000f
|
|
02ba 00ff
|
|
02bb 000f
|
|
02be 00ff
|
|
02bf 001f
|
|
02c2 00ff
|
|
02c3 001f
|
|
0396 0004
|
|
0397 000d
|
|
03b2 00c8
|
|
03b4 0001
|
|
03b8 00ff
|
|
03b9 000f
|
|
03ba 00ff
|
|
03bb 000f
|
|
03be 00ff
|
|
03bf 001f
|
|
03c2 00ff
|
|
03c3 001f
|
|
0060 0001
|
|
0061 0003
|
|
022e 0080
|
|
032e 0080
|
|
/* TL82 Pattern Gen Set 1
|
|
* Horizontal Gray Scale 256 steps
|
|
*/
|
|
040A 0010
|
|
040B 0080
|
|
040C 0080
|
|
040D 0080
|
|
0444 0019
|
|
0445 0020
|
|
0446 001f
|
|
];
|
|
|
|
i2c7_bu18tl82_pinctrl: i2c7-bu18tl82-pinctrl {
|
|
compatible = "rohm,bu18tl82-pinctrl";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c7_bu18tl82_panel_pins>;
|
|
status = "disabled";
|
|
|
|
i2c7_bu18tl82_panel_pins: panel-pins {
|
|
lcd-bl-pwm {
|
|
pins = "BU18TL82_GPIO0";
|
|
function = "SER_TO_DES_GPIO0";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18TL82_GPIO1";
|
|
function = "SER_TO_DES_GPIO1";
|
|
};
|
|
|
|
ser-irq {
|
|
pins = "BU18TL82_GPIO2";
|
|
function = "DES_GPIO2_TO_SER";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18TL82_GPIO3";
|
|
function = "DES_GPIO4_TO_SER";
|
|
};
|
|
};
|
|
|
|
|
|
i2c7_bu18tl82_gpio: i2c7-bu18tl82-gpio {
|
|
compatible = "rohm,bu18tl82-gpio";
|
|
status = "disabled";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c7_bu18tl82_pinctrl 0 232 8>;
|
|
};
|
|
};
|
|
|
|
i2c7_bu18tl82_bridge: i2c7-bu18tl82-bridge {
|
|
compatible = "rohm,bu18tl82-bridge";
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c7_bu18tl82_in_edp1: endpoint {
|
|
remote-endpoint = <&edp1_out_i2c7_bu18tl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c7_bu18tl82_out_i2c7_bu18rl82: endpoint {
|
|
remote-endpoint = <&i2c7_bu18rl82_in_i2c7_bu18tl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
i2c7_bu18rl82: i2c7-bu18rl82@30 {
|
|
compatible = "rohm,bu18rl82";
|
|
reg = <0x30>;
|
|
status = "disabled";
|
|
|
|
serdes-init-sequence = [
|
|
0011 000b
|
|
0012 0003
|
|
0013 0001
|
|
001d 0008
|
|
001f 0002
|
|
0020 0002
|
|
0031 0041 //i2c addr 0x41
|
|
0032 0041 //i2c addr 0x41
|
|
0057 0000 //rl gpio0 output lcd_bl_pwm
|
|
0058 0002 //bypass ser gpio0
|
|
005a 0000 //rl gpio1 output lcd_pwr_en
|
|
005b 0001 //bypass ser gpio1
|
|
005d 0000 //rl gpio2 output lcd_rst
|
|
005e 0004 //bypass ser gpio2
|
|
0060 0018 //rl gpio3 input tp-int
|
|
042e 0005 //bypass ser gpio3
|
|
0061 0005 //bypass ser gpio3
|
|
0063 0000 //rl gpio4 output tp-rst
|
|
0064 0006 //bypass ser gpio4
|
|
0066 0000 //rl gpio5 output
|
|
0067 0007 //bypass ser gpio5
|
|
0073 0080
|
|
0074 0007
|
|
0079 000a
|
|
007b 0038
|
|
007c 0004
|
|
0081 0003
|
|
0082 0010
|
|
0084 0020
|
|
0086 0002
|
|
0087 0002
|
|
0088 0010
|
|
0089 0010
|
|
008b 0020
|
|
008d 0002
|
|
008e 0002
|
|
008f 0010
|
|
00d0 0040
|
|
00d8 0042
|
|
00d9 0004
|
|
0423 0002
|
|
0424 00ec
|
|
0425 0027
|
|
0429 000a
|
|
045d 0001
|
|
0529 000a
|
|
055d 0003
|
|
0090 0001
|
|
0091 0003
|
|
0426 0080
|
|
042d 0004
|
|
/* RL82 Pattern Gen Set
|
|
* Vertical Gray Scale Color Bar
|
|
*/
|
|
060A 00B0
|
|
060B 00FF
|
|
060C 00FF
|
|
060D 00FF
|
|
0644 0019
|
|
0645 0020
|
|
0646 001f
|
|
];
|
|
|
|
i2c7_bu18rl82_pinctrl: i2c7-bu18rl82-pinctrl {
|
|
compatible = "rohm,bu18rl82-pinctrl";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c7_bu18rl82_panel_pins>;
|
|
status = "disabled";
|
|
|
|
i2c7_bu18rl82_panel_pins: panel-pins {
|
|
lcd-bl-pwm {
|
|
pins = "BU18RL82_GPIO0";
|
|
function = "SER_GPIO0_TO_DES";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "SER_GPIO1_TO_DES";
|
|
};
|
|
|
|
lcd-rst {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-rst {
|
|
pins = "BU18RL82_GPIO3";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18RL82_GPIO4";
|
|
function = "DES_TO_SER_GPIO3";
|
|
};
|
|
|
|
lcd-otp-pin {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
};
|
|
|
|
i2c7_bu18rl82_gpio: i2c7-bu18rl82-gpio {
|
|
compatible = "rohm,bu18rl82-gpio";
|
|
status = "disabled";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c7_bu18rl82_pinctrl 0 241 8>;
|
|
};
|
|
};
|
|
|
|
i2c7_bu18rl82_bridge: i2c7-bu18rl82-bridge {
|
|
compatible = "rohm,bu18rl82-bridge";
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c7_bu18rl82_in_i2c7_bu18tl82: endpoint {
|
|
remote-endpoint = <&i2c7_bu18tl82_out_i2c7_bu18rl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c7_bu18rl82_out_panel1: endpoint {
|
|
remote-endpoint = <&panel1_in_i2c7_bu18rl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
lt7911d@2b {
|
|
compatible = "lontium,lt7911d-fb-notifier";
|
|
reg = <0x2b>;
|
|
reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
&i2c8 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c8m2_xfer>;
|
|
clock-frequency = <400000>;
|
|
|
|
i2c8_bu18tl82: i2c8-bu18tl82@10 {
|
|
compatible = "rohm,bu18tl82";
|
|
reg = <0x10>;
|
|
status = "disabled";
|
|
|
|
serdes-init-sequence = [
|
|
0013 001a //013h[3]1-lane1 enable 013h[3] 1-LVDS Receiver Port-A
|
|
0014 000a //014h[3]1-lane1 enable 014h[3] 1-LVDS Receiver Port-B
|
|
0021 0008
|
|
0023 0009
|
|
0024 0009
|
|
022b 0038
|
|
022c 0072
|
|
022d 0023 //VPLL=75MHZS
|
|
//022b 00d8
|
|
//022c 0089
|
|
//022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M
|
|
022e 0080
|
|
027c 0048
|
|
027d 0048 //i2c addr 0x48
|
|
0296 0004
|
|
0297 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane
|
|
//0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane
|
|
0018 00a5
|
|
0019 0069
|
|
0267 003d
|
|
0268 002c
|
|
0269 002c
|
|
026a 002c
|
|
026b 002c
|
|
0367 003d
|
|
0368 002c
|
|
0369 002c
|
|
036a 002c
|
|
036b 002c
|
|
0018 0000
|
|
0019 0000
|
|
002a 0018 //gpio0 input lcd_bl_pwm
|
|
002d 0018 //gpio1 input lcd_pwr_en
|
|
|
|
0030 0018 //gpio2 input lcd_rst
|
|
0033 0018 //gpio3 input tp_rst
|
|
0034 0005 //bypass des gpio3
|
|
0036 0000 //gpio4 output tp_int
|
|
0037 0006 //bypass des gpio4
|
|
|
|
02a7 0002
|
|
02a8 0003
|
|
02a9 0004
|
|
02aa 0005
|
|
02af 0002 //gpio0 1MHZ
|
|
0045 0080
|
|
0046 0007 //1920
|
|
004b 00d0
|
|
004c 0002 //720
|
|
004d 00d0
|
|
004e 0002 //720
|
|
0051 0080
|
|
0052 0007 //1920
|
|
0053 0064 //0053h[6]1:2 Rx ports CLLCH2_EN 53h[5] 1:2 Clock Tx lanes
|
|
024d 0061
|
|
0252 0005
|
|
0274 0030
|
|
0275 0020
|
|
0396 0004
|
|
0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane
|
|
//0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane
|
|
0061 0003 //CLLTX0 enable CLLTX1 enable
|
|
0060 0003 //CLLTX0/1 RGB data output Enable
|
|
/* TL82 Pattern Gen Set 1
|
|
* Horizontal Gray Scale 256 steps
|
|
*/
|
|
040A 0010
|
|
040B 0080
|
|
040C 0080
|
|
040D 0080
|
|
0444 0090 //h_blank=144
|
|
0446 00d2 //v_blank=210
|
|
];
|
|
|
|
i2c8_bu18tl82_pinctrl: i2c8-bu18tl82-pinctrl {
|
|
compatible = "rohm,bu18tl82-pinctrl";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c8_bu18tl82_panel_pins>;
|
|
status = "disabled";
|
|
|
|
i2c8_bu18tl82_panel_pins: panel-pins {
|
|
lcd-bl-pwm {
|
|
pins = "BU18TL82_GPIO0";
|
|
function = "SER_TO_DES_GPIO0";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18TL82_GPIO1";
|
|
function = "SER_TO_DES_GPIO1";
|
|
};
|
|
|
|
ser-irq {
|
|
pins = "BU18TL82_GPIO2";
|
|
function = "DES_GPIO2_TO_SER";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18TL82_GPIO3";
|
|
function = "DES_GPIO4_TO_SER";
|
|
};
|
|
};
|
|
|
|
|
|
i2c8_bu18tl82_gpio: i2c8-bu18tl82-gpio {
|
|
compatible = "rohm,bu18tl82-gpio";
|
|
status = "disabled";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c8_bu18tl82_pinctrl 0 250 8>;
|
|
};
|
|
};
|
|
|
|
i2c8_bu18tl82_bridge: i2c8-bu18tl82-bridge {
|
|
compatible = "rohm,bu18tl82-bridge";
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c8_bu18tl82_in_dp1: endpoint {
|
|
remote-endpoint = <&dp1_out_i2c8_bu18tl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c8_bu18tl82_out_i2c8_bu18rl82: endpoint {
|
|
remote-endpoint = <&i2c8_bu18rl82_in_i2c8_bu18tl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
i2c8_bu18rl82: i2c8-bu18rl82@30 {
|
|
compatible = "rohm,bu18rl82";
|
|
reg = <0x30>;
|
|
status = "disabled";
|
|
|
|
serdes-init-sequence = [
|
|
0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA
|
|
0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB
|
|
0013 0000
|
|
001d 0008
|
|
001f 0002 //LVDSTX0_REFSEL
|
|
0020 0002 //LVDSTX1_REFSEL
|
|
0031 0048
|
|
0032 0048 //i2c addr 0x48
|
|
0423 0000
|
|
0424 0000
|
|
0425 0020
|
|
0426 0080
|
|
0057 0000
|
|
0058 0002
|
|
0057 0000 //rl gpio0 output lcd_bl_pwm
|
|
0058 0002 //bypass ser gpio0
|
|
005a 0000 //rl gpio1 output lcd_pwr_en
|
|
005b 0003 //bypass ser gpio1
|
|
005d 0000 //rl gpio2 output lcd_rst
|
|
005e 0004 //bypass ser gpio2
|
|
0060 0000 //rl gpio3 output tp-rst
|
|
0061 0005 //bypass ser gpio3
|
|
0063 0018 //rl gpio4 input tp-int
|
|
0064 0006 //bypass ser gpio4
|
|
0066 0000 //rl gpio5 output
|
|
0067 0001 //set gpio5 high
|
|
|
|
0073 0080
|
|
0074 0007 //0x0780 = 1920
|
|
0075 0080
|
|
0076 0007 //0x0780 = 1920
|
|
0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane
|
|
007b 00d0
|
|
007c 0002 //0x02d0 = 720
|
|
007d 00d0
|
|
007e 0002 //0x02d0 = 720
|
|
0081 0003 //01---> Sync OFF
|
|
0082 0010 //Hsync=16clk
|
|
0084 001c //HBP=28clk
|
|
0086 0002 //Vsync=2lines
|
|
0087 0008 //VBP=8lines
|
|
0088 0000 //VSYNC_CHG=0CLK
|
|
0089 0010 //Hsync = 16?
|
|
008b 001c //HFP=28clk?
|
|
008d 0002 //Vsync=2lines?
|
|
008e 0008 //VFP=8line?
|
|
008f 0000 //VSYNC_CHG=0CLK?
|
|
00d0 0040 //[3]FixHtotalEN
|
|
00d8 00c0
|
|
00d9 0003 //DE=960
|
|
0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz
|
|
045d 0001
|
|
0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz
|
|
055d 0001
|
|
0091 0003
|
|
0090 0001
|
|
/* RL82 Pattern Gen Set
|
|
* Vertical Gray Scale Color Bar
|
|
*/
|
|
060A 00B0
|
|
060B 00FF
|
|
060C 00FF
|
|
060D 00FF
|
|
0644 0090
|
|
0646 00d2
|
|
];
|
|
|
|
i2c8_bu18rl82_pinctrl: i2c8-bu18rl82-pinctrl {
|
|
compatible = "rohm,bu18rl82-pinctrl";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c8_bu18rl82_panel_pins>;
|
|
status = "disabled";
|
|
|
|
i2c8_bu18rl82_panel_pins: panel-pins {
|
|
lcd-bl-pwm {
|
|
pins = "BU18RL82_GPIO0";
|
|
function = "SER_GPIO0_TO_DES";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "SER_GPIO1_TO_DES";
|
|
};
|
|
|
|
lcd-rst {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-rst {
|
|
pins = "BU18RL82_GPIO3";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18RL82_GPIO4";
|
|
function = "DES_TO_SER_GPIO3";
|
|
};
|
|
|
|
lcd-otp-pin {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
};
|
|
|
|
i2c8_bu18rl82_gpio: i2c8-bu18rl82-gpio {
|
|
compatible = "rohm,bu18rl82-gpio";
|
|
status = "disabled";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c8_bu18rl82_pinctrl 0 259 8>;
|
|
};
|
|
};
|
|
|
|
i2c8_bu18rl82_bridge: i2c8-bu18rl82-bridge {
|
|
compatible = "rohm,bu18rl82-bridge";
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c8_bu18rl82_in_i2c8_bu18tl82: endpoint {
|
|
remote-endpoint = <&i2c8_bu18tl82_out_i2c8_bu18rl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c8_bu18rl82_out_panel1: endpoint {
|
|
remote-endpoint = <&panel1_in_i2c8_bu18rl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
lt7911d@2b {
|
|
compatible = "lontium,lt7911d-fb-notifier";
|
|
reg = <0x2b>;
|
|
reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
&mipi_dcphy0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&mipi_dcphy1 {
|
|
status = "okay";
|
|
};
|
|
|
|
/* dsi0->serdes->lvds_panel */
|
|
&pwm0 {
|
|
status = "okay";
|
|
pinctrl-0 = <&pwm0m2_pins>;
|
|
};
|
|
|
|
/* dp0->serdes->lvds_panel */
|
|
&pwm10 {
|
|
pinctrl-0 = <&pwm10m2_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
/* edp1->serdes->lvds_panel */
|
|
&pwm11 {
|
|
pinctrl-0 = <&pwm11m3_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
/* edp0->serdes->lvds_panel */
|
|
&pwm7 {
|
|
pinctrl-0 = <&pwm7m0_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
/* dsi1->serdes->lvds_panel */
|
|
&pwm13 {
|
|
status = "okay";
|
|
pinctrl-0 = <&pwm13m1_pins>;
|
|
};
|
|
|
|
/* dp1->serdes->lvds_panel */
|
|
&pwm14 {
|
|
pinctrl-0 = <&pwm14m0_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
&route_dp0 {
|
|
status = "disabled";
|
|
connect = <&vp0_out_dp0>;
|
|
logo,uboot = "logo34.bmp";
|
|
logo,kernel = "logo34.bmp";
|
|
};
|
|
|
|
&route_dp1 {
|
|
status = "disabled";
|
|
connect = <&vp0_out_dp1>;
|
|
logo,uboot = "logo34.bmp";
|
|
logo,kernel = "logo34.bmp";
|
|
};
|
|
|
|
&route_dsi0 {
|
|
status = "disabled";
|
|
connect = <&vp2_out_dsi0>;
|
|
logo,uboot = "logo1.bmp";
|
|
logo,kernel = "logo1.bmp";
|
|
};
|
|
|
|
&route_dsi1 {
|
|
status = "disabled";
|
|
connect = <&vp3_out_dsi1>;
|
|
logo,uboot = "logo2.bmp";
|
|
logo,kernel = "logo2.bmp";
|
|
};
|
|
|
|
&route_edp0 {
|
|
status = "disabled";
|
|
connect = <&vp1_out_edp0>;
|
|
logo,uboot = "logo56.bmp";
|
|
logo,kernel = "logo56.bmp";
|
|
};
|
|
|
|
&route_edp1 {
|
|
status = "disabled";
|
|
connect = <&vp1_out_edp1>;
|
|
logo,uboot = "logo56.bmp";
|
|
logo,kernel = "logo56.bmp";
|
|
};
|
|
|
|
&usbdp_phy0 {
|
|
rockchip,dp-lane-mux = <0 1 2 3>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbdp_phy1 {
|
|
rockchip,dp-lane-mux = <0 1 2 3>;
|
|
status = "okay";
|
|
};
|
|
|
|
&vop {
|
|
assigned-clocks = <&cru PLL_V0PLL>;
|
|
assigned-clock-rates = <1152000000>;
|
|
};
|
|
|
|
&vp0 {
|
|
assigned-clocks = <&cru DCLK_VOP0_SRC>;
|
|
assigned-clock-parents = <&cru PLL_V0PLL>;
|
|
};
|
|
|
|
&vp1 {
|
|
assigned-clocks = <&cru DCLK_VOP1_SRC>;
|
|
assigned-clock-parents = <&cru PLL_GPLL>;
|
|
};
|
|
|
|
&vp2 {
|
|
assigned-clocks = <&cru DCLK_VOP2_SRC>;
|
|
assigned-clock-parents = <&cru PLL_V0PLL>;
|
|
};
|
|
|
|
&vp3 {
|
|
assigned-clocks = <&cru DCLK_VOP3>;
|
|
assigned-clock-parents = <&cru PLL_V0PLL>;
|
|
};
|