511 lines
13 KiB
Plaintext
511 lines
13 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*
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*/
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#include <dt-bindings/display/media-bus-format.h>
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/ {
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max96722_dcphy0_osc: max96722-dcphy0-oscillator {
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compatible = "fixed-clock";
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#clock-cells = <1>;
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clock-frequency = <25000000>;
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clock-output-names = "max96722-dcphy0-osc";
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};
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max96722_dcphy0_vcc1v2: max96722-dcphy0-vcc1v2 {
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compatible = "regulator-fixed";
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regulator-name = "max96722_dcphy0_vcc1v2";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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startup-delay-us = <850>;
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vin-supply = <&vcc5v0_sys>;
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};
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max96722_dcphy0_vcc1v8: max96722-dcphy0-vcc1v8 {
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compatible = "regulator-fixed";
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regulator-name = "max96722_dcphy0_vcc1v8";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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startup-delay-us = <200>;
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vin-supply = <&vcc_3v3_s3>;
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};
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max96722_dcphy0_pwdn_regulator: max96722-dcphy0-pwdn-regulator {
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compatible = "regulator-fixed";
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regulator-name = "max96722_dcphy0_pwdn";
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gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&max96722_dcphy0_pwdn>;
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enable-active-high;
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startup-delay-us = <10000>;
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off-on-delay-us = <5000>;
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vin-supply = <&max96722_dcphy0_vcc1v8>;
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};
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max96722_dcphy0_poc_regulator: max96722-dcphy0-poc-regulator {
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compatible = "regulator-fixed";
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regulator-name = "max96722_dcphy0_poc";
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gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <10000>;
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off-on-delay-us = <5000>;
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vin-supply = <&vcc12v_dcin>;
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};
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};
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&mipi_dcphy0 {
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status = "okay";
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};
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&csi2_dcphy0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_dcphy0_in_max96722: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&max96722_dcphy0_out>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidcphy0_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi0_csi2_input>;
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};
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};
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};
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};
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&i2c8 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c8m2_xfer>;
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max96722_dcphy0: max96722@29 {
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compatible = "maxim4c,max96722";
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status = "okay";
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reg = <0x29>;
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clock-names = "xvclk";
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clocks = <&max96722_dcphy0_osc 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&max96722_dcphy0_errb>, <&max96722_dcphy0_lock>;
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power-domains = <&power RK3588_PD_VI>;
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rockchip,grf = <&sys_grf>;
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vcc1v2-supply = <&max96722_dcphy0_vcc1v2>;
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vcc1v8-supply = <&max96722_dcphy0_vcc1v8>;
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pwdn-supply = <&max96722_dcphy0_pwdn_regulator>;
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lock-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "max96722";
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rockchip,camera-module-lens-name = "max96722";
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port {
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max96722_dcphy0_out: endpoint {
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remote-endpoint = <&mipi_dcphy0_in_max96722>;
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data-lanes = <1 2>;
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};
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};
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/* support mode config start */
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support-mode-config {
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status = "okay";
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bus-format = <MEDIA_BUS_FMT_UYVY8_2X8>;
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sensor-width = <1920>;
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sensor-height = <1080>;
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max-fps-numerator = <10000>;
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max-fps-denominator = <300000>;
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bpp = <16>;
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link-freq-idx = <24>;
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};
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/* support mode config end */
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/* serdes local device start */
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serdes-local-device {
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status = "okay";
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/* GMSL LINK config start */
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gmsl-links {
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status = "okay";
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link-vdd-ldo1-en = <1>;
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link-vdd-ldo2-en = <1>;
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// Link A: link-id = 0
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gmsl-link-config-0 {
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status = "okay";
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link-id = <0>; // Link ID: 0/1/2/3
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link-type = <1>;
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link-rx-rate = <0>;
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link-tx-rate = <0>;
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link-remote-cam = <&max96722_dcphy0_cam0>; // remote camera
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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14 D1 03 00 00 // VGAHiGain
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14 45 00 00 00 // Disable SSC
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];
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};
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};
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// Link B: link-id = 1
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gmsl-link-config-1 {
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status = "okay";
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link-id = <1>; // Link ID: 0/1/2/3
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link-type = <1>;
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link-rx-rate = <0>;
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link-tx-rate = <0>;
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link-remote-cam = <&max96722_dcphy0_cam1>; // remote camera
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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15 D1 03 00 00 // VGAHiGain
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15 45 00 00 00 // Disable SSC
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];
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};
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};
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};
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/* GMSL LINK config end */
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/* VIDEO PIPE config start */
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video-pipes {
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status = "okay";
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// Video Pipe 0
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video-pipe-config-0 {
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status = "okay";
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pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7
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pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <0>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Send YUV422, FS, and FE from Video Pipe 0 to Controller 0
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09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
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09 2D 00 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 0;
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// For the following MSB 2 bits = VC, LSB 6 bits = DT
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09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
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09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit
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09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start
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09 10 00 00 00 // DST1 VC = 0, DT = Frame Start
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09 11 01 00 00 // SRC2 VC = 0, DT = Frame End
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09 12 01 00 00 // DST2 VC = 0, DT = Frame End
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];
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};
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};
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// Video Pipe 1
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video-pipe-config-1 {
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status = "okay";
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pipe-id = <1>; // Video Pipe 1: pipe-id = 1
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pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <1>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Send YUV422, FS, and FE from Video Pipe 1 to Controller 0
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09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
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09 6D 00 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 0;
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// For the following MSB 2 bits = VC, LSB 6 bits = DT
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09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
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09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit
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09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start
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09 50 40 00 00 // DST1 VC = 1, DT = Frame Start
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09 51 01 00 00 // SRC2 VC = 0, DT = Frame End
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09 52 41 00 00 // DST2 VC = 1, DT = Frame End
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];
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};
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};
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};
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/* VIDEO PIPE config end */
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/* MIPI TXPHY config start */
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mipi-txphys {
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status = "okay";
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phy-mode = <1>;
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phy-force-clock-out = <1>;
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phy-force-clk0-en = <0>;
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phy-force-clk3-en = <0>;
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// MIPI TXPHY A: phy-id = 0
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mipi-txphy-config-0 {
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status = "okay";
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phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3
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phy-type = <0>;
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auto-deskew = <0x00>;
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data-lane-num = <2>;
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data-lane-map = <0x4>;
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vc-ext-en = <0>;
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};
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};
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/* MIPI TXPHY config end */
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/* local device extra init sequence */
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extra-init-sequence {
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status = "disabled";
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// common init sequence such as fsync / gpio and so on
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];
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};
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};
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/* serdes local device end */
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/* i2c-mux start */
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i2c-mux {
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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// Note: Serializer node defined before camera node
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max96722_dcphy0_ser0: max96717@41 {
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compatible = "maxim,ser,max96717";
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reg = <0x41>;
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ser-i2c-addr-def = <0x40>;
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ser-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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02 BE 00 00 01 // MFP0 GPIO_OUT = 0: MFP0 output is driven to 0
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03 02 10 00 00 // Improve CMU voltage performance to improve link robustness
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14 17 00 00 00 // RLMS17 = 0x00: disable AGC/DFE adaptation
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14 32 7f 00 00 // RLMS32 = 0x7F: change OSN loop mode
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03 F0 59 00 00 // REFGEN_PREDEF_FREQ_ALT = 1: Alternative table, REFGEN_PREDEF_FREQ = 0x1
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00 03 03 00 00 // RCLKSEL = 0x3: Reference PLL output
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00 06 B1 00 01 // RCLKEN = 1: RCLK output is enabled
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02 BE 10 00 00 // MFP0 GPIO_OUT = 1: MFP0 output is driven to 1
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02 BF 40 00 00 // MFP0 PULL_UPDN_SEL = 1: Pullup
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];
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};
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};
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max96722_dcphy0_cam0: ox03j10@31 {
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compatible = "maxim,ovti,ox03j10";
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reg = <0x31>;
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cam-i2c-addr-def = <0x36>;
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cam-remote-ser = <&max96722_dcphy0_ser0>; // remote serializer
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poc-supply = <&max96722_dcphy0_poc_regulator>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "ox03j10";
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rockchip,camera-module-lens-name = "ox03j10";
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/* port config start */
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port {
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max96722_dcphy0_cam0_out: endpoint {
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/* remote endpoint: rkcif_mipi_lvds_sditf */
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//remote-endpoint = <&mipi_lvds_sditf_in>;
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data-lanes = <1 2 3 4>;
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};
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};
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/* port config end */
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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// Note: Serializer node defined before camera node
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max96722_dcphy0_ser1: max96717@41 {
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compatible = "maxim,ser,max96717";
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reg = <0x41>;
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ser-i2c-addr-def = <0x40>;
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ser-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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02 BE 00 00 01 // MFP0 GPIO_OUT = 0: MFP0 output is driven to 0
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03 02 10 00 00 // Improve CMU voltage performance to improve link robustness
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14 17 00 00 00 // RLMS17 = 0x00: disable AGC/DFE adaptation
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14 32 7f 00 00 // RLMS32 = 0x7F: change OSN loop mode
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03 F0 59 00 00 // REFGEN_PREDEF_FREQ_ALT = 1: Alternative table, REFGEN_PREDEF_FREQ = 0x1
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00 03 03 00 00 // RCLKSEL = 0x3: Reference PLL output
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00 06 B1 00 01 // RCLKEN = 1: RCLK output is enabled
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02 BE 10 00 00 // MFP0 GPIO_OUT = 1: MFP0 output is driven to 1
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02 BF 40 00 00 // MFP0 PULL_UPDN_SEL = 1: Pullup
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];
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};
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};
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max96722_dcphy0_cam1: ox03j10@32 {
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compatible = "maxim,ovti,ox03j10";
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reg = <0x32>;
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cam-i2c-addr-def = <0x36>;
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cam-remote-ser = <&max96722_dcphy0_ser1>; // remote serializer
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poc-supply = <&max96722_dcphy0_poc_regulator>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "ox03j10";
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rockchip,camera-module-lens-name = "ox03j10";
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/* port config start */
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port {
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max96722_dcphy0_cam1_out: endpoint {
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/* remote endpoint: rkcif_mipi_lvds_sditf_vir1 */
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//remote-endpoint = <&mipi_lvds_sditf_vir1_in>;
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data-lanes = <1 2 3 4>;
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};
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};
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/* port config end */
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};
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};
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};
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/* i2c-mux end */
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};
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};
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&mipi0_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi0_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csidcphy0_out>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi0_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi0_in>;
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};
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};
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};
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};
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&rkcif_mipi_lvds {
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status = "okay";
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/* parameters for do cif reset detecting:
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* index0: monitor mode,
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0 for idle,
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1 for continue,
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2 for trigger,
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3 for hotplug (for nextchip)
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* index1: the frame id to start timer,
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min is 2
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* index2: frame num of monitoring cycle
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* index3: err time for keep monitoring
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after finding out err (ms)
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* index4: csi2 err reference val for resetting
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*/
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rockchip,cif-monitor = <3 2 1 1000 5>;
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port {
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cif_mipi0_in: endpoint {
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remote-endpoint = <&mipi0_csi2_output>;
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};
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};
|
|
};
|
|
|
|
&rkcif {
|
|
status = "okay";
|
|
rockchip,android-usb-camerahal-enable;
|
|
};
|
|
|
|
&rkcif_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&pinctrl {
|
|
max96722-dcphy0 {
|
|
max96722_dcphy0_pwdn: max96722-dcphy0-pwdn {
|
|
rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
|
|
};
|
|
|
|
max96722_dcphy0_errb: max96722-dcphy0-errb {
|
|
rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none_smt>;
|
|
};
|
|
|
|
max96722_dcphy0_lock: max96722-dcphy0-lock {
|
|
rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none_smt>;
|
|
};
|
|
};
|
|
};
|