1407 lines
27 KiB
Plaintext
1407 lines
27 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*
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*/
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/ {
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dp2lvds_backlight0: dp2lvds_backlight0 {
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compatible = "pwm-backlight";
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brightness-levels = <
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0 20 20 21 21 22 22 23
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23 24 24 25 25 26 26 27
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27 28 28 29 29 30 30 31
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31 32 32 33 33 34 34 35
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35 36 36 37 37 38 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255
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>;
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default-brightness-level = <200>;
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};
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edp2lvds_backlight0: edp2lvds_backlight0 {
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compatible = "pwm-backlight";
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brightness-levels = <
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0 20 20 21 21 22 22 23
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23 24 24 25 25 26 26 27
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27 28 28 29 29 30 30 31
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31 32 32 33 33 34 34 35
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35 36 36 37 37 38 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255
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>;
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default-brightness-level = <200>;
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};
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dsi2lvds_panel0 {
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compatible = "simple-panel";
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backlight = <&backlight>;
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display-timings {
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native-mode = <&dsi2lvds0>;
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dsi2lvds0: timing0 {
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clock-frequency = <115000000>;//115000000/105573600
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hactive = <1920>;
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vactive = <720>;
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hfront-porch = <56>;
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hsync-len = <32>;
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hback-porch = <56>;
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vfront-porch = <200>;
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vsync-len = <2>;
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vback-porch = <8>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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panel0_in_i2c8_bu18rl82: endpoint {
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remote-endpoint = <&i2c8_bu18rl82_out_panel0>;
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};
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};
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};
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};
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dp2lvds_panel0 {
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compatible = "simple-panel";
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backlight = <&dp2lvds_backlight0>;
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status = "okay";
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panel-timing {
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clock-frequency = <148500000>;
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hactive = <1920>;
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vactive = <1080>;
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hfront-porch = <140>;
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hsync-len = <40>;
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hback-porch = <100>;
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vfront-porch = <15>;
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vsync-len = <20>;
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vback-porch = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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port {
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panel0_in_i2c5_bu18rl82: endpoint {
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remote-endpoint = <&i2c5_bu18rl82_out_panel0>;
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};
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};
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};
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edp2lvds_panel0 {
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compatible = "simple-panel";
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backlight = <&edp2lvds_backlight0>;
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status = "okay";
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panel-timing {
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clock-frequency = <115000000>;//115000000/105573600
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hactive = <1920>;
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vactive = <720>;
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hfront-porch = <56>;
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hsync-len = <32>;
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hback-porch = <56>;
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vfront-porch = <200>;
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vsync-len = <2>;
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vback-porch = <8>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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port {
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panel0_in_i2c2_bu18rl82: endpoint {
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remote-endpoint = <&i2c2_bu18rl82_out_panel0>;
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};
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};
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};
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};
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&backlight {
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pwms = <&pwm1_6ch_1 0 25000 0>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&i2c8_serdes_pins>;
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//enable-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&combphy0_ps {
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status = "okay";
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};
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&combphy1_psu {
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status = "okay";
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};
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&dp {
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//split-mode;
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force-hpd;
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status = "okay";
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};
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&dp0 {
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status = "okay";
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ports {
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port@1 {
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reg = <1>;
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dp_out_i2c5_bu18tl82: endpoint {
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remote-endpoint = <&i2c5_bu18tl82_in_dp>;
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};
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};
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};
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};
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&dp0_in_vp0 {
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status = "disabled";
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};
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&dp0_in_vp1 {
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status = "disabled";
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};
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&dp0_in_vp2 {
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status = "okay";
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};
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&dp2lvds_backlight0 {
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pwms = <&pwm2_8ch_0 0 25000 0>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&i2c5_serdes_pins>;
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//enable-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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/*
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* mipi_dcphy needs to be enabled
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* when dsi is enabled
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*/
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&dsi {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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dsi_out_i2c8_bu18tl82: endpoint {
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remote-endpoint = <&i2c8_bu18tl82_in_dsi>;
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};
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};
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};
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};
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&dsi_in_vp0 {
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status = "disabled";
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};
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&dsi_in_vp1 {
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status = "okay";
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};
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&dsi_in_vp2 {
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status = "disabled";
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};
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&edp {
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//split-mode;
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force-hpd;
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status = "okay";
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ports {
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port@1 {
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reg = <1>;
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edp_out_i2c2_bu18tl82: endpoint {
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remote-endpoint = <&i2c2_bu18tl82_in_edp>;
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};
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};
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};
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};
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&edp_in_vp0 {
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status = "okay";
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};
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&edp_in_vp1 {
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status = "disabled";
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};
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&edp_in_vp2 {
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status = "disabled";
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};
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&edp2lvds_backlight0 {
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pwms = <&pwm2_8ch_5 0 25000 0>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&i2c2_serdes_pins>;
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//enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&hdmi {
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status = "disabled";
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};
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&hdptxphy {
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status = "okay";
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};
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&hdptxphy_hdmi {
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status = "disabled";
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};
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&i2c8 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c8m2_xfer>;
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clock-frequency = <400000>;
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i2c8_bu18tl82: i2c8-bu18tl82@10 {
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compatible = "rohm,bu18tl82";
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reg = <0x10>;
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sel-mipi;
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status = "okay";
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serdes-init-sequence = [
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0013 0019
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0014 0008 //014h[3]-lane1 enable
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0021 0008
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0023 0009
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0024 0009
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022b 0038
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022c 0072
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022d 0023 //VPLL=75MHZS
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//022b 00d8
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//022c 0089
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//022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M
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022e 0080
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027c 0048
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027d 0048 //i2c addr 0x48
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0296 0004
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0297 0009 //CLLTX0_PLL_GAIN 297h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane
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//0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane
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0018 00a5
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0019 0069
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0267 003d
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0268 002c
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0269 002c
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026a 002c
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026b 002c
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0367 003d
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0368 002c
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0369 002c
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036a 002c
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036b 002c
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0018 0000
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0019 0000
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//002a 0018 //gpio0 input lcd_bl_pwm
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//002d 0018 //gpio1 input lcd_pwr_en
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//0030 0018 //gpio2 input lcd_rst
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//0033 0018 //gpio3 input tp_rst
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//0034 0005 //bypass des gpio3
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//0036 0000 //gpio4 output tp_int
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//0037 0006 //bypass des gpio4
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02a7 0002
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02a8 0003
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02a9 0004
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02aa 0005
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02af 0002 //gpio0 1MHZ
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0045 0080
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0046 0007 //1920
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004b 00d0
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004c 0002 //720
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004d 00d0
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004e 0002 //720
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0051 0080
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0052 0007 //1920
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0053 0024 //CLLCH2_EN 53h[5] 0:1 Clock Tx lane/1:2 Clock Tx lanes
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0054 0080
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024d 0061
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0252 0005
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0274 0030 //I2C slave address of BU18RL82 for accessing via BU18TL82
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0275 0020
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0396 0004
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0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.31 Gbps/lane
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//0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.60 Gbps/lane
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0061 0003 //CLLTX0 enable CLLTX1 enable
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0060 0003 //CLLTX0/1 RGB data output Enable
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/* TL82 Pattern Gen Set 1
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* Horizontal Gray Scale 256 steps
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*/
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040A 0010
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040B 0080
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040C 0080
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040D 0080
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0444 0090
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0446 00d2
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];
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i2c8_bu18tl82_pinctrl: i2c8-bu18tl82-pinctrl {
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compatible = "rohm,bu18tl82-pinctrl";
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pinctrl-names = "default","sleep";
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pinctrl-0 = <&i2c8_bu18tl82_panel_pins>;
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pinctrl-1 = <&i2c8_bu18tl82_panel_pins>;
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status = "okay";
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i2c8_bu18tl82_panel_pins: panel-pins {
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lcd-bl-pwm {
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pins = "BU18TL82_GPIO0";
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function = "SER_TO_DES_GPIO0";
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};
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lcd-pwr-en {
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pins = "BU18TL82_GPIO1";
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function = "SER_TO_DES_GPIO1";
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};
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ser-irq {
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pins = "BU18TL82_GPIO2";
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function = "DES_GPIO2_TO_SER";
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};
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tp-int {
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pins = "BU18TL82_GPIO3";
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function = "DES_GPIO4_TO_SER";
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};
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};
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i2c8_bu18tl82_gpio: i2c8-bu18tl82-gpio {
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compatible = "rohm,bu18tl82-gpio";
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status = "okay";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&i2c8_bu18tl82_pinctrl 0 160 8>;
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};
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};
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i2c8_bu18tl82_bridge: i2c8-bu18tl82-bridge {
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compatible = "rohm,bu18tl82-bridge";
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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i2c8_bu18tl82_in_dsi: endpoint {
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remote-endpoint = <&dsi_out_i2c8_bu18tl82>;
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};
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};
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port@1 {
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reg = <1>;
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i2c8_bu18tl82_out_i2c8_bu18rl82: endpoint {
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remote-endpoint = <&i2c8_bu18rl82_in_i2c8_bu18tl82>;
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};
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};
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};
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};
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};
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i2c8_bu18rl82: i2c8-bu18rl82@30 {
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compatible = "rohm,bu18rl82";
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reg = <0x30>;
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status = "okay";
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serdes-init-sequence = [
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0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA
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0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB
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0013 0000
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001d 0008
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001f 0002 //LVDSTX0_REFSEL
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0020 0002 //LVDSTX1_REFSEL
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0031 0048
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0032 0048 //i2c addr 0x48
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0423 0000
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0424 0000
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0425 0020
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0426 0080
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0057 0000 //rl gpio0 output lcd_bl_pwm
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0058 0000 //bypass ser gpio0
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005a 0000 //rl gpio1 output lcd_pwr_en
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005b 0000 //bypass ser gpio1
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005d 0000 //rl gpio2 output lcd_rst
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005e 0000 //bypass ser gpio2
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0060 0000 //rl gpio3 output tp-rst
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0061 0000 //bypass ser gpio3
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0063 0018 //rl gpio4 input tp-int
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0064 0006 //bypass ser gpio4
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0066 0000 //rl gpio5 output
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0067 0000 //set gpio5 high
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0073 0080
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0074 0007 //0x0780 = 1920
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0075 0080
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0076 0007 //0x0780 = 1920
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0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane
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007b 00d0
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007c 0002 //0x02d0 = 720
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007d 00d0
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007e 0002 //0x02d0 = 720
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0081 0003 //01---> Sync OFF
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0082 0010 //Hsync=16clk
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0084 001c //HBP=28clk
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0086 0002 //Vsync=2lines
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0087 0008 //VBP=8lines
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0088 0000 //VSYNC_CHG=0CLK
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0089 0010 //Hsync = 16?
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008b 001c //HFP=28clk?
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008d 0002 //Vsync=2lines?
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008e 0008 //VFP=8line?
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008f 0000 //VSYNC_CHG=0CLK?
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00d0 0040 //[3]FixHtotalEN
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00d8 00c0
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00d9 0003 //DE=960
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0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz
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045d 0001
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0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz
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055d 0001
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0091 0003
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0090 0001
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/* RL82 Pattern Gen Set
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* Vertical Gray Scale Color Bar
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*/
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060A 00B0
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060B 00FF
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060C 00FF
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060D 00FF
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0644 0090
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0646 00d2
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];
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i2c8_bu18rl82_pinctrl: i2c8-bu18rl82-pinctrl {
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compatible = "rohm,bu18rl82-pinctrl";
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pinctrl-names = "default","init","sleep";
|
|
pinctrl-0 = <&i2c8_bu18rl82_panel_pins>;
|
|
pinctrl-1 = <&i2c8_bu18rl82_panel_pins>;
|
|
pinctrl-2 = <&i2c8_bu18rl82_panel_sleep_pins>;
|
|
status = "okay";
|
|
|
|
i2c8_bu18rl82_panel_pins: panel-pins {
|
|
lcd-otp-pin {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
tp-rst {
|
|
pins = "BU18RL82_GPIO3";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
lcd-rst {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
tp-int {
|
|
pins = "BU18RL82_GPIO4";
|
|
function = "DES_TO_SER_GPIO3";
|
|
};
|
|
40ms-delay {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "DELAY_40MS";
|
|
};
|
|
lcd-pwr-en {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
lcd-bl-pwm {
|
|
pins = "BU18RL82_GPIO0";
|
|
function = "SER_GPIO0_TO_DES";
|
|
};
|
|
};
|
|
|
|
i2c8_bu18rl82_panel_sleep_pins: panel-sleep-pins {
|
|
lcd-rst-sleep {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
tp-rst-sleep {
|
|
pins = "BU18RL82_GPIO3";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
lcd-otp-pin-sleep {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
};
|
|
|
|
i2c8_bu18rl82_gpio: i2c8-bu18rl82-gpio {
|
|
compatible = "rohm,bu18rl82-gpio";
|
|
status = "okay";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c8_bu18rl82_pinctrl 0 169 8>;
|
|
};
|
|
};
|
|
|
|
i2c8_bu18rl82_bridge: i2c8-bu18rl82-bridge {
|
|
compatible = "rohm,bu18rl82-bridge";
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c8_bu18rl82_in_i2c8_bu18tl82: endpoint {
|
|
remote-endpoint = <&i2c8_bu18tl82_out_i2c8_bu18rl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c8_bu18rl82_out_panel0: endpoint {
|
|
remote-endpoint = <&panel0_in_i2c8_bu18rl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
himax@48 {
|
|
compatible = "himax,hxcommon";
|
|
reg = <0x48>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&touch_gpio_dsi>;
|
|
pinctrl-1 = <&touch_gpio_dsi>;
|
|
himax,location = "himax-touch-dsi";
|
|
himax,irq-gpio = <&gpio3 RK_PA3 IRQ_TYPE_EDGE_FALLING>;
|
|
himax,rst-gpio = <&i2c8_bu18rl82_gpio 3 GPIO_ACTIVE_LOW>;
|
|
himax,panel-coords = <0 1920 0 720>;
|
|
himax,display-coords = <0 1920 0 720>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&i2c5 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c5m3_xfer>;
|
|
clock-frequency = <400000>;
|
|
status = "okay";
|
|
|
|
i2c5_bu18tl82: i2c5-bu18tl82@10 {
|
|
compatible = "rohm,bu18tl82";
|
|
reg = <0x10>;
|
|
status = "okay";
|
|
|
|
serdes-init-sequence = [
|
|
0013 001a
|
|
0014 000a
|
|
0021 0008
|
|
0023 0009
|
|
0024 0009
|
|
//002a 0018 //gpio0 input lcd_bl_pwm
|
|
//002d 0018 //gpio1 input lcd_pwr_en
|
|
|
|
//0030 0018 //gpio2 input lcd_rst
|
|
//0033 0000 //gpio3 output tp_int
|
|
//0034 0005 //bypass des gpio3
|
|
//0036 0018 //gpio4 input tp_rst
|
|
//0037 0006 //bypass des gpio4
|
|
027c 0041
|
|
027d 0041
|
|
0045 0080
|
|
0046 0007
|
|
004b 0038
|
|
004c 0004
|
|
0053 0064
|
|
022b 0062
|
|
022c 0027
|
|
022d 002e
|
|
0274 0030
|
|
0275 0020
|
|
0296 0004
|
|
0297 000d
|
|
02af 0002 //gpio0 1MHZ
|
|
02b2 00c8
|
|
02b4 0001
|
|
02b8 00ff
|
|
02b9 000f
|
|
02ba 00ff
|
|
02bb 000f
|
|
02be 00ff
|
|
02bf 001f
|
|
02c2 00ff
|
|
02c3 001f
|
|
0396 0004
|
|
0397 000d
|
|
03b2 00c8
|
|
03b4 0001
|
|
03b8 00ff
|
|
03b9 000f
|
|
03ba 00ff
|
|
03bb 000f
|
|
03be 00ff
|
|
03bf 001f
|
|
03c2 00ff
|
|
03c3 001f
|
|
0060 0001
|
|
0061 0003
|
|
022e 0080
|
|
032e 0080
|
|
/* TL82 Pattern Gen Set 1
|
|
* Horizontal Gray Scale 256 steps
|
|
*/
|
|
040A 0010
|
|
040B 0080
|
|
040C 0080
|
|
040D 0080
|
|
0444 0019
|
|
0445 0020
|
|
0446 001f
|
|
|
|
];
|
|
|
|
i2c5_bu18tl82_pinctrl: i2c5-bu18tl82-pinctrl {
|
|
compatible = "rohm,bu18tl82-pinctrl";
|
|
pinctrl-names = "default","sleep";
|
|
pinctrl-0 = <&i2c5_bu18tl82_panel_pins>;
|
|
pinctrl-1 = <&i2c5_bu18tl82_panel_pins>;
|
|
status = "okay";
|
|
|
|
i2c5_bu18tl82_panel_pins: panel-pins {
|
|
lcd-bl-pwm {
|
|
pins = "BU18TL82_GPIO0";
|
|
function = "SER_TO_DES_GPIO0";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18TL82_GPIO1";
|
|
function = "SER_TO_DES_GPIO1";
|
|
};
|
|
|
|
ser-irq {
|
|
pins = "BU18TL82_GPIO2";
|
|
function = "DES_GPIO2_TO_SER";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18TL82_GPIO3";
|
|
function = "DES_GPIO3_TO_SER";
|
|
};
|
|
|
|
};
|
|
|
|
i2c5_bu18tl82_gpio: i2c5-bu18tl82-gpio {
|
|
compatible = "rohm,bu18tl82-gpio";
|
|
status = "okay";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c5_bu18tl82_pinctrl 0 178 8>;
|
|
};
|
|
};
|
|
|
|
i2c5_bu18tl82_bridge: i2c5-bu18tl82-bridge {
|
|
compatible = "rohm,bu18tl82-bridge";
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c5_bu18tl82_in_dp: endpoint {
|
|
remote-endpoint = <&dp_out_i2c5_bu18tl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c5_bu18tl82_out_i2c5_bu18rl82: endpoint {
|
|
remote-endpoint = <&i2c5_bu18rl82_in_i2c5_bu18tl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
i2c5_bu18rl82: i2c5-bu18rl82@30 {
|
|
compatible = "rohm,bu18rl82";
|
|
reg = <0x30>;
|
|
status = "okay";
|
|
|
|
serdes-init-sequence = [
|
|
0011 000b
|
|
0012 0003
|
|
0013 0001
|
|
001d 0008
|
|
001f 0002
|
|
0020 0002
|
|
0031 0041 //i2c addr 0x41
|
|
0032 0041 //i2c addr 0x41
|
|
0057 0000 //rl gpio0 output lcd_bl_pwm
|
|
0058 0000 //set gpio0 low
|
|
005a 0000 //rl gpio1 output lcd_pwr_en
|
|
005b 0000 //set gpio1 low
|
|
005d 0000 //rl gpio2 output lcd_rst
|
|
005e 0000 //set gpio2 low
|
|
0060 0000 //rl gpio3 output tp-rst
|
|
0061 0000 //set gpio3 low
|
|
0063 0018 //rl gpio4 input tp-int
|
|
0064 0006 //bypass ser gpio4
|
|
0066 0000 //rl gpio5 output
|
|
0067 0000 //set gpio5 low
|
|
0073 0080
|
|
0074 0007
|
|
0079 000a
|
|
007b 0038
|
|
007c 0004
|
|
0081 0003
|
|
0082 0010
|
|
0084 0020
|
|
0086 0002
|
|
0087 0002
|
|
0088 0010
|
|
0089 0010
|
|
008b 0020
|
|
008d 0002
|
|
008e 0002
|
|
008f 0010
|
|
00d0 0040
|
|
00d8 0042
|
|
00d9 0004
|
|
0423 0002
|
|
0424 00ec
|
|
0425 0027
|
|
0429 000a
|
|
045d 0001
|
|
0529 000a
|
|
055d 0003
|
|
0090 0001
|
|
0091 0003
|
|
0426 0080
|
|
042d 0004
|
|
/* RL82 Pattern Gen Set
|
|
* Vertical Gray Scale Color Bar
|
|
*/
|
|
060A 00B0
|
|
060B 00FF
|
|
060C 00FF
|
|
060D 00FF
|
|
0644 0019
|
|
0645 0020
|
|
0646 001f
|
|
|
|
];
|
|
|
|
i2c5_bu18rl82_pinctrl: i2c5-bu18rl82-pinctrl {
|
|
compatible = "rohm,bu18rl82-pinctrl";
|
|
pinctrl-names = "default","init","sleep";
|
|
pinctrl-0 = <&i2c5_bu18rl82_panel_pins>;
|
|
pinctrl-1 = <&i2c5_bu18rl82_panel_pins>;
|
|
pinctrl-2 = <&i2c5_bu18rl82_panel_sleep_pins>;
|
|
status = "okay";
|
|
|
|
i2c5_bu18rl82_panel_pins: panel-pins {
|
|
lcd-otp-pin {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-rst {
|
|
pins = "BU18RL82_GPIO3";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
lcd-rst {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18RL82_GPIO4";
|
|
function = "DES_TO_SER_GPIO3";
|
|
};
|
|
|
|
40ms-delay {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "DELAY_40MS";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
lcd-bl-pwm {
|
|
pins = "BU18RL82_GPIO0";
|
|
function = "SER_GPIO0_TO_DES";
|
|
};
|
|
};
|
|
|
|
i2c5_bu18rl82_panel_sleep_pins: panel-sleep-pins {
|
|
lcd-rst-sleep {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
|
|
tp-rst-sleep {
|
|
pins = "BU18RL82_GPIO4";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
|
|
lcd-otp-pin-sleep {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
};
|
|
|
|
i2c5_bu18rl82_gpio: i2c5-bu18rl82-gpio {
|
|
compatible = "rohm,bu18rl82-gpio";
|
|
status = "okay";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c5_bu18rl82_pinctrl 0 187 8>;
|
|
};
|
|
};
|
|
|
|
i2c5_bu18rl82_bridge: i2c5-bu18rl82-bridge {
|
|
compatible = "rohm,bu18rl82-bridge";
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c5_bu18rl82_in_i2c5_bu18tl82: endpoint {
|
|
remote-endpoint = <&i2c5_bu18tl82_out_i2c5_bu18rl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c5_bu18rl82_out_panel0: endpoint {
|
|
remote-endpoint = <&panel0_in_i2c5_bu18rl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ilitek@41 {
|
|
compatible = "ilitek,ili251x";
|
|
reg = <0x41>;
|
|
interrupt-parent = <&gpio2>;
|
|
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&touch_gpio_dp>;
|
|
//reset-gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_LOW>;
|
|
ilitek,name = "ilitek_i2c";
|
|
status = "okay";
|
|
};
|
|
|
|
lt7911d@2b {
|
|
compatible = "lontium,lt7911d-fb-notifier";
|
|
reg = <0x2b>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&i2c2 {
|
|
pinctrl-0 = <&i2c2m3_xfer>;
|
|
clock-frequency = <400000>;
|
|
status = "okay";
|
|
|
|
i2c2_bu18tl82: i2c2-bu18tl82@10 {
|
|
compatible = "rohm,bu18tl82";
|
|
reg = <0x10>;
|
|
status = "okay";
|
|
|
|
serdes-init-sequence = [
|
|
0013 001a
|
|
0014 000a
|
|
0021 0008
|
|
0023 0009
|
|
0024 0009
|
|
//002a 0018 //gpio0 input lcd_bl_pwm
|
|
//002d 0018 //gpio1 input lcd_pwr_en
|
|
|
|
//0030 0018 //gpio2 input lcd_rst
|
|
//0033 0000 //gpio3 output tp_int
|
|
//0034 0005 //bypass des gpio3
|
|
//0036 0018 //gpio4 input tp_rst
|
|
//0037 0006 //bypass des gpio4
|
|
027c 0041
|
|
027d 0041
|
|
0045 0080
|
|
0046 0007
|
|
004b 0038
|
|
004c 0004
|
|
0053 0064
|
|
022b 0062
|
|
022c 0027
|
|
022d 002e
|
|
0274 0030
|
|
0275 0020
|
|
0296 0004
|
|
0297 000d
|
|
02af 0002 //gpio0 1MHZ
|
|
02b2 00c8
|
|
02b4 0001
|
|
02b8 00ff
|
|
02b9 000f
|
|
02ba 00ff
|
|
02bb 000f
|
|
02be 00ff
|
|
02bf 001f
|
|
02c2 00ff
|
|
02c3 001f
|
|
0396 0004
|
|
0397 000d
|
|
03b2 00c8
|
|
03b4 0001
|
|
03b8 00ff
|
|
03b9 000f
|
|
03ba 00ff
|
|
03bb 000f
|
|
03be 00ff
|
|
03bf 001f
|
|
03c2 00ff
|
|
03c3 001f
|
|
0060 0001
|
|
0061 0003
|
|
022e 0080
|
|
032e 0080
|
|
/* TL82 Pattern Gen Set 1
|
|
* Horizontal Gray Scale 256 steps
|
|
*/
|
|
040A 0010
|
|
040B 0080
|
|
040C 0080
|
|
040D 0080
|
|
0444 0019
|
|
0445 0020
|
|
0446 001f
|
|
];
|
|
|
|
i2c2_bu18tl82_pinctrl: i2c2-bu18tl82-pinctrl {
|
|
compatible = "rohm,bu18tl82-pinctrl";
|
|
pinctrl-names = "default","sleep";
|
|
pinctrl-0 = <&i2c2_bu18tl82_panel_pins>;
|
|
pinctrl-1 = <&i2c2_bu18tl82_panel_pins>;
|
|
status = "okay";
|
|
|
|
i2c2_bu18tl82_panel_pins: panel-pins {
|
|
lcd-bl-pwm {
|
|
pins = "BU18TL82_GPIO0";
|
|
function = "SER_TO_DES_GPIO0";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18TL82_GPIO1";
|
|
function = "SER_TO_DES_GPIO1";
|
|
};
|
|
|
|
ser-irq {
|
|
pins = "BU18TL82_GPIO2";
|
|
function = "DES_GPIO2_TO_SER";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18TL82_GPIO3";
|
|
function = "DES_GPIO3_TO_SER";
|
|
};
|
|
};
|
|
|
|
|
|
i2c2_bu18tl82_gpio: i2c2-bu18tl82-gpio {
|
|
compatible = "rohm,bu18tl82-gpio";
|
|
status = "okay";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c2_bu18tl82_pinctrl 0 196 8>;
|
|
};
|
|
};
|
|
|
|
i2c2_bu18tl82_bridge: i2c2-bu18tl82-bridge {
|
|
compatible = "rohm,bu18tl82-bridge";
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c2_bu18tl82_in_edp: endpoint {
|
|
remote-endpoint = <&edp_out_i2c2_bu18tl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c2_bu18tl82_out_i2c2_bu18rl82: endpoint {
|
|
remote-endpoint = <&i2c2_bu18rl82_in_i2c2_bu18tl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
i2c2_bu18rl82: i2c2-bu18rl82@30 {
|
|
compatible = "rohm,bu18rl82";
|
|
reg = <0x30>;
|
|
status = "okay";
|
|
|
|
serdes-init-sequence = [
|
|
0011 000b
|
|
0012 0003
|
|
0013 0001
|
|
001d 0008
|
|
001f 0002
|
|
0020 0002
|
|
0031 0041 //i2c addr 0x41
|
|
0032 0041 //i2c addr 0x41
|
|
0057 0000 //rl gpio0 output lcd_bl_pwm
|
|
0058 0000 //set gpio0 low
|
|
005a 0000 //rl gpio1 output lcd_pwr_en
|
|
005b 0000 //set gpio1 low
|
|
005d 0000 //rl gpio2 output lcd_rst
|
|
005e 0000 //set gpio2 low
|
|
0060 0000 //rl gpio3 output tp-rst
|
|
0061 0000 //set gpio3 low
|
|
0063 0018 //rl gpio4 input tp-int
|
|
0064 0006 //bypass ser gpio4
|
|
0066 0000 //rl gpio5 output
|
|
0067 0000 //set gpio5 low
|
|
0073 0080
|
|
0074 0007
|
|
0079 000a
|
|
007b 0038
|
|
007c 0004
|
|
0081 0003
|
|
0082 0010
|
|
0084 0020
|
|
0086 0002
|
|
0087 0002
|
|
0088 0010
|
|
0089 0010
|
|
008b 0020
|
|
008d 0002
|
|
008e 0002
|
|
008f 0010
|
|
00d0 0040
|
|
00d8 0042
|
|
00d9 0004
|
|
0423 0002
|
|
0424 00ec
|
|
0425 0027
|
|
0429 000a
|
|
045d 0001
|
|
0529 000a
|
|
055d 0003
|
|
0090 0001
|
|
0091 0003
|
|
0426 0080
|
|
042d 0004
|
|
/* RL82 Pattern Gen Set
|
|
* Vertical Gray Scale Color Bar
|
|
*/
|
|
060A 00B0
|
|
060B 00FF
|
|
060C 00FF
|
|
060D 00FF
|
|
0644 0019
|
|
0645 0020
|
|
0646 001f
|
|
];
|
|
|
|
i2c2_bu18rl82_pinctrl: i2c2-bu18rl82-pinctrl {
|
|
compatible = "rohm,bu18rl82-pinctrl";
|
|
pinctrl-names = "default","init","sleep";
|
|
pinctrl-0 = <&i2c2_bu18rl82_panel_pins>;
|
|
pinctrl-1 = <&i2c2_bu18rl82_panel_pins>;
|
|
pinctrl-2 = <&i2c2_bu18rl82_panel_sleep_pins>;
|
|
status = "okay";
|
|
|
|
i2c2_bu18rl82_panel_pins: panel-pins {
|
|
lcd-otp-pin {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-rst {
|
|
pins = "BU18RL82_GPIO3";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
lcd-rst {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
tp-int {
|
|
pins = "BU18RL82_GPIO4";
|
|
function = "DES_TO_SER_GPIO3";
|
|
};
|
|
|
|
40ms-delay {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "DELAY_40MS";
|
|
};
|
|
|
|
lcd-pwr-en {
|
|
pins = "BU18RL82_GPIO1";
|
|
function = "DES_GPIO_OUTPUT_HIGH";
|
|
};
|
|
|
|
lcd-bl-pwm {
|
|
pins = "BU18RL82_GPIO0";
|
|
function = "SER_GPIO0_TO_DES";
|
|
};
|
|
};
|
|
|
|
i2c2_bu18rl82_panel_sleep_pins: panel-sleep-pins {
|
|
lcd-rst-sleep {
|
|
pins = "BU18RL82_GPIO2";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
|
|
tp-rst-sleep {
|
|
pins = "BU18RL82_GPIO4";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
|
|
lcd-otp-pin-sleep {
|
|
pins = "BU18RL82_GPIO5";
|
|
function = "DES_GPIO_OUTPUT_LOW";
|
|
};
|
|
};
|
|
|
|
i2c2_bu18rl82_gpio: i2c2-bu18rl82-gpio {
|
|
compatible = "rohm,bu18rl82-gpio";
|
|
status = "okay";
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&i2c2_bu18rl82_pinctrl 0 205 8>;
|
|
};
|
|
};
|
|
|
|
i2c2_bu18rl82_bridge: i2c2-bu18rl82-bridge {
|
|
compatible = "rohm,bu18rl82-bridge";
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
i2c2_bu18rl82_in_i2c2_bu18tl82: endpoint {
|
|
remote-endpoint = <&i2c2_bu18tl82_out_i2c2_bu18rl82>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
i2c2_bu18rl82_out_panel0: endpoint {
|
|
remote-endpoint = <&panel0_in_i2c2_bu18rl82>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
himax@48 {
|
|
compatible = "himax,hxcommon";
|
|
reg = <0x48>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&touch_gpio_edp>;
|
|
pinctrl-1 = <&touch_gpio_edp>;
|
|
himax,location = "himax-touch-edp";
|
|
himax,irq-gpio = <&gpio4 RK_PC1 IRQ_TYPE_EDGE_FALLING>;
|
|
himax,rst-gpio = <&i2c8_bu18rl82_gpio 3 GPIO_ACTIVE_LOW>;
|
|
himax,panel-coords = <0 1920 0 720>;
|
|
himax,display-coords = <0 1920 0 720>;
|
|
status = "okay";
|
|
};
|
|
|
|
lt7911d@2b {
|
|
compatible = "lontium,lt7911d-fb-notifier";
|
|
reg = <0x2b>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&mipidcphy0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&pinctrl {
|
|
serdes {
|
|
i2c2_serdes_pins: i2c2-serdes-pins {
|
|
rockchip,pins =
|
|
<2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
};
|
|
|
|
i2c5_serdes_pins: i2c5-serdes-pins {
|
|
rockchip,pins =
|
|
<2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
};
|
|
|
|
i2c8_serdes_pins: i2c8-serdes-pins {
|
|
rockchip,pins =
|
|
<2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/* dsi->serdes->lvds_panel */
|
|
&pwm1_6ch_1 {
|
|
status = "okay";
|
|
pinctrl-0 = <&pwm1m0_ch1>;
|
|
};
|
|
|
|
/* dp->serdes->lvds_panel */
|
|
&pwm2_8ch_0 {
|
|
pinctrl-0 = <&pwm2m2_ch0>;
|
|
status = "okay";
|
|
};
|
|
|
|
|
|
/* edp->serdes->lvds_panel */
|
|
&pwm2_8ch_5 {
|
|
pinctrl-0 = <&pwm2m1_ch5>;
|
|
status = "okay";
|
|
};
|
|
|
|
&route_dp0 {
|
|
status = "disabled";
|
|
connect = <&vp0_out_dp0>;
|
|
logo,uboot = "logo34.bmp";
|
|
logo,kernel = "logo34.bmp";
|
|
};
|
|
|
|
&route_dsi {
|
|
status = "disabled";
|
|
connect = <&vp2_out_dsi>;
|
|
logo,uboot = "logo1.bmp";
|
|
logo,kernel = "logo1.bmp";
|
|
};
|
|
|
|
&route_edp {
|
|
status = "disabled";
|
|
connect = <&vp1_out_edp>;
|
|
logo,uboot = "logo2.bmp";
|
|
logo,kernel = "logo2.bmp";
|
|
};
|
|
|
|
&usbdp_phy {
|
|
rockchip,dp-lane-mux = <0 1 2 3>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbdp_phy_dp {
|
|
status = "okay";
|
|
};
|
|
|
|
&usbdp_phy_u3 {
|
|
maximum-speed = "high-speed";
|
|
status = "okay";
|
|
};
|
|
|
|
&vop {
|
|
assigned-clocks = <&cru PLL_VPLL>;
|
|
assigned-clock-rates = <1150000000>;
|
|
};
|
|
|
|
//dsi
|
|
&vp1 {
|
|
assigned-clocks = <&cru DCLK_VP1_SRC>;
|
|
assigned-clock-parents = <&cru PLL_VPLL>;
|
|
};
|
|
|