724 lines
19 KiB
Plaintext
724 lines
19 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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*
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*/
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#include <dt-bindings/display/media-bus-format.h>
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/ {
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max96712_dphy0_osc: max96712-dphy0-oscillator {
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compatible = "fixed-clock";
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#clock-cells = <1>;
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clock-frequency = <25000000>;
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clock-output-names = "max96712-dphy0-osc";
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};
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max96712_dphy0_vcc1v2: max96712-dphy0-vcc1v2 {
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compatible = "regulator-fixed";
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regulator-name = "max96712_dphy0_vcc1v2";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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startup-delay-us = <850>;
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vin-supply = <&vcc5v0_buck>;
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};
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max96712_dphy0_vcc1v8: max96712-dphy0-vcc1v8 {
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compatible = "regulator-fixed";
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regulator-name = "max96712_dphy0_vcc1v8";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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startup-delay-us = <200>;
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vin-supply = <&vcc_3v3_s3>;
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};
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max96712_dphy0_pwdn_regulator: max96712-dphy0-pwdn-regulator {
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compatible = "regulator-fixed";
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regulator-name = "max96712_dphy0_pwdn";
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gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&max96712_dphy0_pwdn>;
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enable-active-high;
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startup-delay-us = <10000>;
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off-on-delay-us = <5000>;
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vin-supply = <&max96712_dphy0_vcc1v8>;
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};
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max96712_dphy0_poc_regulator: max96712-dphy0-poc-regulator {
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compatible = "regulator-fixed";
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regulator-name = "max96712_dphy0_poc";
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gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <10000>;
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off-on-delay-us = <5000>;
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vin-supply = <&dphy0_vcc12v_buck1>;
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};
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};
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&csi2_dphy0_hw {
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status = "okay";
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};
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&csi2_dphy0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_dphy0_in_max96712: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&max96712_dphy0_out>;
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data-lanes = <1 2 3 4>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy0_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi1_csi2_input>;
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};
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};
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};
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};
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&i2c5 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5m3_xfer>;
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max96712_dphy0: max96712@29 {
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compatible = "maxim4c,max96712";
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status = "okay";
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reg = <0x29>;
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clock-names = "xvclk";
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clocks = <&max96712_dphy0_osc 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&max96712_dphy0_errb>, <&max96712_dphy0_lock>;
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power-domains = <&power RK3576_PD_VI>;
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rockchip,grf = <&sys_grf>;
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vcc1v2-supply = <&max96712_dphy0_vcc1v2>;
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vcc1v8-supply = <&max96712_dphy0_vcc1v8>;
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pwdn-supply = <&max96712_dphy0_pwdn_regulator>;
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lock-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "default";
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rockchip,camera-module-lens-name = "default";
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port {
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max96712_dphy0_out: endpoint {
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remote-endpoint = <&mipi_dphy0_in_max96712>;
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data-lanes = <1 2 3 4>;
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};
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};
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/* support mode config start */
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support-mode-config {
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status = "okay";
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bus-format = <MEDIA_BUS_FMT_UYVY8_2X8>;
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sensor-width = <1920>;
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sensor-height = <1440>;
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max-fps-numerator = <10000>;
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max-fps-denominator = <300000>;
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bpp = <16>;
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link-freq-idx = <20>;
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};
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/* support mode config end */
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/* serdes local device start */
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serdes-local-device {
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status = "okay";
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/* GMSL LINK config start */
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gmsl-links {
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status = "okay";
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link-vdd-ldo1-en = <1>;
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link-vdd-ldo2-en = <1>;
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// Link A: link-id = 0
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gmsl-link-config-0 {
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status = "okay";
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link-id = <0>; // Link ID: 0/1/2/3
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link-type = <1>; // 0: GMSL1, 1: GMSL2
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link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
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link-tx-rate = <0>; // 0: default for 187.5MBPS
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link-remote-cam = <&max96712_dphy0_cam0>; // remote camera
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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14 D1 03 00 00 // VGAHiGain
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14 45 00 00 00 // Disable SSC
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];
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};
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};
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// Link B: link-id = 1
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gmsl-link-config-1 {
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status = "okay";
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link-id = <1>; // Link ID: 0/1/2/3
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link-type = <1>; // 0: GMSL1, 1: GMSL2
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link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
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link-tx-rate = <0>; // 0: default for 187.5MBPS
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link-remote-cam = <&max96712_dphy0_cam1>; // remote camera
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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15 D1 03 00 00 // VGAHiGain
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15 45 00 00 00 // Disable SSC
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];
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};
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};
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// Link C: link-id = 2
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gmsl-link-config-2 {
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status = "okay";
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link-id = <2>; // Link ID: 0/1/2/3
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link-type = <1>; // 0: GMSL1, 1: GMSL2
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link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
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link-tx-rate = <0>; // 0: default for 187.5MBPS
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link-remote-cam = <&max96712_dphy0_cam2>; // remote camera
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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16 D1 03 00 00 // VGAHiGain
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16 45 00 00 00 // Disable SSC
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];
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};
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};
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// Link D: link-id = 3
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gmsl-link-config-3 {
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status = "okay";
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link-id = <3>; // Link ID: 0/1/2/3
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link-type = <1>; // 0: GMSL1, 1: GMSL2
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link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
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link-tx-rate = <0>; // 0: default for 187.5MBPS
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link-remote-cam = <&max96712_dphy0_cam3>; // remote camera
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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17 D1 03 00 00 // VGAHiGain
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17 45 00 00 00 // Disable SSC
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];
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};
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};
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};
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/* GMSL LINK config end */
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/* VIDEO PIPE config start */
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video-pipes {
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status = "okay";
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// Video Pipe 0
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video-pipe-config-0 {
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status = "okay";
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pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7
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pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <0>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Send YUV422, FS, and FE from Video Pipe 0 to Controller 1
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09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
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09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
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// For the following MSB 2 bits = VC, LSB 6 bits = DT
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09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
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09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit
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09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start
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09 10 00 00 00 // DST1 VC = 0, DT = Frame Start
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09 11 01 00 00 // SRC2 VC = 0, DT = Frame End
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09 12 01 00 00 // DST2 VC = 0, DT = Frame End
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];
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};
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};
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// Video Pipe 1
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video-pipe-config-1 {
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status = "okay";
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pipe-id = <1>; // Video Pipe 1: pipe-id = 1
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pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <1>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Send YUV422, FS, and FE from Video Pipe 1 to Controller 1
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09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
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09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
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// For the following MSB 2 bits = VC, LSB 6 bits = DT
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09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
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09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit
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09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start
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09 50 40 00 00 // DST1 VC = 1, DT = Frame Start
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09 51 01 00 00 // SRC2 VC = 0, DT = Frame End
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09 52 41 00 00 // DST2 VC = 1, DT = Frame End
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];
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};
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};
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// Video Pipe 2
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video-pipe-config-2 {
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status = "okay";
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pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7
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pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <2>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Send YUV422, FS, and FE from Video Pipe 2 to Controller 1
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09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
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09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
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// For the following MSB 2 bits = VC, LSB 6 bits = DT
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09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
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09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit
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09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start
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09 90 80 00 00 // DST1 VC = 2, DT = Frame Start
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09 91 01 00 00 // SRC2 VC = 0, DT = Frame End
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09 92 81 00 00 // DST2 VC = 2, DT = Frame End
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];
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};
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};
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// Video Pipe 3
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video-pipe-config-3 {
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status = "okay";
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pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7
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pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <3>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Send YUV422, FS, and FE from Video Pipe 3 to Controller 1
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09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings
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09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
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// For the following MSB 2 bits = VC, LSB 6 bits = DT
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09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
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09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit
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09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start
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09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start
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09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End
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09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End
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];
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};
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};
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};
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/* VIDEO PIPE config end */
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/* MIPI TXPHY config start */
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mipi-txphys {
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status = "okay";
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phy-mode = <0>; // 0: 4Lanes, 1: 2Lanes
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phy-force-clock-out = <1>; // 1: default for force clock out
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phy-force-clk0-en = <1>; // provide MIPI clock: 0 = PHY1, 1 = PHY0
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phy-force-clk3-en = <0>; // provide MIPI clock: 0 = PHY2, 1 = PHY3
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// MIPI TXPHY A: phy-id = 0
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mipi-txphy-config-0 {
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status = "okay";
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phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3
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phy-type = <0>; // 0: DPHY, 1: CPHY
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auto-deskew = <0x80>;
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data-lane-num = <4>;
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data-lane-map = <0x4>;
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vc-ext-en = <0>;
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};
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// MIPI TXPHY B: phy-id = 1
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mipi-txphy-config-1 {
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status = "okay";
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phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3
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phy-type = <0>; // 0: DPHY, 1: CPHY
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auto-deskew = <0x80>;
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data-lane-num = <4>;
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data-lane-map = <0xe>;
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vc-ext-en = <0>;
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};
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};
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/* MIPI TXPHY config end */
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/* local device extra init sequence */
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extra-init-sequence {
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status = "disabled";
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// common init sequence such as fsync / gpio and so on
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];
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};
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};
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/* serdes local device end */
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/* i2c-mux start */
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i2c-mux {
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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// Note: Serializer node defined before camera node
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max96712_dphy0_ser0: max96717@51 {
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compatible = "maxim,ser,max96717";
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reg = <0x51>;
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ser-i2c-addr-def = <0x40>;
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ser-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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03 02 10 00 00
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14 17 00 00 00
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14 32 7f 00 00
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];
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};
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};
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max96712_dphy0_cam0: sc320at@31 {
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compatible = "maxim,smartsens,sc320at";
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reg = <0x31>;
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cam-i2c-addr-def = <0x30>;
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cam-remote-ser = <&max96712_dphy0_ser0>; // remote serializer
|
|
|
|
poc-supply = <&max96712_dphy0_poc_regulator>;
|
|
|
|
rockchip,camera-module-index = <0>;
|
|
rockchip,camera-module-facing = "back";
|
|
rockchip,camera-module-name = "default";
|
|
rockchip,camera-module-lens-name = "default";
|
|
|
|
/* port config start */
|
|
port {
|
|
max96712_dphy0_cam0_out: endpoint {
|
|
/* remote endpoint: rkcif_mipi_lvds_sditf */
|
|
//remote-endpoint = <&mipi_lvds_sditf_in>;
|
|
data-lanes = <1 2 3 4>;
|
|
};
|
|
};
|
|
/* port config end */
|
|
};
|
|
};
|
|
|
|
i2c@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
|
|
// Note: Serializer node defined before camera node
|
|
max96712_dphy0_ser1: max96717@52 {
|
|
compatible = "maxim,ser,max96717";
|
|
reg = <0x52>;
|
|
|
|
ser-i2c-addr-def = <0x40>;
|
|
|
|
ser-init-sequence {
|
|
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
|
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
|
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
|
|
|
// reg_addr reg_val val_mask delay
|
|
init-sequence = [
|
|
03 02 10 00 00
|
|
14 17 00 00 00
|
|
14 32 7f 00 00
|
|
];
|
|
};
|
|
};
|
|
|
|
// Note: Serializer node defined before camera node
|
|
max96712_dphy0_cam1: sc320at@32 {
|
|
compatible = "maxim,smartsens,sc320at";
|
|
reg = <0x32>;
|
|
|
|
cam-i2c-addr-def = <0x30>;
|
|
|
|
cam-remote-ser = <&max96712_dphy0_ser1>; // remote serializer
|
|
|
|
poc-supply = <&max96712_dphy0_poc_regulator>;
|
|
|
|
rockchip,camera-module-index = <1>;
|
|
rockchip,camera-module-facing = "back";
|
|
rockchip,camera-module-name = "default";
|
|
rockchip,camera-module-lens-name = "default";
|
|
|
|
/* port config start */
|
|
port {
|
|
max96712_dphy0_cam1_out: endpoint {
|
|
/* remote endpoint: rkcif_mipi_lvds_sditf_vir1 */
|
|
//remote-endpoint = <&mipi_lvds_sditf_vir1_in>;
|
|
data-lanes = <1 2 3 4>;
|
|
};
|
|
};
|
|
/* port config end */
|
|
};
|
|
};
|
|
|
|
i2c@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <2>;
|
|
|
|
// Note: Serializer node defined before camera node
|
|
max96712_dphy0_ser2: max96717@53 {
|
|
compatible = "maxim,ser,max96717";
|
|
reg = <0x53>;
|
|
|
|
ser-i2c-addr-def = <0x40>;
|
|
|
|
ser-init-sequence {
|
|
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
|
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
|
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
|
|
|
// reg_addr reg_val val_mask delay
|
|
init-sequence = [
|
|
03 02 10 00 00
|
|
14 17 00 00 00
|
|
14 32 7f 00 00
|
|
];
|
|
};
|
|
};
|
|
|
|
max96712_dphy0_cam2: sc320at@33 {
|
|
compatible = "maxim,smartsens,sc320at";
|
|
reg = <0x33>;
|
|
|
|
cam-i2c-addr-def = <0x30>;
|
|
|
|
cam-remote-ser = <&max96712_dphy0_ser2>; // remote serializer
|
|
|
|
poc-supply = <&max96712_dphy0_poc_regulator>;
|
|
|
|
rockchip,camera-module-index = <2>;
|
|
rockchip,camera-module-facing = "back";
|
|
rockchip,camera-module-name = "default";
|
|
rockchip,camera-module-lens-name = "default";
|
|
|
|
/* port config start */
|
|
port {
|
|
max96712_dphy0_cam2_out: endpoint {
|
|
/* remote endpoint: rkcif_mipi_lvds_sditf_vir2 */
|
|
//remote-endpoint = <&mipi_lvds_sditf_vir2_in>;
|
|
data-lanes = <1 2 3 4>;
|
|
};
|
|
};
|
|
/* port config end */
|
|
};
|
|
};
|
|
|
|
i2c@3 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <3>;
|
|
|
|
// Note: Serializer node defined before camera node
|
|
max96712_dphy0_ser3: max96717@54 {
|
|
compatible = "maxim,ser,max96717";
|
|
reg = <0x54>;
|
|
|
|
ser-i2c-addr-def = <0x40>;
|
|
|
|
ser-init-sequence {
|
|
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
|
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
|
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
|
|
|
// reg_addr reg_val val_mask delay
|
|
init-sequence = [
|
|
03 02 10 00 00
|
|
14 17 00 00 00
|
|
14 32 7f 00 00
|
|
];
|
|
};
|
|
};
|
|
|
|
max96712_dphy0_cam3: sc320at@34 {
|
|
compatible = "maxim,smartsens,sc320at";
|
|
reg = <0x34>;
|
|
|
|
cam-i2c-addr-def = <0x30>;
|
|
|
|
cam-remote-ser = <&max96712_dphy0_ser3>; // remote serializer
|
|
|
|
poc-supply = <&max96712_dphy0_poc_regulator>;
|
|
|
|
rockchip,camera-module-index = <3>;
|
|
rockchip,camera-module-facing = "back";
|
|
rockchip,camera-module-name = "default";
|
|
rockchip,camera-module-lens-name = "default";
|
|
|
|
/* port config start */
|
|
port {
|
|
max96712_dphy0_cam3_out: endpoint {
|
|
/* remote endpoint: rkcif_mipi_lvds_sditf_vir3 */
|
|
//remote-endpoint = <&mipi_lvds_sditf_vir3_in>;
|
|
data-lanes = <1 2 3 4>;
|
|
};
|
|
};
|
|
/* port config end */
|
|
};
|
|
};
|
|
};
|
|
/* i2c-mux end */
|
|
};
|
|
};
|
|
|
|
&mipi1_csi2 {
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mipi1_csi2_input: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&csidphy0_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mipi1_csi2_output: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&cif_mipi1_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&rkcif_mipi_lvds1 {
|
|
status = "okay";
|
|
/* parameters for do cif reset detecting:
|
|
* index0: monitor mode,
|
|
0 for idle,
|
|
1 for continue,
|
|
2 for trigger,
|
|
3 for hotplug (for nextchip)
|
|
* index1: the frame id to start timer,
|
|
min is 2
|
|
* index2: frame num of monitoring cycle
|
|
* index3: err time for keep monitoring
|
|
after finding out err (ms)
|
|
* index4: csi2 err reference val for resetting
|
|
*/
|
|
rockchip,cif-monitor = <3 2 1 1000 5>;
|
|
|
|
port {
|
|
cif_mipi1_in: endpoint {
|
|
remote-endpoint = <&mipi1_csi2_output>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&rkcif {
|
|
status = "okay";
|
|
rockchip,android-usb-camerahal-enable;
|
|
};
|
|
|
|
&rkcif_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&pinctrl {
|
|
max96712-dphy0 {
|
|
max96712_dphy0_pwdn: max96712-dphy0-pwdn {
|
|
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_output_low>;
|
|
};
|
|
|
|
max96712_dphy0_errb: max96712-dphy0-errb {
|
|
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none_smt>;
|
|
};
|
|
|
|
max96712_dphy0_lock: max96712-dphy0-lock {
|
|
rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none_smt>;
|
|
};
|
|
};
|
|
};
|