799 lines
24 KiB
Plaintext
799 lines
24 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config XTENSA
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def_bool y
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select ARCH_32BIT_OFF_T
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select ARCH_HAS_BINFMT_FLAT if !MMU
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select ARCH_HAS_CURRENT_STACK_POINTER
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select ARCH_HAS_DEBUG_VM_PGTABLE
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select ARCH_HAS_DMA_PREP_COHERENT if MMU
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select ARCH_HAS_GCOV_PROFILE_ALL
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select ARCH_HAS_KCOV
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select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU
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select ARCH_HAS_DMA_SET_UNCACHED if MMU
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select ARCH_HAS_STRNCPY_FROM_USER if !KASAN
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select ARCH_HAS_STRNLEN_USER
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select ARCH_USE_MEMTEST
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select ARCH_USE_QUEUED_RWLOCKS
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select ARCH_USE_QUEUED_SPINLOCKS
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select ARCH_WANT_FRAME_POINTERS
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select ARCH_WANT_IPC_PARSE_VERSION
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select BUILDTIME_TABLE_SORT
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select CLONE_BACKWARDS
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select COMMON_CLK
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select DMA_NONCOHERENT_MMAP if MMU
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select GENERIC_ATOMIC64
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select GENERIC_IRQ_SHOW
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select GENERIC_LIB_CMPDI2
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select GENERIC_LIB_MULDI3
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select GENERIC_LIB_UCMPDI2
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select GENERIC_PCI_IOMAP
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select GENERIC_SCHED_CLOCK
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select HAVE_ARCH_AUDITSYSCALL
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select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
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select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
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select HAVE_ARCH_KCSAN
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select HAVE_ARCH_SECCOMP_FILTER
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select HAVE_ARCH_TRACEHOOK
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select HAVE_CONTEXT_TRACKING_USER
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select HAVE_DEBUG_KMEMLEAK
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select HAVE_DMA_CONTIGUOUS
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select HAVE_EXIT_THREAD
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select HAVE_FUNCTION_TRACER
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select HAVE_GCC_PLUGINS if GCC_VERSION >= 120000
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select HAVE_HW_BREAKPOINT if PERF_EVENTS
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select HAVE_IRQ_TIME_ACCOUNTING
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select HAVE_PCI
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select HAVE_PERF_EVENTS
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select HAVE_STACKPROTECTOR
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select HAVE_SYSCALL_TRACEPOINTS
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select HAVE_VIRT_CPU_ACCOUNTING_GEN
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select IRQ_DOMAIN
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select LOCK_MM_AND_FIND_VMA
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select MODULES_USE_ELF_RELA
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select PERF_USE_VMALLOC
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select TRACE_IRQFLAGS_SUPPORT
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help
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Xtensa processors are 32-bit RISC machines designed by Tensilica
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primarily for embedded systems. These processors are both
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configurable and extensible. The Linux port to the Xtensa
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architecture supports all processor configurations and extensions,
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with reasonable minimum requirements. The Xtensa Linux project has
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a home page at <http://www.linux-xtensa.org/>.
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config GENERIC_HWEIGHT
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def_bool y
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config ARCH_HAS_ILOG2_U32
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def_bool n
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config ARCH_HAS_ILOG2_U64
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def_bool n
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config NO_IOPORT_MAP
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def_bool n
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config HZ
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int
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default 100
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config LOCKDEP_SUPPORT
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def_bool y
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config STACKTRACE_SUPPORT
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def_bool y
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config MMU
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def_bool n
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select PFAULT
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config HAVE_XTENSA_GPIO32
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def_bool n
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config KASAN_SHADOW_OFFSET
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hex
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default 0x6e400000
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config CPU_BIG_ENDIAN
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def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1)
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config CPU_LITTLE_ENDIAN
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def_bool !CPU_BIG_ENDIAN
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config CC_HAVE_CALL0_ABI
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def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null)" = 1)
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menu "Processor type and features"
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choice
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prompt "Xtensa Processor Configuration"
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default XTENSA_VARIANT_FSF
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config XTENSA_VARIANT_FSF
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bool "fsf - default (not generic) configuration"
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select MMU
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config XTENSA_VARIANT_DC232B
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bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
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select MMU
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select HAVE_XTENSA_GPIO32
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help
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This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
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config XTENSA_VARIANT_DC233C
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bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
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select MMU
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select HAVE_XTENSA_GPIO32
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help
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This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
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config XTENSA_VARIANT_CUSTOM
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bool "Custom Xtensa processor configuration"
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select HAVE_XTENSA_GPIO32
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help
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Select this variant to use a custom Xtensa processor configuration.
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You will be prompted for a processor variant CORENAME.
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endchoice
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config XTENSA_VARIANT_CUSTOM_NAME
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string "Xtensa Processor Custom Core Variant Name"
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depends on XTENSA_VARIANT_CUSTOM
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help
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Provide the name of a custom Xtensa processor variant.
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This CORENAME selects arch/xtensa/variant/CORENAME.
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Don't forget you have to select MMU if you have one.
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config XTENSA_VARIANT_NAME
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string
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default "dc232b" if XTENSA_VARIANT_DC232B
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default "dc233c" if XTENSA_VARIANT_DC233C
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default "fsf" if XTENSA_VARIANT_FSF
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default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM
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config XTENSA_VARIANT_MMU
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bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"
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depends on XTENSA_VARIANT_CUSTOM
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default y
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select MMU
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help
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Build a Conventional Kernel with full MMU support,
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ie: it supports a TLB with auto-loading, page protection.
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config XTENSA_VARIANT_HAVE_PERF_EVENTS
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bool "Core variant has Performance Monitor Module"
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depends on XTENSA_VARIANT_CUSTOM
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default n
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help
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Enable if core variant has Performance Monitor Module with
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External Registers Interface.
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If unsure, say N.
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config XTENSA_FAKE_NMI
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bool "Treat PMM IRQ as NMI"
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depends on XTENSA_VARIANT_HAVE_PERF_EVENTS
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default n
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help
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If PMM IRQ is the only IRQ at EXCM level it is safe to
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treat it as NMI, which improves accuracy of profiling.
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If there are other interrupts at or above PMM IRQ priority level
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but not above the EXCM level, PMM IRQ still may be treated as NMI,
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but only if these IRQs are not used. There will be a build warning
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saying that this is not safe, and a bugcheck if one of these IRQs
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actually fire.
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If unsure, say N.
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config PFAULT
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bool "Handle protection faults" if EXPERT && !MMU
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default y
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help
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Handle protection faults. MMU configurations must enable it.
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noMMU configurations may disable it if used memory map never
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generates protection faults or faults are always fatal.
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If unsure, say Y.
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config XTENSA_UNALIGNED_USER
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bool "Unaligned memory access in user space"
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help
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The Xtensa architecture currently does not handle unaligned
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memory accesses in hardware but through an exception handler.
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Per default, unaligned memory accesses are disabled in user space.
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Say Y here to enable unaligned memory access in user space.
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config HAVE_SMP
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bool "System Supports SMP (MX)"
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depends on XTENSA_VARIANT_CUSTOM
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select XTENSA_MX
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help
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This option is used to indicate that the system-on-a-chip (SOC)
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supports Multiprocessing. Multiprocessor support implemented above
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the CPU core definition and currently needs to be selected manually.
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Multiprocessor support is implemented with external cache and
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interrupt controllers.
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The MX interrupt distributer adds Interprocessor Interrupts
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and causes the IRQ numbers to be increased by 4 for devices
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like the open cores ethernet driver and the serial interface.
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You still have to select "Enable SMP" to enable SMP on this SOC.
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config SMP
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bool "Enable Symmetric multi-processing support"
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depends on HAVE_SMP
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select GENERIC_SMP_IDLE_THREAD
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help
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Enabled SMP Software; allows more than one CPU/CORE
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to be activated during startup.
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config NR_CPUS
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depends on SMP
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int "Maximum number of CPUs (2-32)"
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range 2 32
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default "4"
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config HOTPLUG_CPU
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bool "Enable CPU hotplug support"
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depends on SMP
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help
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Say Y here to allow turning CPUs off and on. CPUs can be
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controlled through /sys/devices/system/cpu.
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Say N if you want to disable CPU hotplug.
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config SECONDARY_RESET_VECTOR
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bool "Secondary cores use alternative reset vector"
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default y
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depends on HAVE_SMP
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help
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Secondary cores may be configured to use alternative reset vector,
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or all cores may use primary reset vector.
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Say Y here to supply handler for the alternative reset location.
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config FAST_SYSCALL_XTENSA
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bool "Enable fast atomic syscalls"
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default n
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help
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fast_syscall_xtensa is a syscall that can make atomic operations
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on UP kernel when processor has no s32c1i support.
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This syscall is deprecated. It may have issues when called with
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invalid arguments. It is provided only for backwards compatibility.
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Only enable it if your userspace software requires it.
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If unsure, say N.
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config FAST_SYSCALL_SPILL_REGISTERS
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bool "Enable spill registers syscall"
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default n
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help
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fast_syscall_spill_registers is a syscall that spills all active
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register windows of a calling userspace task onto its stack.
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This syscall is deprecated. It may have issues when called with
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invalid arguments. It is provided only for backwards compatibility.
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Only enable it if your userspace software requires it.
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If unsure, say N.
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choice
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prompt "Kernel ABI"
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default KERNEL_ABI_DEFAULT
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help
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Select ABI for the kernel code. This ABI is independent of the
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supported userspace ABI and any combination of the
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kernel/userspace ABI is possible and should work.
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In case both kernel and userspace support only call0 ABI
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all register windows support code will be omitted from the
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build.
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If unsure, choose the default ABI.
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config KERNEL_ABI_DEFAULT
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bool "Default ABI"
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help
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Select this option to compile kernel code with the default ABI
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selected for the toolchain.
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Normally cores with windowed registers option use windowed ABI and
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cores without it use call0 ABI.
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config KERNEL_ABI_CALL0
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bool "Call0 ABI" if CC_HAVE_CALL0_ABI
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help
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Select this option to compile kernel code with call0 ABI even with
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toolchain that defaults to windowed ABI.
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When this option is not selected the default toolchain ABI will
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be used for the kernel code.
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endchoice
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config USER_ABI_CALL0
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bool
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choice
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prompt "Userspace ABI"
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default USER_ABI_DEFAULT
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help
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Select supported userspace ABI.
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If unsure, choose the default ABI.
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config USER_ABI_DEFAULT
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bool "Default ABI only"
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help
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Assume default userspace ABI. For XEA2 cores it is windowed ABI.
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call0 ABI binaries may be run on such kernel, but signal delivery
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will not work correctly for them.
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config USER_ABI_CALL0_ONLY
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bool "Call0 ABI only"
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select USER_ABI_CALL0
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help
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Select this option to support only call0 ABI in userspace.
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Windowed ABI binaries will crash with a segfault caused by
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an illegal instruction exception on the first 'entry' opcode.
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Choose this option if you're planning to run only user code
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built with call0 ABI.
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config USER_ABI_CALL0_PROBE
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bool "Support both windowed and call0 ABI by probing"
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select USER_ABI_CALL0
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help
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Select this option to support both windowed and call0 userspace
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ABIs. When enabled all processes are started with PS.WOE disabled
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and a fast user exception handler for an illegal instruction is
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used to turn on PS.WOE bit on the first 'entry' opcode executed by
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the userspace.
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This option should be enabled for the kernel that must support
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both call0 and windowed ABIs in userspace at the same time.
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Note that Xtensa ISA does not guarantee that entry opcode will
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raise an illegal instruction exception on cores with XEA2 when
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PS.WOE is disabled, check whether the target core supports it.
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endchoice
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endmenu
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config XTENSA_CALIBRATE_CCOUNT
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def_bool n
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help
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On some platforms (XT2000, for example), the CPU clock rate can
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vary. The frequency can be determined, however, by measuring
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against a well known, fixed frequency, such as an UART oscillator.
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config SERIAL_CONSOLE
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def_bool n
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config PLATFORM_HAVE_XIP
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def_bool n
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menu "Platform options"
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choice
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prompt "Xtensa System Type"
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default XTENSA_PLATFORM_ISS
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config XTENSA_PLATFORM_ISS
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bool "ISS"
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select XTENSA_CALIBRATE_CCOUNT
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select SERIAL_CONSOLE
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help
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ISS is an acronym for Tensilica's Instruction Set Simulator.
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config XTENSA_PLATFORM_XT2000
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bool "XT2000"
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help
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XT2000 is the name of Tensilica's feature-rich emulation platform.
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This hardware is capable of running a full Linux distribution.
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config XTENSA_PLATFORM_XTFPGA
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bool "XTFPGA"
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select ETHOC if ETHERNET
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select PLATFORM_WANT_DEFAULT_MEM if !MMU
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select SERIAL_CONSOLE
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select XTENSA_CALIBRATE_CCOUNT
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select PLATFORM_HAVE_XIP
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help
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XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).
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This hardware is capable of running a full Linux distribution.
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endchoice
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config PLATFORM_NR_IRQS
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int
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default 3 if XTENSA_PLATFORM_XT2000
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default 0
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config XTENSA_CPU_CLOCK
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int "CPU clock rate [MHz]"
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depends on !XTENSA_CALIBRATE_CCOUNT
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default 16
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config GENERIC_CALIBRATE_DELAY
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bool "Auto calibration of the BogoMIPS value"
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help
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The BogoMIPS value can easily be derived from the CPU frequency.
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config CMDLINE_BOOL
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bool "Default bootloader kernel arguments"
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config CMDLINE
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string "Initial kernel command string"
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depends on CMDLINE_BOOL
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default "console=ttyS0,38400 root=/dev/ram"
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help
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On some architectures (EBSA110 and CATS), there is currently no way
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for the boot loader to pass arguments to the kernel. For these
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architectures, you should supply some command-line options at build
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time by entering them here. As a minimum, you should specify the
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memory size and the root device (e.g., mem=64M root=/dev/nfs).
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config USE_OF
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bool "Flattened Device Tree support"
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select OF
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select OF_EARLY_FLATTREE
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help
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Include support for flattened device tree machine descriptions.
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config BUILTIN_DTB_SOURCE
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string "DTB to build into the kernel image"
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depends on OF
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config PARSE_BOOTPARAM
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bool "Parse bootparam block"
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default y
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help
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Parse parameters passed to the kernel from the bootloader. It may
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be disabled if the kernel is known to run without the bootloader.
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If unsure, say Y.
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choice
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prompt "Semihosting interface"
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default XTENSA_SIMCALL_ISS
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depends on XTENSA_PLATFORM_ISS
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help
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Choose semihosting interface that will be used for serial port,
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block device and networking.
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config XTENSA_SIMCALL_ISS
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bool "simcall"
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help
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Use simcall instruction. simcall is only available on simulators,
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it does nothing on hardware.
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config XTENSA_SIMCALL_GDBIO
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bool "GDBIO"
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help
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Use break instruction. It is available on real hardware when GDB
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is attached to it via JTAG.
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endchoice
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config BLK_DEV_SIMDISK
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tristate "Host file-based simulated block device support"
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default n
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depends on XTENSA_PLATFORM_ISS && BLOCK
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help
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Create block devices that map to files in the host file system.
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Device binding to host file may be changed at runtime via proc
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interface provided the device is not in use.
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config BLK_DEV_SIMDISK_COUNT
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int "Number of host file-based simulated block devices"
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range 1 10
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depends on BLK_DEV_SIMDISK
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default 2
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help
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This is the default minimal number of created block devices.
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Kernel/module parameter 'simdisk_count' may be used to change this
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value at runtime. More file names (but no more than 10) may be
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specified as parameters, simdisk_count grows accordingly.
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config SIMDISK0_FILENAME
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string "Host filename for the first simulated device"
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depends on BLK_DEV_SIMDISK = y
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default ""
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help
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Attach a first simdisk to a host file. Conventionally, this file
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contains a root file system.
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config SIMDISK1_FILENAME
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string "Host filename for the second simulated device"
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depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1
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default ""
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help
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Another simulated disk in a host file for a buildroot-independent
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storage.
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config XTFPGA_LCD
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bool "Enable XTFPGA LCD driver"
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depends on XTENSA_PLATFORM_XTFPGA
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default n
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help
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There's a 2x16 LCD on most of XTFPGA boards, kernel may output
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progress messages there during bootup/shutdown. It may be useful
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during board bringup.
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If unsure, say N.
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config XTFPGA_LCD_BASE_ADDR
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hex "XTFPGA LCD base address"
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depends on XTFPGA_LCD
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default "0x0d0c0000"
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help
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Base address of the LCD controller inside KIO region.
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Different boards from XTFPGA family have LCD controller at different
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addresses. Please consult prototyping user guide for your board for
|
|
the correct address. Wrong address here may lead to hardware lockup.
|
|
|
|
config XTFPGA_LCD_8BIT_ACCESS
|
|
bool "Use 8-bit access to XTFPGA LCD"
|
|
depends on XTFPGA_LCD
|
|
default n
|
|
help
|
|
LCD may be connected with 4- or 8-bit interface, 8-bit access may
|
|
only be used with 8-bit interface. Please consult prototyping user
|
|
guide for your board for the correct interface width.
|
|
|
|
comment "Kernel memory layout"
|
|
|
|
config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
|
|
bool "Initialize Xtensa MMU inside the Linux kernel code"
|
|
depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B
|
|
default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM
|
|
help
|
|
Earlier version initialized the MMU in the exception vector
|
|
before jumping to _startup in head.S and had an advantage that
|
|
it was possible to place a software breakpoint at 'reset' and
|
|
then enter your normal kernel breakpoints once the MMU was mapped
|
|
to the kernel mappings (0XC0000000).
|
|
|
|
This unfortunately won't work for U-Boot and likely also won't
|
|
work for using KEXEC to have a hot kernel ready for doing a
|
|
KDUMP.
|
|
|
|
So now the MMU is initialized in head.S but it's necessary to
|
|
use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup.
|
|
xt-gdb can't place a Software Breakpoint in the 0XD region prior
|
|
to mapping the MMU and after mapping even if the area of low memory
|
|
was mapped gdb wouldn't remove the breakpoint on hitting it as the
|
|
PC wouldn't match. Since Hardware Breakpoints are recommended for
|
|
Linux configurations it seems reasonable to just assume they exist
|
|
and leave this older mechanism for unfortunate souls that choose
|
|
not to follow Tensilica's recommendation.
|
|
|
|
Selecting this will cause U-Boot to set the KERNEL Load and Entry
|
|
address at 0x00003000 instead of the mapped std of 0xD0003000.
|
|
|
|
If in doubt, say Y.
|
|
|
|
config XIP_KERNEL
|
|
bool "Kernel Execute-In-Place from ROM"
|
|
depends on PLATFORM_HAVE_XIP
|
|
help
|
|
Execute-In-Place allows the kernel to run from non-volatile storage
|
|
directly addressable by the CPU, such as NOR flash. This saves RAM
|
|
space since the text section of the kernel is not loaded from flash
|
|
to RAM. Read-write sections, such as the data section and stack,
|
|
are still copied to RAM. The XIP kernel is not compressed since
|
|
it has to run directly from flash, so it will take more space to
|
|
store it. The flash address used to link the kernel object files,
|
|
and for storing it, is configuration dependent. Therefore, if you
|
|
say Y here, you must know the proper physical address where to
|
|
store the kernel image depending on your own flash memory usage.
|
|
|
|
Also note that the make target becomes "make xipImage" rather than
|
|
"make Image" or "make uImage". The final kernel binary to put in
|
|
ROM memory will be arch/xtensa/boot/xipImage.
|
|
|
|
If unsure, say N.
|
|
|
|
config MEMMAP_CACHEATTR
|
|
hex "Cache attributes for the memory address space"
|
|
depends on !MMU
|
|
default 0x22222222
|
|
help
|
|
These cache attributes are set up for noMMU systems. Each hex digit
|
|
specifies cache attributes for the corresponding 512MB memory
|
|
region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
|
|
bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
|
|
|
|
Cache attribute values are specific for the MMU type.
|
|
For region protection MMUs:
|
|
1: WT cached,
|
|
2: cache bypass,
|
|
4: WB cached,
|
|
f: illegal.
|
|
For full MMU:
|
|
bit 0: executable,
|
|
bit 1: writable,
|
|
bits 2..3:
|
|
0: cache bypass,
|
|
1: WB cache,
|
|
2: WT cache,
|
|
3: special (c and e are illegal, f is reserved).
|
|
For MPU:
|
|
0: illegal,
|
|
1: WB cache,
|
|
2: WB, no-write-allocate cache,
|
|
3: WT cache,
|
|
4: cache bypass.
|
|
|
|
config KSEG_PADDR
|
|
hex "Physical address of the KSEG mapping"
|
|
depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
|
|
default 0x00000000
|
|
help
|
|
This is the physical address where KSEG is mapped. Please refer to
|
|
the chosen KSEG layout help for the required address alignment.
|
|
Unpacked kernel image (including vectors) must be located completely
|
|
within KSEG.
|
|
Physical memory below this address is not available to linux.
|
|
|
|
If unsure, leave the default value here.
|
|
|
|
config KERNEL_VIRTUAL_ADDRESS
|
|
hex "Kernel virtual address"
|
|
depends on MMU && XIP_KERNEL
|
|
default 0xd0003000
|
|
help
|
|
This is the virtual address where the XIP kernel is mapped.
|
|
XIP kernel may be mapped into KSEG or KIO region, virtual address
|
|
provided here must match kernel load address provided in
|
|
KERNEL_LOAD_ADDRESS.
|
|
|
|
config KERNEL_LOAD_ADDRESS
|
|
hex "Kernel load address"
|
|
default 0x60003000 if !MMU
|
|
default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
|
|
default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
|
|
help
|
|
This is the address where the kernel is loaded.
|
|
It is virtual address for MMUv2 configurations and physical address
|
|
for all other configurations.
|
|
|
|
If unsure, leave the default value here.
|
|
|
|
choice
|
|
prompt "Relocatable vectors location"
|
|
default XTENSA_VECTORS_IN_TEXT
|
|
help
|
|
Choose whether relocatable vectors are merged into the kernel .text
|
|
or placed separately at runtime. This option does not affect
|
|
configurations without VECBASE register where vectors are always
|
|
placed at their hardware-defined locations.
|
|
|
|
config XTENSA_VECTORS_IN_TEXT
|
|
bool "Merge relocatable vectors into kernel text"
|
|
depends on !MTD_XIP
|
|
help
|
|
This option puts relocatable vectors into the kernel .text section
|
|
with proper alignment.
|
|
This is a safe choice for most configurations.
|
|
|
|
config XTENSA_VECTORS_SEPARATE
|
|
bool "Put relocatable vectors at fixed address"
|
|
help
|
|
This option puts relocatable vectors at specific virtual address.
|
|
Vectors are merged with the .init data in the kernel image and
|
|
are copied into their designated location during kernel startup.
|
|
Use it to put vectors into IRAM or out of FLASH on kernels with
|
|
XIP-aware MTD support.
|
|
|
|
endchoice
|
|
|
|
config VECTORS_ADDR
|
|
hex "Kernel vectors virtual address"
|
|
default 0x00000000
|
|
depends on XTENSA_VECTORS_SEPARATE
|
|
help
|
|
This is the virtual address of the (relocatable) vectors base.
|
|
It must be within KSEG if MMU is used.
|
|
|
|
config XIP_DATA_ADDR
|
|
hex "XIP kernel data virtual address"
|
|
depends on XIP_KERNEL
|
|
default 0x00000000
|
|
help
|
|
This is the virtual address where XIP kernel data is copied.
|
|
It must be within KSEG if MMU is used.
|
|
|
|
config PLATFORM_WANT_DEFAULT_MEM
|
|
def_bool n
|
|
|
|
config DEFAULT_MEM_START
|
|
hex
|
|
prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM
|
|
default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM
|
|
default 0x00000000
|
|
help
|
|
This is the base address used for both PAGE_OFFSET and PHYS_OFFSET
|
|
in noMMU configurations.
|
|
|
|
If unsure, leave the default value here.
|
|
|
|
choice
|
|
prompt "KSEG layout"
|
|
depends on MMU
|
|
default XTENSA_KSEG_MMU_V2
|
|
|
|
config XTENSA_KSEG_MMU_V2
|
|
bool "MMUv2: 128MB cached + 128MB uncached"
|
|
help
|
|
MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
|
|
at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000
|
|
without cache.
|
|
KSEG_PADDR must be aligned to 128MB.
|
|
|
|
config XTENSA_KSEG_256M
|
|
bool "256MB cached + 256MB uncached"
|
|
depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
|
|
help
|
|
TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000
|
|
with cache and to 0xc0000000 without cache.
|
|
KSEG_PADDR must be aligned to 256MB.
|
|
|
|
config XTENSA_KSEG_512M
|
|
bool "512MB cached + 512MB uncached"
|
|
depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
|
|
help
|
|
TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000
|
|
with cache and to 0xc0000000 without cache.
|
|
KSEG_PADDR must be aligned to 256MB.
|
|
|
|
endchoice
|
|
|
|
config HIGHMEM
|
|
bool "High Memory Support"
|
|
depends on MMU
|
|
select KMAP_LOCAL
|
|
help
|
|
Linux can use the full amount of RAM in the system by
|
|
default. However, the default MMUv2 setup only maps the
|
|
lowermost 128 MB of memory linearly to the areas starting
|
|
at 0xd0000000 (cached) and 0xd8000000 (uncached).
|
|
When there are more than 128 MB memory in the system not
|
|
all of it can be "permanently mapped" by the kernel.
|
|
The physical memory that's not permanently mapped is called
|
|
"high memory".
|
|
|
|
If you are compiling a kernel which will never run on a
|
|
machine with more than 128 MB total physical RAM, answer
|
|
N here.
|
|
|
|
If unsure, say Y.
|
|
|
|
config ARCH_FORCE_MAX_ORDER
|
|
int "Maximum zone order"
|
|
default "11"
|
|
help
|
|
The kernel memory allocator divides physically contiguous memory
|
|
blocks into "zones", where each zone is a power of two number of
|
|
pages. This option selects the largest power of two that the kernel
|
|
keeps in the memory allocator. If you need to allocate very large
|
|
blocks of physically contiguous memory, then you may need to
|
|
increase this value.
|
|
|
|
This config option is actually maximum order plus one. For example,
|
|
a value of 11 means that the largest free memory block is 2^10 pages.
|
|
|
|
endmenu
|
|
|
|
menu "Power management options"
|
|
|
|
config ARCH_HIBERNATION_POSSIBLE
|
|
def_bool y
|
|
|
|
source "kernel/power/Kconfig"
|
|
|
|
endmenu
|