214 lines
8.4 KiB
C
Executable File
214 lines
8.4 KiB
C
Executable File
/*
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* Copyright (C) 2012-2014, 2016-2017 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained from Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include "mali_dlbu.h"
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#include "mali_memory.h"
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#include "mali_pp.h"
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#include "mali_group.h"
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#include "mali_osk.h"
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#include "mali_hw_core.h"
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/**
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* Size of DLBU registers in bytes
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*/
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#define MALI_DLBU_SIZE 0x400
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mali_dma_addr mali_dlbu_phys_addr = 0;
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static mali_io_address mali_dlbu_cpu_addr = NULL;
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/**
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* DLBU register numbers
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* Used in the register read/write routines.
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* See the hardware documentation for more information about each register
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*/
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typedef enum mali_dlbu_register {
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MALI_DLBU_REGISTER_MASTER_TLLIST_PHYS_ADDR = 0x0000, /**< Master tile list physical base address;
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31:12 Physical address to the page used for the DLBU
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0 DLBU enable - set this bit to 1 enables the AXI bus
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between PPs and L2s, setting to 0 disables the router and
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no further transactions are sent to DLBU */
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MALI_DLBU_REGISTER_MASTER_TLLIST_VADDR = 0x0004, /**< Master tile list virtual base address;
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31:12 Virtual address to the page used for the DLBU */
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MALI_DLBU_REGISTER_TLLIST_VBASEADDR = 0x0008, /**< Tile list virtual base address;
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31:12 Virtual address to the tile list. This address is used when
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calculating the call address sent to PP.*/
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MALI_DLBU_REGISTER_FB_DIM = 0x000C, /**< Framebuffer dimension;
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23:16 Number of tiles in Y direction-1
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7:0 Number of tiles in X direction-1 */
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MALI_DLBU_REGISTER_TLLIST_CONF = 0x0010, /**< Tile list configuration;
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29:28 select the size of each allocated block: 0=128 bytes, 1=256, 2=512, 3=1024
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21:16 2^n number of tiles to be binned to one tile list in Y direction
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5:0 2^n number of tiles to be binned to one tile list in X direction */
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MALI_DLBU_REGISTER_START_TILE_POS = 0x0014, /**< Start tile positions;
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31:24 start position in Y direction for group 1
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23:16 start position in X direction for group 1
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15:8 start position in Y direction for group 0
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7:0 start position in X direction for group 0 */
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MALI_DLBU_REGISTER_PP_ENABLE_MASK = 0x0018, /**< PP enable mask;
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7 enable PP7 for load balancing
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6 enable PP6 for load balancing
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5 enable PP5 for load balancing
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4 enable PP4 for load balancing
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3 enable PP3 for load balancing
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2 enable PP2 for load balancing
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1 enable PP1 for load balancing
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0 enable PP0 for load balancing */
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} mali_dlbu_register;
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typedef enum {
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PP0ENABLE = 0,
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PP1ENABLE,
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PP2ENABLE,
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PP3ENABLE,
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PP4ENABLE,
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PP5ENABLE,
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PP6ENABLE,
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PP7ENABLE
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} mali_dlbu_pp_enable;
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struct mali_dlbu_core {
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struct mali_hw_core hw_core; /**< Common for all HW cores */
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u32 pp_cores_mask; /**< This is a mask for the PP cores whose operation will be controlled by LBU
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see MALI_DLBU_REGISTER_PP_ENABLE_MASK register */
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};
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_mali_osk_errcode_t mali_dlbu_initialize(void)
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{
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MALI_DEBUG_PRINT(2, ("Mali DLBU: Initializing\n"));
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if (_MALI_OSK_ERR_OK ==
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mali_mmu_get_table_page(&mali_dlbu_phys_addr,
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&mali_dlbu_cpu_addr)) {
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return _MALI_OSK_ERR_OK;
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}
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return _MALI_OSK_ERR_FAULT;
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}
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void mali_dlbu_terminate(void)
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{
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MALI_DEBUG_PRINT(3, ("Mali DLBU: terminating\n"));
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if (0 != mali_dlbu_phys_addr && 0 != mali_dlbu_cpu_addr) {
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mali_mmu_release_table_page(mali_dlbu_phys_addr,
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mali_dlbu_cpu_addr);
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mali_dlbu_phys_addr = 0;
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mali_dlbu_cpu_addr = 0;
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}
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}
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struct mali_dlbu_core *mali_dlbu_create(const _mali_osk_resource_t *resource)
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{
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struct mali_dlbu_core *core = NULL;
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MALI_DEBUG_PRINT(2, ("Mali DLBU: Creating Mali dynamic load balancing unit: %s\n", resource->description));
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core = _mali_osk_malloc(sizeof(struct mali_dlbu_core));
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if (NULL != core) {
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if (_MALI_OSK_ERR_OK == mali_hw_core_create(&core->hw_core, resource, MALI_DLBU_SIZE)) {
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core->pp_cores_mask = 0;
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if (_MALI_OSK_ERR_OK == mali_dlbu_reset(core)) {
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return core;
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}
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MALI_PRINT_ERROR(("Failed to reset DLBU %s\n", core->hw_core.description));
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mali_hw_core_delete(&core->hw_core);
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}
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_mali_osk_free(core);
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} else {
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MALI_PRINT_ERROR(("Mali DLBU: Failed to allocate memory for DLBU core\n"));
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}
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return NULL;
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}
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void mali_dlbu_delete(struct mali_dlbu_core *dlbu)
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{
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MALI_DEBUG_ASSERT_POINTER(dlbu);
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mali_hw_core_delete(&dlbu->hw_core);
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_mali_osk_free(dlbu);
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}
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_mali_osk_errcode_t mali_dlbu_reset(struct mali_dlbu_core *dlbu)
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{
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u32 dlbu_registers[7];
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_mali_osk_errcode_t err = _MALI_OSK_ERR_FAULT;
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MALI_DEBUG_ASSERT_POINTER(dlbu);
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MALI_DEBUG_PRINT(4, ("Mali DLBU: mali_dlbu_reset: %s\n", dlbu->hw_core.description));
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dlbu_registers[0] = mali_dlbu_phys_addr | 1; /* bit 0 enables the whole core */
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dlbu_registers[1] = MALI_DLBU_VIRT_ADDR;
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dlbu_registers[2] = 0;
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dlbu_registers[3] = 0;
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dlbu_registers[4] = 0;
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dlbu_registers[5] = 0;
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dlbu_registers[6] = dlbu->pp_cores_mask;
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/* write reset values to core registers */
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mali_hw_core_register_write_array_relaxed(&dlbu->hw_core, MALI_DLBU_REGISTER_MASTER_TLLIST_PHYS_ADDR, dlbu_registers, 7);
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err = _MALI_OSK_ERR_OK;
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return err;
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}
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void mali_dlbu_update_mask(struct mali_dlbu_core *dlbu)
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{
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MALI_DEBUG_ASSERT_POINTER(dlbu);
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mali_hw_core_register_write(&dlbu->hw_core, MALI_DLBU_REGISTER_PP_ENABLE_MASK, dlbu->pp_cores_mask);
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}
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void mali_dlbu_add_group(struct mali_dlbu_core *dlbu, struct mali_group *group)
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{
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struct mali_pp_core *pp_core;
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u32 bcast_id;
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MALI_DEBUG_ASSERT_POINTER(dlbu);
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MALI_DEBUG_ASSERT_POINTER(group);
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pp_core = mali_group_get_pp_core(group);
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bcast_id = mali_pp_core_get_bcast_id(pp_core);
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dlbu->pp_cores_mask |= bcast_id;
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MALI_DEBUG_PRINT(3, ("Mali DLBU: Adding core[%d] New mask= 0x%02x\n", bcast_id , dlbu->pp_cores_mask));
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}
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/* Remove a group from the DLBU */
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void mali_dlbu_remove_group(struct mali_dlbu_core *dlbu, struct mali_group *group)
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{
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struct mali_pp_core *pp_core;
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u32 bcast_id;
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MALI_DEBUG_ASSERT_POINTER(dlbu);
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MALI_DEBUG_ASSERT_POINTER(group);
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pp_core = mali_group_get_pp_core(group);
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bcast_id = mali_pp_core_get_bcast_id(pp_core);
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dlbu->pp_cores_mask &= ~bcast_id;
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MALI_DEBUG_PRINT(3, ("Mali DLBU: Removing core[%d] New mask= 0x%02x\n", bcast_id, dlbu->pp_cores_mask));
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}
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/* Configure the DLBU for \a job. This needs to be done before the job is started on the groups in the DLBU. */
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void mali_dlbu_config_job(struct mali_dlbu_core *dlbu, struct mali_pp_job *job)
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{
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u32 *registers;
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MALI_DEBUG_ASSERT(job);
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registers = mali_pp_job_get_dlbu_registers(job);
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MALI_DEBUG_PRINT(4, ("Mali DLBU: Starting job\n"));
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/* Writing 4 registers:
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* DLBU registers except the first two (written once at DLBU initialisation / reset) and the PP_ENABLE_MASK register */
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mali_hw_core_register_write_array_relaxed(&dlbu->hw_core, MALI_DLBU_REGISTER_TLLIST_VBASEADDR, registers, 4);
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}
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