35 lines
930 B
Plaintext
35 lines
930 B
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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&cru {
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assigned-clocks =
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<&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>,
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<&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>,
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<&cru PLL_HPLL>, <&cru ARMCLK>,
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<&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>,
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<&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>,
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<&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>,
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<&cru HCLK_PDCORE_NIU>;
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assigned-clock-rates =
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<32768>, <1188000000>,
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<100000000>, <491520000>,
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<1400000000>, <600000000>,
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<500000000>, <200000000>,
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<100000000>, <300000000>,
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<200000000>, <150000000>,
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<200000000>;
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};
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&i2s0_8ch {
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clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>,
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<&cru MCLK_I2S0_TX_DIV>, <&cru MCLK_I2S0_RX_DIV>,
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<&cru PLL_CPLL>, <&cru PLL_CPLL>;
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clock-names = "mclk_tx", "mclk_rx", "hclk",
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"mclk_tx_src", "mclk_rx_src",
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"mclk_root0", "mclk_root1";
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rockchip,mclk-calibrate;
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};
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