1399 lines
29 KiB
Plaintext
1399 lines
29 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rockchip-pinconf.dtsi"
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/*
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* This file is auto generated by pin2dts tool, please keep these code
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* by adding changes at end of this file.
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*/
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&pinctrl {
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adc {
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/omit-if-no-ref/
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adc_pins: adc-pins {
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rockchip,pins =
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/* adc_in0 */
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<4 RK_PC0 1 &pcfg_pull_none>,
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/* adc_in1 */
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<4 RK_PC1 1 &pcfg_pull_none>;
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};
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};
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avs {
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/omit-if-no-ref/
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avs_pins: avs-pins {
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rockchip,pins =
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/* avs_arm */
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<1 RK_PA2 2 &pcfg_pull_none>;
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};
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};
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clk {
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/omit-if-no-ref/
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clk_32k: clk-32k {
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rockchip,pins =
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/* clk_32k */
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<0 RK_PA0 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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clk_refout: clk-refout {
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rockchip,pins =
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/* clk_refout */
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<0 RK_PA0 3 &pcfg_pull_none>;
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};
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};
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dsmaudio {
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/omit-if-no-ref/
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dsmaudio_pins: dsmaudio-pins {
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rockchip,pins =
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/* dsmaudio_n */
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<1 RK_PD3 7 &pcfg_pull_none>,
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/* dsmaudio_p */
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<1 RK_PD2 7 &pcfg_pull_none>;
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};
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};
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emmc {
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/omit-if-no-ref/
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emmc_bus8: emmc-bus8 {
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rockchip,pins =
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/* emmc_d0 */
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<4 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d1 */
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<4 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d2 */
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<4 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d3 */
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<4 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d4 */
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<4 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d5 */
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<4 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d6 */
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<4 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d7 */
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<4 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
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};
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/omit-if-no-ref/
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emmc_clk: emmc-clk {
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rockchip,pins =
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/* emmc_clk */
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<4 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
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};
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/omit-if-no-ref/
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emmc_cmd: emmc-cmd {
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rockchip,pins =
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/* emmc_cmd */
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<4 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
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};
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};
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flash {
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/omit-if-no-ref/
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flash_pins: flash-pins {
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rockchip,pins =
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/* flash_trig_out */
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<2 RK_PA6 6 &pcfg_pull_none>;
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};
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};
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fspi {
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/omit-if-no-ref/
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fspi_pins: fspi-pins {
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rockchip,pins =
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/* fspi_clk */
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<4 RK_PB1 2 &pcfg_pull_up_drv_level_2>,
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/* fspi_d0 */
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<4 RK_PA4 2 &pcfg_pull_none>,
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/* fspi_d1 */
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<4 RK_PA3 2 &pcfg_pull_none>,
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/* fspi_d2 */
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<4 RK_PA2 2 &pcfg_pull_none>,
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/* fspi_d3 */
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<4 RK_PA6 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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fspi_cs0: fspi-cs0 {
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rockchip,pins =
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/* fspi_cs0n */
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<4 RK_PB0 2 &pcfg_pull_up>;
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};
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};
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hpmcu {
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/omit-if-no-ref/
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hpmcum0_pins: hpmcum0-pins {
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rockchip,pins =
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/* hpmcu_jtag_tck_m0 */
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<1 RK_PB2 3 &pcfg_pull_none>,
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/* hpmcu_jtag_tms_m0 */
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<1 RK_PB3 3 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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hpmcum1_pins: hpmcum1-pins {
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rockchip,pins =
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/* hpmcu_jtag_tck_m1 */
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<3 RK_PA7 4 &pcfg_pull_none>,
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/* hpmcu_jtag_tms_m1 */
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<3 RK_PA6 4 &pcfg_pull_none>;
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};
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};
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i2c0 {
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/omit-if-no-ref/
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i2c0m0_xfer: i2c0m0-xfer {
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rockchip,pins =
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/* i2c0_scl_m0 */
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<1 RK_PA3 2 &pcfg_pull_none_smt>,
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/* i2c0_sda_m0 */
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<1 RK_PA4 2 &pcfg_pull_none_smt>;
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};
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/omit-if-no-ref/
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i2c0m1_xfer: i2c0m1-xfer {
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rockchip,pins =
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/* i2c0_scl_m1 */
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<4 RK_PA1 4 &pcfg_pull_none_smt>,
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/* i2c0_sda_m1 */
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<4 RK_PA0 4 &pcfg_pull_none_smt>;
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};
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/omit-if-no-ref/
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i2c0m2_xfer: i2c0m2-xfer {
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rockchip,pins =
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/* i2c0_scl_m2 */
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<3 RK_PA4 3 &pcfg_pull_none_smt>,
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/* i2c0_sda_m2 */
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<3 RK_PA5 3 &pcfg_pull_none_smt>;
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};
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};
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i2c1 {
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/omit-if-no-ref/
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i2c1m0_xfer: i2c1m0-xfer {
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rockchip,pins =
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/* i2c1_scl_m0 */
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<0 RK_PA5 1 &pcfg_pull_none_smt>,
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/* i2c1_sda_m0 */
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<0 RK_PA6 1 &pcfg_pull_none_smt>;
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};
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/omit-if-no-ref/
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i2c1m1_xfer: i2c1m1-xfer {
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rockchip,pins =
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/* i2c1_scl_m1 */
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<2 RK_PB0 2 &pcfg_pull_none_smt>,
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/* i2c1_sda_m1 */
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<2 RK_PB1 2 &pcfg_pull_none_smt>;
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};
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};
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i2c2 {
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/omit-if-no-ref/
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i2c2m0_xfer: i2c2m0-xfer {
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rockchip,pins =
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/* i2c2_scl_m0 */
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<1 RK_PA0 2 &pcfg_pull_none_smt>,
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/* i2c2_sda_m0 */
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<1 RK_PA1 2 &pcfg_pull_none_smt>;
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};
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/omit-if-no-ref/
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i2c2m1_xfer: i2c2m1-xfer {
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rockchip,pins =
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/* i2c2_scl_m1 */
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<4 RK_PA7 4 &pcfg_pull_none_smt>,
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/* i2c2_sda_m1 */
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<4 RK_PA5 4 &pcfg_pull_none_smt>;
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};
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};
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i2c3 {
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/omit-if-no-ref/
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i2c3m0_xfer: i2c3m0-xfer {
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rockchip,pins =
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/* i2c3_scl_m0 */
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<2 RK_PA6 5 &pcfg_pull_none_smt>,
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/* i2c3_sda_m0 */
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<2 RK_PA7 5 &pcfg_pull_none_smt>;
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};
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/omit-if-no-ref/
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i2c3m1_xfer: i2c3m1-xfer {
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rockchip,pins =
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/* i2c3_scl_m1 */
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<1 RK_PD3 3 &pcfg_pull_none_smt>,
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/* i2c3_sda_m1 */
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<1 RK_PD2 3 &pcfg_pull_none_smt>;
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};
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/omit-if-no-ref/
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i2c3m2_xfer: i2c3m2-xfer {
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rockchip,pins =
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/* i2c3_scl_m2 */
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<3 RK_PD1 3 &pcfg_pull_none_smt>,
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/* i2c3_sda_m2 */
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<3 RK_PD2 3 &pcfg_pull_none_smt>;
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};
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};
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i2c4 {
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/omit-if-no-ref/
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i2c4m0_xfer: i2c4m0-xfer {
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rockchip,pins =
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/* i2c4_scl_m0 */
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<2 RK_PA1 5 &pcfg_pull_none_smt>,
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/* i2c4_sda_m0 */
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<2 RK_PA0 5 &pcfg_pull_none_smt>;
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};
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/omit-if-no-ref/
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i2c4m1_xfer: i2c4m1-xfer {
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rockchip,pins =
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/* i2c4_scl_m1 */
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<1 RK_PC2 4 &pcfg_pull_none_smt>,
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/* i2c4_sda_m1 */
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<1 RK_PC3 4 &pcfg_pull_none_smt>;
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};
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/omit-if-no-ref/
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i2c4m2_xfer: i2c4m2-xfer {
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rockchip,pins =
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/* i2c4_scl_m2 */
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<3 RK_PC7 3 &pcfg_pull_none_smt>,
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/* i2c4_sda_m2 */
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<3 RK_PD0 3 &pcfg_pull_none_smt>;
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};
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};
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i2s0 {
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/omit-if-no-ref/
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i2s0_pins: i2s0-pins {
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rockchip,pins =
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/* i2s0_lrck */
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<2 RK_PA1 2 &pcfg_pull_none>,
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/* i2s0_mclk */
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<2 RK_PA2 2 &pcfg_pull_none>,
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/* i2s0_sclk */
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<2 RK_PA0 2 &pcfg_pull_none>,
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/* i2s0_sdi0 */
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<2 RK_PA5 2 &pcfg_pull_none>,
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/* i2s0_sdo0 */
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<2 RK_PA4 2 &pcfg_pull_none>,
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/* i2s0_sdo1_sdi3 */
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<2 RK_PA7 2 &pcfg_pull_none>,
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/* i2s0_sdo2_sdi2 */
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<2 RK_PA6 2 &pcfg_pull_none>,
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/* i2s0_sdo3_sdi1 */
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<2 RK_PA3 2 &pcfg_pull_none>;
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};
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};
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lcd {
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/omit-if-no-ref/
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lcd_pins: lcd-pins {
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rockchip,pins =
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/* lcd_clk */
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<1 RK_PD3 1 &pcfg_pull_none_drv_level_4>,
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/* lcd_d0 */
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<1 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
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/* lcd_d1 */
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<1 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
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/* lcd_d2 */
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<1 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
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/* lcd_d3 */
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<1 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
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/* lcd_d4 */
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<1 RK_PC3 1 &pcfg_pull_none_drv_level_3>,
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/* lcd_d5 */
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<1 RK_PC2 1 &pcfg_pull_none_drv_level_3>,
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/* lcd_d6 */
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<1 RK_PC1 1 &pcfg_pull_none_drv_level_3>,
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/* lcd_d7 */
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<1 RK_PC0 1 &pcfg_pull_none_drv_level_3>,
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/* lcd_d8 */
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<2 RK_PA0 3 &pcfg_pull_none_drv_level_3>,
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/* lcd_d9 */
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<2 RK_PA1 3 &pcfg_pull_none_drv_level_3>,
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/* lcd_d10 */
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<2 RK_PA2 3 &pcfg_pull_none_drv_level_3>,
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/* lcd_d11 */
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<2 RK_PA3 3 &pcfg_pull_none_drv_level_3>,
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/* lcd_d12 */
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<2 RK_PA4 3 &pcfg_pull_none_drv_level_3>,
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/* lcd_d13 */
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<2 RK_PA5 3 &pcfg_pull_none_drv_level_3>,
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/* lcd_d14 */
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<2 RK_PA6 3 &pcfg_pull_none_drv_level_3>,
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/* lcd_d15 */
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<2 RK_PA7 3 &pcfg_pull_none_drv_level_3>,
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/* lcd_d16 */
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<2 RK_PB0 3 &pcfg_pull_none_drv_level_3>,
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/* lcd_d17 */
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<2 RK_PB1 3 &pcfg_pull_none_drv_level_3>,
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/* lcd_den */
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<1 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
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/* lcd_hsync */
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<1 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
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/* lcd_vsync */
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<1 RK_PD2 1 &pcfg_pull_none_drv_level_3>;
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};
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};
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lpmcu {
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/omit-if-no-ref/
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lpmcum0_pins: lpmcum0-pins {
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rockchip,pins =
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/* lpmcu_jtag_tck_m0 */
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<1 RK_PB2 4 &pcfg_pull_none>,
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/* lpmcu_jtag_tms_m0 */
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<1 RK_PB3 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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lpmcum1_pins: lpmcum1-pins {
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rockchip,pins =
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/* lpmcu_jtag_tck_m1 */
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<3 RK_PA4 4 &pcfg_pull_none>,
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/* lpmcu_jtag_tms_m1 */
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<3 RK_PA5 4 &pcfg_pull_none>;
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};
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};
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mipi {
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/omit-if-no-ref/
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mipi_pins: mipi-pins {
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rockchip,pins =
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/* mipi_lvds_ck0n */
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<3 RK_PC0 2 &pcfg_pull_none>,
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/* mipi_lvds_ck0p */
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<3 RK_PC1 2 &pcfg_pull_none>,
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/* mipi_lvds_ck1n */
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<3 RK_PB2 2 &pcfg_pull_none>,
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/* mipi_lvds_ck1p */
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<3 RK_PB3 2 &pcfg_pull_none>,
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/* mipi_lvds_d0n */
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<3 RK_PC2 2 &pcfg_pull_none>,
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/* mipi_lvds_d0p */
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<3 RK_PC3 2 &pcfg_pull_none>,
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/* mipi_lvds_d1n */
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<3 RK_PB6 2 &pcfg_pull_none>,
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/* mipi_lvds_d1p */
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<3 RK_PB7 2 &pcfg_pull_none>,
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/* mipi_lvds_d2n */
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<3 RK_PB4 2 &pcfg_pull_none>,
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/* mipi_lvds_d2p */
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<3 RK_PB5 2 &pcfg_pull_none>,
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/* mipi_lvds_d3n */
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<3 RK_PB0 2 &pcfg_pull_none>,
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/* mipi_lvds_d3p */
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<3 RK_PB1 2 &pcfg_pull_none>;
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};
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};
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pmic {
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/omit-if-no-ref/
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pmicm0_pins: pmicm0-pins {
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rockchip,pins =
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/* pmic_sleep_m0 */
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<0 RK_PA4 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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pmicm1_pins: pmicm1-pins {
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rockchip,pins =
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/* pmic_sleep_m1 */
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<0 RK_PA3 1 &pcfg_pull_none>;
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};
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};
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pmu {
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/omit-if-no-ref/
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pmu_pins: pmu-pins {
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rockchip,pins =
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/* pmu_debug */
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<1 RK_PA1 3 &pcfg_pull_none>;
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};
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};
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prelight {
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/omit-if-no-ref/
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prelight_pins: prelight-pins {
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rockchip,pins =
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/* prelight_trig_out */
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<2 RK_PA7 6 &pcfg_pull_none>;
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};
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};
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pwm0 {
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/omit-if-no-ref/
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pwm0m0_pins: pwm0m0-pins {
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rockchip,pins =
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/* pwm0_m0 */
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<1 RK_PA2 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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pwm0m1_pins: pwm0m1-pins {
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rockchip,pins =
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/* pwm0_m1 */
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<1 RK_PD2 6 &pcfg_pull_none>;
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};
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};
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pwm1 {
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/omit-if-no-ref/
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pwm1m0_pins: pwm1m0-pins {
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rockchip,pins =
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/* pwm1_m0 */
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<0 RK_PA4 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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pwm1m1_pins: pwm1m1-pins {
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rockchip,pins =
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/* pwm1_m1 */
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<4 RK_PC1 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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pwm1m2_pins: pwm1m2-pins {
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rockchip,pins =
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/* pwm1_m2 */
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<3 RK_PD3 2 &pcfg_pull_none>;
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};
|
|
};
|
|
|
|
pwm2 {
|
|
/omit-if-no-ref/
|
|
pwm2m0_pins: pwm2m0-pins {
|
|
rockchip,pins =
|
|
/* pwm2_m0 */
|
|
<0 RK_PA1 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm2m1_pins: pwm2m1-pins {
|
|
rockchip,pins =
|
|
/* pwm2_m1 */
|
|
<2 RK_PA6 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm2m2_pins: pwm2m2-pins {
|
|
rockchip,pins =
|
|
/* pwm2_m2 */
|
|
<1 RK_PC0 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm3 {
|
|
/omit-if-no-ref/
|
|
pwm3m0_pins: pwm3m0-pins {
|
|
rockchip,pins =
|
|
/* pwm3_ir_m0 */
|
|
<0 RK_PA2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm3m1_pins: pwm3m1-pins {
|
|
rockchip,pins =
|
|
/* pwm3_ir_m1 */
|
|
<1 RK_PB0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm3m2_pins: pwm3m2-pins {
|
|
rockchip,pins =
|
|
/* pwm3_ir_m2 */
|
|
<1 RK_PD0 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm4 {
|
|
/omit-if-no-ref/
|
|
pwm4m0_pins: pwm4m0-pins {
|
|
rockchip,pins =
|
|
/* pwm4_m0 */
|
|
<1 RK_PA1 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm4m1_pins: pwm4m1-pins {
|
|
rockchip,pins =
|
|
/* pwm4_m1 */
|
|
<2 RK_PA7 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm4m2_pins: pwm4m2-pins {
|
|
rockchip,pins =
|
|
/* pwm4_m2 */
|
|
<1 RK_PC1 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm5 {
|
|
/omit-if-no-ref/
|
|
pwm5m0_pins: pwm5m0-pins {
|
|
rockchip,pins =
|
|
/* pwm5_m0 */
|
|
<0 RK_PA5 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm5m1_pins: pwm5m1-pins {
|
|
rockchip,pins =
|
|
/* pwm5_m1 */
|
|
<2 RK_PB0 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm5m2_pins: pwm5m2-pins {
|
|
rockchip,pins =
|
|
/* pwm5_m2 */
|
|
<1 RK_PC2 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm6 {
|
|
/omit-if-no-ref/
|
|
pwm6m0_pins: pwm6m0-pins {
|
|
rockchip,pins =
|
|
/* pwm6_m0 */
|
|
<0 RK_PA6 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm6m1_pins: pwm6m1-pins {
|
|
rockchip,pins =
|
|
/* pwm6_m1 */
|
|
<2 RK_PB1 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm6m2_pins: pwm6m2-pins {
|
|
rockchip,pins =
|
|
/* pwm6_m2 */
|
|
<1 RK_PC3 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm7 {
|
|
/omit-if-no-ref/
|
|
pwm7m0_pins: pwm7m0-pins {
|
|
rockchip,pins =
|
|
/* pwm7_ir_m0 */
|
|
<1 RK_PA0 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm7m1_pins: pwm7m1-pins {
|
|
rockchip,pins =
|
|
/* pwm7_ir_m1 */
|
|
<1 RK_PB1 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm7m2_pins: pwm7m2-pins {
|
|
rockchip,pins =
|
|
/* pwm7_ir_m2 */
|
|
<3 RK_PC6 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm8 {
|
|
/omit-if-no-ref/
|
|
pwm8m0_pins: pwm8m0-pins {
|
|
rockchip,pins =
|
|
/* pwm8_m0 */
|
|
<3 RK_PA3 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm8m1_pins: pwm8m1-pins {
|
|
rockchip,pins =
|
|
/* pwm8_m1 */
|
|
<1 RK_PC4 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm9 {
|
|
/omit-if-no-ref/
|
|
pwm9m0_pins: pwm9m0-pins {
|
|
rockchip,pins =
|
|
/* pwm9_m0 */
|
|
<3 RK_PA2 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm9m1_pins: pwm9m1-pins {
|
|
rockchip,pins =
|
|
/* pwm9_m1 */
|
|
<1 RK_PC5 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm10 {
|
|
/omit-if-no-ref/
|
|
pwm10m0_pins: pwm10m0-pins {
|
|
rockchip,pins =
|
|
/* pwm10_m0 */
|
|
<3 RK_PA4 5 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm10m1_pins: pwm10m1-pins {
|
|
rockchip,pins =
|
|
/* pwm10_m1 */
|
|
<1 RK_PC6 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm10m2_pins: pwm10m2-pins {
|
|
rockchip,pins =
|
|
/* pwm10_m2 */
|
|
<1 RK_PD1 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm11 {
|
|
/omit-if-no-ref/
|
|
pwm11m0_pins: pwm11m0-pins {
|
|
rockchip,pins =
|
|
/* pwm11_ir_m0 */
|
|
<3 RK_PA5 5 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm11m1_pins: pwm11m1-pins {
|
|
rockchip,pins =
|
|
/* pwm11_ir_m1 */
|
|
<1 RK_PC7 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
pwm11m2_pins: pwm11m2-pins {
|
|
rockchip,pins =
|
|
/* pwm11_ir_m2 */
|
|
<1 RK_PD3 5 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
rtc {
|
|
/omit-if-no-ref/
|
|
rtc_pins: rtc-pins {
|
|
rockchip,pins =
|
|
/* rtc_clko */
|
|
<0 RK_PA0 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sdmmc0 {
|
|
/omit-if-no-ref/
|
|
sdmmc0_bus4: sdmmc0-bus4 {
|
|
rockchip,pins =
|
|
/* sdmmc0_d0 */
|
|
<3 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc0_d1 */
|
|
<3 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc0_d2 */
|
|
<3 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc0_d3 */
|
|
<3 RK_PA6 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc0_clk: sdmmc0-clk {
|
|
rockchip,pins =
|
|
/* sdmmc0_clk */
|
|
<3 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc0_cmd: sdmmc0-cmd {
|
|
rockchip,pins =
|
|
/* sdmmc0_cmd */
|
|
<3 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc0_det: sdmmc0-det {
|
|
rockchip,pins =
|
|
/* sdmmc0_det */
|
|
<3 RK_PA1 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc0_idle_pins: sdmmc0-idle-pins {
|
|
rockchip,pins =
|
|
<3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
sdmmc1 {
|
|
/omit-if-no-ref/
|
|
sdmmc1m0_bus1: sdmmc1m0-bus1 {
|
|
rockchip,pins =
|
|
/* sdmmc1_d0_m0 */
|
|
<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc1m0_bus4: sdmmc1m0-bus4 {
|
|
rockchip,pins =
|
|
/* sdmmc1_d0_m0 */
|
|
<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc1_d1_m0 */
|
|
<2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc1_d2_m0 */
|
|
<2 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc1_d3_m0 */
|
|
<2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc1m0_clk: sdmmc1m0-clk {
|
|
rockchip,pins =
|
|
/* sdmmc1_clk_m0 */
|
|
<2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc1m0_cmd: sdmmc1m0-cmd {
|
|
rockchip,pins =
|
|
/* sdmmc1_cmd_m0 */
|
|
<2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc1m0_idle_pins: sdmmc1m0-idle-pins {
|
|
rockchip,pins =
|
|
<2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc1m1_bus4: sdmmc1m1-bus4 {
|
|
rockchip,pins =
|
|
/* sdmmc1_d0_m1 */
|
|
<1 RK_PC1 5 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc1_d1_m1 */
|
|
<1 RK_PC0 5 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc1_d2_m1 */
|
|
<1 RK_PC5 5 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc1_d3_m1 */
|
|
<1 RK_PC4 5 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc1m1_clk: sdmmc1m1-clk {
|
|
rockchip,pins =
|
|
/* sdmmc1_clk_m1 */
|
|
<1 RK_PC2 5 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc1m1_cmd: sdmmc1m1-cmd {
|
|
rockchip,pins =
|
|
/* sdmmc1_cmd_m1 */
|
|
<1 RK_PC3 5 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc1m1_idle_pins: sdmmc1m1-idle-pins {
|
|
rockchip,pins =
|
|
<1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
/omit-if-no-ref/
|
|
spi0m0_pins: spi0m0-pins {
|
|
rockchip,pins =
|
|
/* spi0_clk_m0 */
|
|
<1 RK_PC1 4 &pcfg_pull_none>,
|
|
/* spi0_miso_m0 */
|
|
<1 RK_PC3 6 &pcfg_pull_none>,
|
|
/* spi0_mosi_m0 */
|
|
<1 RK_PC2 6 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
spi0m0_cs0: spi0m0-cs0 {
|
|
rockchip,pins =
|
|
/* spi0_cs0n_m0 */
|
|
<1 RK_PC0 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
spi0m0_cs1: spi0m0-cs1 {
|
|
rockchip,pins =
|
|
/* spi0_cs1n_m0 */
|
|
<1 RK_PD2 5 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spi1 {
|
|
/omit-if-no-ref/
|
|
spi1m0_pins: spi1m0-pins {
|
|
rockchip,pins =
|
|
/* spi1_clk_m0 */
|
|
<4 RK_PA7 2 &pcfg_pull_none>,
|
|
/* spi1_miso_m0 */
|
|
<4 RK_PA0 2 &pcfg_pull_none>,
|
|
/* spi1_mosi_m0 */
|
|
<4 RK_PA1 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
spi1m0_cs0: spi1m0-cs0 {
|
|
rockchip,pins =
|
|
/* spi1_cs0n_m0 */
|
|
<4 RK_PA5 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
spi1m0_cs1: spi1m0-cs1 {
|
|
rockchip,pins =
|
|
/* spi1_cs1n_m0 */
|
|
<1 RK_PB1 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
/omit-if-no-ref/
|
|
uart0m0_xfer: uart0m0-xfer {
|
|
rockchip,pins =
|
|
/* uart0_rx_m0 */
|
|
<0 RK_PA0 1 &pcfg_pull_up>,
|
|
/* uart0_tx_m0 */
|
|
<0 RK_PA1 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart0m1_xfer: uart0m1-xfer {
|
|
rockchip,pins =
|
|
/* uart0_rx_m1 */
|
|
<2 RK_PB0 1 &pcfg_pull_up>,
|
|
/* uart0_tx_m1 */
|
|
<2 RK_PB1 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart0m1_ctsn: uart0m1-ctsn {
|
|
rockchip,pins =
|
|
/* uart0m1_ctsn */
|
|
<2 RK_PA7 1 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart0m1_rtsn: uart0m1-rtsn {
|
|
rockchip,pins =
|
|
/* uart0m1_rtsn */
|
|
<2 RK_PA6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart0m2_xfer: uart0m2-xfer {
|
|
rockchip,pins =
|
|
/* uart0_rx_m2 */
|
|
<4 RK_PA0 3 &pcfg_pull_up>,
|
|
/* uart0_tx_m2 */
|
|
<4 RK_PA1 3 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
/omit-if-no-ref/
|
|
uart1m0_xfer: uart1m0-xfer {
|
|
rockchip,pins =
|
|
/* uart1_rx_m0 */
|
|
<1 RK_PA4 1 &pcfg_pull_up>,
|
|
/* uart1_tx_m0 */
|
|
<1 RK_PA3 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart1m0_ctsn: uart1m0-ctsn {
|
|
rockchip,pins =
|
|
/* uart1m0_ctsn */
|
|
<0 RK_PA6 2 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart1m0_rtsn: uart1m0-rtsn {
|
|
rockchip,pins =
|
|
/* uart1m0_rtsn */
|
|
<0 RK_PA5 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart1m1_xfer: uart1m1-xfer {
|
|
rockchip,pins =
|
|
/* uart1_rx_m1 */
|
|
<2 RK_PA5 4 &pcfg_pull_up>,
|
|
/* uart1_tx_m1 */
|
|
<2 RK_PA4 4 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart1m1_ctsn: uart1m1-ctsn {
|
|
rockchip,pins =
|
|
/* uart1m1_ctsn */
|
|
<2 RK_PA0 4 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart1m1_rtsn: uart1m1-rtsn {
|
|
rockchip,pins =
|
|
/* uart1m1_rtsn */
|
|
<2 RK_PA1 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart1m2_xfer: uart1m2-xfer {
|
|
rockchip,pins =
|
|
/* uart1_rx_m2 */
|
|
<4 RK_PA7 3 &pcfg_pull_up>,
|
|
/* uart1_tx_m2 */
|
|
<4 RK_PA5 3 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
/omit-if-no-ref/
|
|
uart2m0_xfer: uart2m0-xfer {
|
|
rockchip,pins =
|
|
/* uart2_rx_m0 */
|
|
<3 RK_PA3 2 &pcfg_pull_up>,
|
|
/* uart2_tx_m0 */
|
|
<3 RK_PA2 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart2m1_xfer: uart2m1-xfer {
|
|
rockchip,pins =
|
|
/* uart2_rx_m1 */
|
|
<1 RK_PB3 2 &pcfg_pull_up>,
|
|
/* uart2_tx_m1 */
|
|
<1 RK_PB2 2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart3 {
|
|
/omit-if-no-ref/
|
|
uart3m0_xfer: uart3m0-xfer {
|
|
rockchip,pins =
|
|
/* uart3_rx_m0 */
|
|
<1 RK_PA1 1 &pcfg_pull_up>,
|
|
/* uart3_tx_m0 */
|
|
<1 RK_PA0 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart3m1_xfer: uart3m1-xfer {
|
|
rockchip,pins =
|
|
/* uart3_rx_m1 */
|
|
<1 RK_PD1 5 &pcfg_pull_up>,
|
|
/* uart3_tx_m1 */
|
|
<1 RK_PD0 5 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart4 {
|
|
/omit-if-no-ref/
|
|
uart4m0_xfer: uart4m0-xfer {
|
|
rockchip,pins =
|
|
/* uart4_rx_m0 */
|
|
<1 RK_PB0 1 &pcfg_pull_up>,
|
|
/* uart4_tx_m0 */
|
|
<1 RK_PB1 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart4m1_xfer: uart4m1-xfer {
|
|
rockchip,pins =
|
|
/* uart4_rx_m1 */
|
|
<1 RK_PC4 4 &pcfg_pull_up>,
|
|
/* uart4_tx_m1 */
|
|
<1 RK_PC5 4 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart4m1_ctsn: uart4m1-ctsn {
|
|
rockchip,pins =
|
|
/* uart4m1_ctsn */
|
|
<1 RK_PC7 4 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart4m1_rtsn: uart4m1-rtsn {
|
|
rockchip,pins =
|
|
/* uart4m1_rtsn */
|
|
<1 RK_PC6 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart5 {
|
|
/omit-if-no-ref/
|
|
uart5m0_xfer: uart5m0-xfer {
|
|
rockchip,pins =
|
|
/* uart5_rx_m0 */
|
|
<3 RK_PA7 2 &pcfg_pull_up>,
|
|
/* uart5_tx_m0 */
|
|
<3 RK_PA6 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart5m0_ctsn: uart5m0-ctsn {
|
|
rockchip,pins =
|
|
/* uart5m0_ctsn */
|
|
<3 RK_PA5 2 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart5m0_rtsn: uart5m0-rtsn {
|
|
rockchip,pins =
|
|
/* uart5m0_rtsn */
|
|
<3 RK_PA4 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart5m1_xfer: uart5m1-xfer {
|
|
rockchip,pins =
|
|
/* uart5_rx_m1 */
|
|
<1 RK_PD2 4 &pcfg_pull_up>,
|
|
/* uart5_tx_m1 */
|
|
<1 RK_PD3 4 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart5m1_ctsn: uart5m1-ctsn {
|
|
rockchip,pins =
|
|
/* uart5m1_ctsn */
|
|
<1 RK_PD1 4 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart5m1_rtsn: uart5m1-rtsn {
|
|
rockchip,pins =
|
|
/* uart5m1_rtsn */
|
|
<1 RK_PD0 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart5m2_xfer: uart5m2-xfer {
|
|
rockchip,pins =
|
|
/* uart5_rx_m2 */
|
|
<3 RK_PD0 2 &pcfg_pull_up>,
|
|
/* uart5_tx_m2 */
|
|
<3 RK_PC7 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart5m2_ctsn: uart5m2-ctsn {
|
|
rockchip,pins =
|
|
/* uart5m2_ctsn */
|
|
<3 RK_PD2 2 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart5m2_rtsn: uart5m2-rtsn {
|
|
rockchip,pins =
|
|
/* uart5m2_rtsn */
|
|
<3 RK_PD1 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
vicap {
|
|
/omit-if-no-ref/
|
|
vicapm0_pins: vicapm0-pins {
|
|
rockchip,pins =
|
|
/* vicap_clkin_m0 */
|
|
<3 RK_PC2 1 &pcfg_pull_none>,
|
|
/* vicap_d0_m0 */
|
|
<3 RK_PB0 1 &pcfg_pull_none>,
|
|
/* vicap_d1_m0 */
|
|
<3 RK_PB1 1 &pcfg_pull_none>,
|
|
/* vicap_d2_m0 */
|
|
<3 RK_PB2 1 &pcfg_pull_none>,
|
|
/* vicap_d3_m0 */
|
|
<3 RK_PB3 1 &pcfg_pull_none>,
|
|
/* vicap_d4_m0 */
|
|
<3 RK_PB4 1 &pcfg_pull_none>,
|
|
/* vicap_d5_m0 */
|
|
<3 RK_PB5 1 &pcfg_pull_none>,
|
|
/* vicap_d6_m0 */
|
|
<3 RK_PB6 1 &pcfg_pull_none>,
|
|
/* vicap_d7_m0 */
|
|
<3 RK_PB7 1 &pcfg_pull_none>,
|
|
/* vicap_d8_m0 */
|
|
<3 RK_PC0 1 &pcfg_pull_none>,
|
|
/* vicap_d9_m0 */
|
|
<3 RK_PC1 1 &pcfg_pull_none>,
|
|
/* vicap_hsync_m0 */
|
|
<3 RK_PC3 1 &pcfg_pull_none>,
|
|
/* vicap_vsync_m0 */
|
|
<3 RK_PC5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
vicapm1_pins: vicapm1-pins {
|
|
rockchip,pins =
|
|
/* vicap_clkin_m1 */
|
|
<1 RK_PD0 2 &pcfg_pull_none>,
|
|
/* vicap_d0_m1 */
|
|
<1 RK_PA2 3 &pcfg_pull_none>,
|
|
/* vicap_d1_m1 */
|
|
<1 RK_PB1 4 &pcfg_pull_none>,
|
|
/* vicap_d2_m1 */
|
|
<1 RK_PC0 2 &pcfg_pull_none>,
|
|
/* vicap_d3_m1 */
|
|
<1 RK_PC1 2 &pcfg_pull_none>,
|
|
/* vicap_d4_m1 */
|
|
<1 RK_PC2 2 &pcfg_pull_none>,
|
|
/* vicap_d5_m1 */
|
|
<1 RK_PC3 2 &pcfg_pull_none>,
|
|
/* vicap_d6_m1 */
|
|
<1 RK_PC4 2 &pcfg_pull_none>,
|
|
/* vicap_d7_m1 */
|
|
<1 RK_PC5 2 &pcfg_pull_none>,
|
|
/* vicap_d8_m1 */
|
|
<1 RK_PC6 2 &pcfg_pull_none>,
|
|
/* vicap_d9_m1 */
|
|
<1 RK_PC7 2 &pcfg_pull_none>,
|
|
/* vicap_hsync_m1 */
|
|
<1 RK_PD1 2 &pcfg_pull_none>,
|
|
/* vicap_vsync_m1 */
|
|
<1 RK_PD2 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
vicap_d10: vicap-d10 {
|
|
rockchip,pins =
|
|
/* vicap_d10 */
|
|
<3 RK_PC6 1 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
vicap_d11: vicap-d11 {
|
|
rockchip,pins =
|
|
/* vicap_d11 */
|
|
<3 RK_PC7 1 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
vicap_d12: vicap-d12 {
|
|
rockchip,pins =
|
|
/* vicap_d12 */
|
|
<3 RK_PD0 1 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
vicap_d13: vicap-d13 {
|
|
rockchip,pins =
|
|
/* vicap_d13 */
|
|
<3 RK_PD1 1 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
vicap_d14: vicap-d14 {
|
|
rockchip,pins =
|
|
/* vicap_d14 */
|
|
<3 RK_PD2 1 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
vicap_d15: vicap-d15 {
|
|
rockchip,pins =
|
|
/* vicap_d15 */
|
|
<3 RK_PD3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/*
|
|
* This part is edited handly.
|
|
*/
|
|
&pinctrl {
|
|
vicap {
|
|
/omit-if-no-ref/
|
|
vicap_clkout_m0: vicap-clkout-m0 {
|
|
rockchip,pins =
|
|
/* vicap_clkout_m0 */
|
|
<3 RK_PC4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
vicap_clkout_m1: vicap-clkout-m1 {
|
|
rockchip,pins =
|
|
/* vicap_clkout_m1 */
|
|
<1 RK_PD3 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
mipi {
|
|
/omit-if-no-ref/
|
|
mipi_refclk_out0: mipi-refclk-out0 {
|
|
rockchip,pins =
|
|
/* mipi_refclk_out0 */
|
|
<3 RK_PC4 2 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
mipi_refclk_out1: mipi-refclk-out1 {
|
|
rockchip,pins =
|
|
/* mipi_refclk_out1 */
|
|
<3 RK_PC6 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
lcd {
|
|
/omit-if-no-ref/
|
|
bt1120_pins: bt1120-pins {
|
|
rockchip,pins =
|
|
/* lcd_clk */
|
|
<1 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d0 */
|
|
<1 RK_PC7 1 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d1 */
|
|
<1 RK_PC6 1 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d2 */
|
|
<1 RK_PC5 1 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d3 */
|
|
<1 RK_PC4 1 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d4 */
|
|
<1 RK_PC3 1 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d5 */
|
|
<1 RK_PC2 1 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d6 */
|
|
<1 RK_PC1 1 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d7 */
|
|
<1 RK_PC0 1 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d8 */
|
|
<2 RK_PA0 3 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d9 */
|
|
<2 RK_PA1 3 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d10 */
|
|
<2 RK_PA2 3 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d11 */
|
|
<2 RK_PA3 3 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d12 */
|
|
<2 RK_PA4 3 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d13 */
|
|
<2 RK_PA5 3 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d14 */
|
|
<2 RK_PA6 3 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d15 */
|
|
<2 RK_PA7 3 &pcfg_pull_none_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
bt656_pins: bt656-pins {
|
|
rockchip,pins =
|
|
/* lcd_clk */
|
|
<1 RK_PD3 1 &pcfg_pull_none_drv_level_2>,
|
|
/* lcd_d0 */
|
|
<1 RK_PC7 1 &pcfg_pull_none_drv_level_1>,
|
|
/* lcd_d1 */
|
|
<1 RK_PC6 1 &pcfg_pull_none_drv_level_1>,
|
|
/* lcd_d2 */
|
|
<1 RK_PC5 1 &pcfg_pull_none_drv_level_1>,
|
|
/* lcd_d3 */
|
|
<1 RK_PC4 1 &pcfg_pull_none_drv_level_1>,
|
|
/* lcd_d4 */
|
|
<1 RK_PC3 1 &pcfg_pull_none_drv_level_1>,
|
|
/* lcd_d5 */
|
|
<1 RK_PC2 1 &pcfg_pull_none_drv_level_1>,
|
|
/* lcd_d6 */
|
|
<1 RK_PC1 1 &pcfg_pull_none_drv_level_1>,
|
|
/* lcd_d7 */
|
|
<1 RK_PC0 1 &pcfg_pull_none_drv_level_1>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
rgb3x8_pins: rgb3x8-pins {
|
|
rockchip,pins =
|
|
/* lcd_clk */
|
|
<1 RK_PD3 1 &pcfg_pull_none_drv_level_4>,
|
|
/* lcd_d0 */
|
|
<1 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d1 */
|
|
<1 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d2 */
|
|
<1 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d3 */
|
|
<1 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d4 */
|
|
<1 RK_PC3 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d5 */
|
|
<1 RK_PC2 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d6 */
|
|
<1 RK_PC1 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d7 */
|
|
<1 RK_PC0 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_den */
|
|
<1 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_hsync */
|
|
<1 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_vsync */
|
|
<1 RK_PD2 1 &pcfg_pull_none_drv_level_3>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
rgb565_pins: rgb565-pins {
|
|
rockchip,pins =
|
|
/* lcd_clk */
|
|
<1 RK_PD3 1 &pcfg_pull_none_drv_level_4>,
|
|
/* lcd_d0 */
|
|
<1 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d1 */
|
|
<1 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d2 */
|
|
<1 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d3 */
|
|
<1 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d4 */
|
|
<1 RK_PC3 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d5 */
|
|
<1 RK_PC2 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d6 */
|
|
<1 RK_PC1 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d7 */
|
|
<1 RK_PC0 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d8 */
|
|
<2 RK_PA0 3 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d9 */
|
|
<2 RK_PA1 3 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d10 */
|
|
<2 RK_PA2 3 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d11 */
|
|
<2 RK_PA3 3 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d12 */
|
|
<2 RK_PA4 3 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d13 */
|
|
<2 RK_PA5 3 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d14 */
|
|
<2 RK_PA6 3 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_d15 */
|
|
<2 RK_PA7 3 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_den */
|
|
<1 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_hsync */
|
|
<1 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
|
|
/* lcd_vsync */
|
|
<1 RK_PD2 1 &pcfg_pull_none_drv_level_3>;
|
|
};
|
|
};
|
|
};
|