508 lines
13 KiB
Plaintext
508 lines
13 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*/
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#include "rk3502.dtsi"
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/ {
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compatible = "rockchip,rk3506";
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aliases {
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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};
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display_subsystem: display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vop_out>;
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status = "disabled";
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route {
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route_dsi: route-dsi {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vop_out_dsi>;
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};
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route_rgb: route-rgb {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vop_out_rgb>;
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};
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};
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};
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can0: can@ff320000 {
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compatible = "rockchip,rk3506-canfd", "rockchip,rk3576-canfd";
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reg = <0xff320000 0x1000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru CLK_CAN0>, <&cru HCLK_CAN0>;
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clock-names = "baudclk", "apb_pclk";
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resets = <&cru SRST_CAN0>, <&cru SRST_H_CAN0>;
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reset-names = "can", "can-apb";
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assigned-clocks = <&cru CLK_CAN0>;
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assigned-clock-rates = <300000000>;
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status = "disabled";
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};
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can1: can@ff330000 {
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compatible = "rockchip,rk3506-canfd", "rockchip,rk3576-canfd";
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reg = <0xff330000 0x1000>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru CLK_CAN1>, <&cru HCLK_CAN1>;
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clock-names = "baudclk", "apb_pclk";
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resets = <&cru SRST_CAN1>, <&cru SRST_H_CAN1>;
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reset-names = "can", "can-apb";
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assigned-clocks = <&cru CLK_CAN1>;
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assigned-clock-rates = <300000000>;
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status = "disabled";
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};
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gmac0: ethernet@ff4c8000 {
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compatible = "rockchip,rk3506-gmac", "snps,dwmac-4.20a";
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reg = <0xff4c8000 0x2000>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq", "eth_wake_irq";
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rockchip,grf = <&grf>;
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clocks = <&cru CLK_MAC0>, <&cru CLK_MAC0_PTP>,
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<&cru PCLK_MAC0>, <&cru ACLK_MAC0>;
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clock-names = "stmmaceth", "ptp_ref",
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"pclk_mac", "aclk_mac";
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resets = <&cru SRST_A_MAC0>;
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reset-names = "stmmaceth";
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assigned-clocks = <&cru CLK_MAC0_PTP>;
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assigned-clock-rates = <62500000>;
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snps,mixed-burst;
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snps,tso;
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snps,axi-config = <&gmac0_stmmac_axi_setup>;
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snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
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snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
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phy-mode = "rmii";
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status = "disabled";
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mdio0: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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};
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gmac0_stmmac_axi_setup: stmmac-axi-config {
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snps,wr_osr_lmt = <4>;
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snps,rd_osr_lmt = <8>;
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snps,blen = <0 0 0 0 16 8 4>;
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};
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gmac0_mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <1>;
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queue0 {
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status = "okay";
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};
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};
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gmac0_mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <1>;
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queue0 {
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status = "okay";
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};
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};
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};
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gmac1: ethernet@ff4d0000 {
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compatible = "rockchip,rk3506-gmac", "snps,dwmac-4.20a";
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reg = <0xff4d0000 0x2000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq", "eth_wake_irq";
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rockchip,grf = <&grf>;
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clocks = <&cru CLK_MAC1>, <&cru CLK_MAC1_PTP>,
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<&cru PCLK_MAC1>, <&cru ACLK_MAC1>;
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clock-names = "stmmaceth", "ptp_ref",
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"pclk_mac", "aclk_mac";
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resets = <&cru SRST_A_MAC1>;
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reset-names = "stmmaceth";
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assigned-clocks = <&cru CLK_MAC1_PTP>;
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assigned-clock-rates = <62500000>;
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snps,mixed-burst;
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snps,tso;
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snps,axi-config = <&gmac1_stmmac_axi_setup>;
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snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
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snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
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phy-mode = "rmii";
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status = "disabled";
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mdio1: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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};
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gmac1_stmmac_axi_setup: stmmac-axi-config {
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snps,wr_osr_lmt = <4>;
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snps,rd_osr_lmt = <8>;
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snps,blen = <0 0 0 0 16 8 4>;
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};
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gmac1_mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <1>;
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queue0 {
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status = "okay";
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};
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};
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gmac1_mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <1>;
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queue0 {
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status = "okay";
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};
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};
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};
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vop: vop@ff600000 {
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compatible = "rockchip,rk3506-vop";
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reg = <0xff600000 0x200>, <0xff600a00 0x400>;
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reg-names = "regs", "gamma_lut";
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rockchip,grf = <&grf>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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status = "disabled";
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vop_out: port {
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#address-cells = <1>;
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#size-cells = <0>;
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vop_out_rgb: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&rgb_in_vop>;
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};
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vop_out_dsi: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&dsi_in_vop>;
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};
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};
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};
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dsi: dsi@ff640000 {
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compatible = "rockchip,rk3506-mipi-dsi";
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reg = <0xff640000 0x10000>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_DSI_HOST>;
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clock-names = "pclk";
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resets = <&cru SRST_P_DSI_HOST>;
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reset-names = "apb";
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phys = <&dsi_dphy>;
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phy-names = "dphy";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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dsi_in: port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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dsi_in_vop: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vop_out_dsi>;
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status = "disabled";
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};
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};
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};
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};
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dsi_dphy: phy@ff670000 {
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compatible = "rockchip,rk3506-dsi-dphy";
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reg = <0xff670000 0x10000>,
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<0xff640000 0x10000>;
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reg-names = "phy", "host";
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clocks = <&cru CLK_REF_DPHY_TOP>,
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<&cru PCLK_DPHY>, <&cru PCLK_DSI_HOST>;
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clock-names = "ref", "pclk", "pclk_host";
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#clock-cells = <0>;
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resets = <&cru SRST_P_DPHY>;
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reset-names = "apb";
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#phy-cells = <0>;
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status = "disabled";
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};
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dsmc_lb_slave: dsmc-lb-slave@ff880000 {
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compatible = "rockchip,rk3506-dsmc-lb-slave";
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reg = <0xff880000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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rockchip,grf = <&grf>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&cru SRST_DSMC_SLV>, <&cru SRST_A_DSMC_SLV>,
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<&cru SRST_H_DSMC_SLV>;
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reset-names = "dsmc_slv", "a_dsmc_slv", "h_dsmc_slv";
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clocks = <&cru ACLK_DSMC_SLV>,
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<&cru HCLK_DSMC_SLV>;
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clock-names = "aclk_dsmc_slv", "hclk_dsmc_slv";
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pinctrl-names = "default", "active";
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pinctrl-0 = <&dsmc_slv_csn0_pull_pins
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&dsmc_slv_bus8_pins>;
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pinctrl-1 = <&dsmc_slv_csn0_pins>;
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status = "disabled";
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};
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dsmc: dsmc@ff8b0000 {
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compatible = "rockchip,rk3506-dsmc";
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reg = <0xff8b0000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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rockchip,grf = <&grf>;
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interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&cru SRST_A_DSMC>, <&cru SRST_P_DSMC>;
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reset-names = "dsmc", "apb";
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clocks = <&cru CLK_DSMC>,
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<&cru ACLK_DSMC>,
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<&cru PCLK_DSMC>,
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<&cru CLK_DSMC>;
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clock-names = "clk_sys", "aclk_dsmc", "pclk", "aclk_root";
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clock-frequency = <100000000>;
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dmas = <&dmac0 2 0xff288078 0x80000000 0xff2880a8 0x00300000>,
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<&dmac0 3 0xff288078 0x40000000 0xff2880a8 0x00c00000>;
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// dmas = <&dmac0 8 0xff288078 0x80008000 0xff2880ac 0x00030000>,
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// <&dmac0 10 0xff288078 0x40004000 0xff2880ac 0x00300000>;
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dma-names = "req0", "req1";
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pinctrl-names = "default", "active" ,"lb-slave";
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pinctrl-0 = <&dsmc_csn_pull_pins
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&dsmc_bus16_pins
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&dsmc_clk_pins>;
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pinctrl-1 = <&dsmc_csn_pins>;
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pinctrl-2 = <&dsmc_int_pins>;
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status = "disabled";
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slave {
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rockchip,dqs-dll = <0x20 0x20
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0x20 0x20
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0x20 0x20
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0x20 0x20>;
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rockchip,ranges = <0x0 0xc0000000 0x0 0x2000000>;
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rockchip,slave-dev = <&dsmc_slave>;
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};
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};
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dsmc_slave: dsmc-slave {
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compatible = "rockchip,dsmc-slave";
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rockchip,clk-mode = <0>;
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status = "disabled";
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psram {
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dsmc_psram0: psram0 {
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status = "disabled";
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};
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dsmc_psram1: psram1 {
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status = "disabled";
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};
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dsmc_psram2: psram2 {
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status = "disabled";
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};
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dsmc_psram3: psram3 {
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status = "disabled";
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};
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};
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lb-slave {
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dsmc_lb_slave0: lb-slave0 {
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rockchip,mtr-timing = <1 0 0 0 0 0 2 2>;
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rockchip,int-en = <0x0>;
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status = "disabled";
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dsmc_p0_region: region {
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dsmc_p0_region0: region0 {
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rockchip,attribute = "Merged FIFO";
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rockchip,ca-addr-width = <0>;
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rockchip,dummy-clk-num = <1>;
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rockchip,cs0-be-ctrled = <0>;
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rockchip,cs0-ctrl = <0>;
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status = "disabled";
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};
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dsmc_p0_region1: region1 {
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rockchip,attribute = "No-Merge FIFO";
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rockchip,ca-addr-width = <0>;
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rockchip,dummy-clk-num = <1>;
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rockchip,cs0-be-ctrled = <0>;
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rockchip,cs0-ctrl = <0>;
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status = "disabled";
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};
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dsmc_p0_region2: region2 {
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rockchip,attribute = "DPRA";
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rockchip,ca-addr-width = <0>;
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rockchip,dummy-clk-num = <1>;
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rockchip,cs0-be-ctrled = <0>;
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rockchip,cs0-ctrl = <0>;
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status = "disabled";
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};
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dsmc_p0_region3: region3 {
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rockchip,attribute = "Register";
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rockchip,ca-addr-width = <0>;
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rockchip,dummy-clk-num = <1>;
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rockchip,cs0-be-ctrled = <0>;
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rockchip,cs0-ctrl = <0>;
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status = "disabled";
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};
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};
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};
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dsmc_lb_slave1: lb-slave1 {
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rockchip,mtr-timing = <1 0 0 0 0 0 2 2>;
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rockchip,int-en = <0x1>;
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status = "disabled";
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dsmc_p1_region: region {
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dsmc_p1_region0: region0 {
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rockchip,attribute = "Merged FIFO";
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rockchip,ca-addr-width = <0>;
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rockchip,dummy-clk-num = <1>;
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rockchip,cs0-be-ctrled = <0>;
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rockchip,cs0-ctrl = <0>;
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status = "disabled";
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};
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dsmc_p1_region1: region1 {
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rockchip,attribute = "No-Merge FIFO";
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rockchip,ca-addr-width = <0>;
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rockchip,dummy-clk-num = <1>;
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rockchip,cs0-be-ctrled = <0>;
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rockchip,cs0-ctrl = <0>;
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status = "disabled";
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};
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dsmc_p1_region2: region2 {
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rockchip,attribute = "DPRA";
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rockchip,ca-addr-width = <0>;
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rockchip,dummy-clk-num = <1>;
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rockchip,cs0-be-ctrled = <0>;
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rockchip,cs0-ctrl = <0>;
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status = "disabled";
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};
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dsmc_p1_region3: region3 {
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rockchip,attribute = "Register";
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rockchip,ca-addr-width = <0>;
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rockchip,dummy-clk-num = <1>;
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rockchip,cs0-be-ctrled = <0>;
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rockchip,cs0-ctrl = <0>;
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status = "disabled";
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};
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};
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};
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dsmc_lb_slave2: lb-slave2 {
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rockchip,mtr-timing = <1 0 0 0 0 0 2 2>;
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rockchip,int-en = <0x2>;
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status = "disabled";
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dsmc_p2_region: region {
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dsmc_p2_region0: region0 {
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rockchip,attribute = "Merged FIFO";
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rockchip,ca-addr-width = <0>;
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rockchip,dummy-clk-num = <1>;
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rockchip,cs0-be-ctrled = <0>;
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rockchip,cs0-ctrl = <0>;
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status = "disabled";
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};
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dsmc_p2_region1: region1 {
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rockchip,attribute = "No-Merge FIFO";
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rockchip,ca-addr-width = <0>;
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rockchip,dummy-clk-num = <1>;
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rockchip,cs0-be-ctrled = <0>;
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rockchip,cs0-ctrl = <0>;
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status = "disabled";
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};
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dsmc_p2_region2: region2 {
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rockchip,attribute = "DPRA";
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rockchip,ca-addr-width = <0>;
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rockchip,dummy-clk-num = <1>;
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rockchip,cs0-be-ctrled = <0>;
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rockchip,cs0-ctrl = <0>;
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status = "disabled";
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};
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dsmc_p2_region3: region3 {
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rockchip,attribute = "Register";
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rockchip,ca-addr-width = <0>;
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rockchip,dummy-clk-num = <1>;
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rockchip,cs0-be-ctrled = <0>;
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rockchip,cs0-ctrl = <0>;
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status = "disabled";
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};
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};
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};
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dsmc_lb_slave3: lb-slave3 {
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rockchip,mtr-timing = <1 0 0 0 0 0 2 2>;
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rockchip,int-en = <0x3>;
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status = "disabled";
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dsmc_p3_region: region {
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dsmc_p3_region0: region0 {
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rockchip,attribute = "Merged FIFO";
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rockchip,ca-addr-width = <0>;
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rockchip,dummy-clk-num = <1>;
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rockchip,cs0-be-ctrled = <0>;
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rockchip,cs0-ctrl = <0>;
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status = "disabled";
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};
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dsmc_p3_region1: region1 {
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rockchip,attribute = "No-Merge FIFO";
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rockchip,ca-addr-width = <0>;
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rockchip,dummy-clk-num = <1>;
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rockchip,cs0-be-ctrled = <0>;
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rockchip,cs0-ctrl = <0>;
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status = "disabled";
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};
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dsmc_p3_region2: region2 {
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rockchip,attribute = "DPRA";
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rockchip,ca-addr-width = <0>;
|
|
rockchip,dummy-clk-num = <1>;
|
|
rockchip,cs0-be-ctrled = <0>;
|
|
rockchip,cs0-ctrl = <0>;
|
|
status = "disabled";
|
|
};
|
|
dsmc_p3_region3: region3 {
|
|
rockchip,attribute = "Register";
|
|
rockchip,ca-addr-width = <0>;
|
|
rockchip,dummy-clk-num = <1>;
|
|
rockchip,cs0-be-ctrled = <0>;
|
|
rockchip,cs0-ctrl = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&grf {
|
|
rgb: rgb {
|
|
compatible = "rockchip,rk3506-rgb";
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
rgb_in_vop: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&vop_out_rgb>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|