1924 lines
44 KiB
Plaintext
1924 lines
44 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rockchip-pinconf.dtsi"
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/*
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* This file is auto generated by pin2dts tool, please keep these code
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* by adding changes at end of this file.
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*/
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&pinctrl {
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aupll_clk {
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/omit-if-no-ref/
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aupll_clk_pins: aupll-clk-pins {
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rockchip,pins =
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/* aupll_clk_in */
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<0 RK_PC4 2 &pcfg_pull_none>;
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};
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};
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cpu {
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/omit-if-no-ref/
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cpu_pins: cpu-pins {
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rockchip,pins =
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/* cpu_avs */
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<0 RK_PC5 1 &pcfg_pull_none>;
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};
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};
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dsm_aud {
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/omit-if-no-ref/
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dsm_audm0_ln_pins: dsm-audm0-ln-pins {
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rockchip,pins =
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/* dsm_aud_ln_m0 */
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<1 RK_PD0 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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dsm_audm0_lp_pins: dsm-audm0-lp-pins {
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rockchip,pins =
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/* dsm_aud_lp_m0 */
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<1 RK_PD1 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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dsm_audm0_rn_pins: dsm-audm0-rn-pins {
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rockchip,pins =
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/* dsm_aud_rn_m0 */
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<1 RK_PC1 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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dsm_audm0_rp_pins: dsm-audm0-rp-pins {
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rockchip,pins =
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/* dsm_aud_rp_m0 */
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<1 RK_PC2 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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dsm_audm1_ln_pins: dsm-audm1-ln-pins {
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rockchip,pins =
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/* dsm_aud_ln_m1 */
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<2 RK_PB6 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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dsm_audm1_lp_pins: dsm-audm1-lp-pins {
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rockchip,pins =
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/* dsm_aud_lp_m1 */
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<2 RK_PB7 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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dsm_audm1_rn_pins: dsm-audm1-rn-pins {
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rockchip,pins =
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/* dsm_aud_rn_m1 */
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<2 RK_PB4 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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dsm_audm1_rp_pins: dsm-audm1-rp-pins {
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rockchip,pins =
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/* dsm_aud_rp_m1 */
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<2 RK_PB5 2 &pcfg_pull_none>;
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};
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};
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dsmc {
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/omit-if-no-ref/
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dsmc_int_pins: dsmc-int-pins {
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rockchip,pins =
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/* dsmc_int0 */
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<1 RK_PA1 4 &pcfg_pull_down>,
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/* dsmc_int1 */
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<1 RK_PC0 4 &pcfg_pull_down>;
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};
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/omit-if-no-ref/
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dsmc_clk_pins: dsmc-clk-pins {
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rockchip,pins =
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/* dsmc_clkn */
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<1 RK_PA1 2 &pcfg_pull_up_drv_level_3>,
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/* dsmc_resetn */
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<1 RK_PC0 2 &pcfg_pull_up>;
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};
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/omit-if-no-ref/
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dsmc_csn_pins: dsmc-csn-pins {
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rockchip,pins =
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/* dsmc_csn0 */
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<1 RK_PB6 2 &pcfg_pull_up>,
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/* dsmc_csn1 */
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<1 RK_PB1 2 &pcfg_pull_up>,
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/* dsmc_csn2 */
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<1 RK_PD2 2 &pcfg_pull_up>,
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/* dsmc_csn3 */
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<1 RK_PD3 2 &pcfg_pull_up>;
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};
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/omit-if-no-ref/
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dsmc_bus16_pins: dsmc-bus16-pins {
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rockchip,pins =
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/* dsmc_clkp */
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<1 RK_PA0 2 &pcfg_pull_down_drv_level_3>,
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/* dsmc_d0 */
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<1 RK_PA3 2 &pcfg_pull_down>,
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/* dsmc_d1 */
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<1 RK_PA4 2 &pcfg_pull_down>,
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/* dsmc_d2 */
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<1 RK_PA5 2 &pcfg_pull_down>,
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/* dsmc_d3 */
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<1 RK_PA6 2 &pcfg_pull_down>,
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/* dsmc_d4 */
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<1 RK_PA7 2 &pcfg_pull_down>,
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/* dsmc_d5 */
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<1 RK_PB0 2 &pcfg_pull_down>,
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/* dsmc_d6 */
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<1 RK_PB4 2 &pcfg_pull_down>,
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/* dsmc_d7 */
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<1 RK_PB5 2 &pcfg_pull_down>,
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/* dsmc_d8 */
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<1 RK_PC1 2 &pcfg_pull_down>,
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/* dsmc_d9 */
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<1 RK_PC2 2 &pcfg_pull_down>,
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/* dsmc_d10 */
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<1 RK_PC3 2 &pcfg_pull_down>,
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/* dsmc_d11 */
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<1 RK_PC4 2 &pcfg_pull_down>,
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/* dsmc_d12 */
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<1 RK_PC5 2 &pcfg_pull_down>,
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/* dsmc_d13 */
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<1 RK_PC6 2 &pcfg_pull_down>,
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/* dsmc_d14 */
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<1 RK_PC7 2 &pcfg_pull_down>,
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/* dsmc_d15 */
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<1 RK_PD0 2 &pcfg_pull_down>,
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/* dsmc_dqs0 */
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<1 RK_PA2 2 &pcfg_pull_down>,
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/* dsmc_dqs1 */
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<1 RK_PD1 2 &pcfg_pull_down>,
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/* dsmc_int2 */
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<1 RK_PB2 2 &pcfg_pull_down>,
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/* dsmc_int3 */
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<1 RK_PB3 2 &pcfg_pull_down>,
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/* dsmc_rdyn */
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<1 RK_PB7 2 &pcfg_pull_down>;
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};
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};
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dsmc_slv {
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/omit-if-no-ref/
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dsmc_slv_csn0_pins: dsmc-slv-csn0-pins {
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rockchip,pins =
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/* dsmc_slv_csn0 */
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<1 RK_PD2 8 &pcfg_pull_up>;
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};
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/omit-if-no-ref/
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dsmc_slv_bus8_pins: dsmc-slv-bus8-pins {
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rockchip,pins =
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/* dsmc_slv_clk */
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<1 RK_PC0 8 &pcfg_pull_down>,
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/* dsmc_slv_d0 */
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<1 RK_PC2 8 &pcfg_pull_down>,
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/* dsmc_slv_d1 */
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<1 RK_PC3 8 &pcfg_pull_down>,
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/* dsmc_slv_d2 */
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<1 RK_PC4 8 &pcfg_pull_down>,
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/* dsmc_slv_d3 */
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<1 RK_PC5 8 &pcfg_pull_down>,
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/* dsmc_slv_d4 */
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<1 RK_PC6 8 &pcfg_pull_down>,
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/* dsmc_slv_d5 */
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<1 RK_PC7 8 &pcfg_pull_down>,
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/* dsmc_slv_d6 */
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<1 RK_PD0 8 &pcfg_pull_down>,
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/* dsmc_slv_d7 */
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<1 RK_PD1 8 &pcfg_pull_down>,
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/* dsmc_slv_dqs0 */
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<1 RK_PC1 8 &pcfg_pull_down>,
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/* dsmc_slv_int */
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<1 RK_PA1 8 &pcfg_pull_down>,
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/* dsmc_slv_rdyn */
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<1 RK_PD3 8 &pcfg_pull_down>;
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};
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};
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eth_clk0_25m {
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/omit-if-no-ref/
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eth_clk0_25m_out_pins: eth-clk0-25m-out-pins {
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rockchip,pins =
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/* eth_clk0_25m_out */
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<0 RK_PC4 1 &pcfg_pull_none>;
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};
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};
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eth_clk1_25m {
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/omit-if-no-ref/
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eth_clk1_25m_out_pins: eth-clk1-25m-out-pins {
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rockchip,pins =
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/* eth_clk1_25m_out */
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<0 RK_PC3 1 &pcfg_pull_none>;
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};
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};
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eth_rmii0 {
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/omit-if-no-ref/
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eth_rmii0_miim_pins: eth-rmii0-miim-pins {
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rockchip,pins =
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/* eth_rmii0_mdc */
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<2 RK_PB6 1 &pcfg_pull_none>,
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/* eth_rmii0_mdio */
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<2 RK_PB7 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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eth_rmii0_rx_bus2_pins: eth-rmii0-rx-bus2-pins {
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rockchip,pins =
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/* eth_rmii0_rxd0 */
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<2 RK_PB0 1 &pcfg_pull_none>,
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/* eth_rmii0_rxd1 */
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<2 RK_PB1 1 &pcfg_pull_none>,
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/* eth_rmii0_rxdvcrs */
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<2 RK_PC0 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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eth_rmii0_tx_bus2_pins: eth-rmii0-tx-bus2-pins {
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rockchip,pins =
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/* eth_rmii0_txd0 */
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<2 RK_PB3 1 &pcfg_pull_none>,
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/* eth_rmii0_txd1 */
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<2 RK_PB4 1 &pcfg_pull_none>,
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/* eth_rmii0_txen */
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<2 RK_PB5 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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eth_rmii0_clk_pins: eth-rmii0-clk-pins {
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rockchip,pins =
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/* eth_rmii0_clk */
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<2 RK_PB2 1 &pcfg_pull_none>;
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};
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};
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eth_rmii1 {
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/omit-if-no-ref/
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eth_rmii1_miim_pins: eth-rmii1-miim-pins {
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rockchip,pins =
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/* eth_rmii1_mdc */
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<3 RK_PB4 2 &pcfg_pull_none>,
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/* eth_rmii1_mdio */
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<3 RK_PB5 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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eth_rmii1_rx_bus2_pins: eth-rmii1-rx-bus2-pins {
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rockchip,pins =
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/* eth_rmii1_rxd0 */
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<3 RK_PA6 2 &pcfg_pull_none>,
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/* eth_rmii1_rxd1 */
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<3 RK_PA7 2 &pcfg_pull_none>,
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/* eth_rmii1_rxdvcrs */
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<3 RK_PB6 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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eth_rmii1_tx_bus2_pins: eth-rmii1-tx-bus2-pins {
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rockchip,pins =
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/* eth_rmii1_txd0 */
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<3 RK_PB1 2 &pcfg_pull_none>,
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/* eth_rmii1_txd1 */
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<3 RK_PB2 2 &pcfg_pull_none>,
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/* eth_rmii1_txen */
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<3 RK_PB3 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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eth_rmii1_clk_pins: eth-rmii1-clk-pins {
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rockchip,pins =
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/* eth_rmii1_clk */
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<3 RK_PB0 2 &pcfg_pull_none>;
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};
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};
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flexbus0 {
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/omit-if-no-ref/
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flexbus0m0_pins: flexbus0m0-pins {
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rockchip,pins =
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/* flexbus0_csn_m0 */
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<1 RK_PB0 5 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0m1_pins: flexbus0m1-pins {
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rockchip,pins =
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/* flexbus0_csn_m1 */
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<1 RK_PB2 5 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0m2_pins: flexbus0m2-pins {
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rockchip,pins =
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/* flexbus0_csn_m2 */
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<1 RK_PB4 5 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0m3_pins: flexbus0m3-pins {
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rockchip,pins =
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/* flexbus0_csn_m3 */
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<1 RK_PB6 5 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0m4_pins: flexbus0m4-pins {
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rockchip,pins =
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/* flexbus0_csn_m4 */
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<1 RK_PC0 5 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0m5_pins: flexbus0m5-pins {
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rockchip,pins =
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/* flexbus0_csn_m5 */
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<1 RK_PC2 5 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_clk_pins: flexbus0-clk-pins {
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rockchip,pins =
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/* flexbus0_clk */
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<1 RK_PC1 3 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d0_pins: flexbus0-d0-pins {
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rockchip,pins =
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/* flexbus0_d0 */
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<1 RK_PD3 3 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d1_pins: flexbus0-d1-pins {
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rockchip,pins =
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/* flexbus0_d1 */
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<1 RK_PD2 3 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d2_pins: flexbus0-d2-pins {
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rockchip,pins =
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/* flexbus0_d2 */
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<1 RK_PD1 3 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d3_pins: flexbus0-d3-pins {
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rockchip,pins =
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/* flexbus0_d3 */
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<1 RK_PD0 3 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d4_pins: flexbus0-d4-pins {
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rockchip,pins =
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/* flexbus0_d4 */
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<1 RK_PC7 3 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d5_pins: flexbus0-d5-pins {
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rockchip,pins =
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/* flexbus0_d5 */
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<1 RK_PC6 3 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d6_pins: flexbus0-d6-pins {
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rockchip,pins =
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/* flexbus0_d6 */
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<1 RK_PC5 3 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d7_pins: flexbus0-d7-pins {
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rockchip,pins =
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/* flexbus0_d7 */
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<1 RK_PC4 3 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d8_pins: flexbus0-d8-pins {
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rockchip,pins =
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/* flexbus0_d8 */
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<1 RK_PC3 3 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d9_pins: flexbus0-d9-pins {
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rockchip,pins =
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/* flexbus0_d9 */
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<1 RK_PC2 3 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d10_pins: flexbus0-d10-pins {
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rockchip,pins =
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/* flexbus0_d10 */
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<1 RK_PB7 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d11_pins: flexbus0-d11-pins {
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rockchip,pins =
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/* flexbus0_d11 */
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<1 RK_PB6 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d12_pins: flexbus0-d12-pins {
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rockchip,pins =
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/* flexbus0_d12 */
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<1 RK_PB5 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d13_pins: flexbus0-d13-pins {
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rockchip,pins =
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/* flexbus0_d13 */
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<1 RK_PB4 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d14_pins: flexbus0-d14-pins {
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rockchip,pins =
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/* flexbus0_d14 */
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<1 RK_PB3 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus0_d15_pins: flexbus0-d15-pins {
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rockchip,pins =
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/* flexbus0_d15 */
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<1 RK_PB2 4 &pcfg_pull_none>;
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};
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};
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flexbus1 {
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/omit-if-no-ref/
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flexbus1m0_pins: flexbus1m0-pins {
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rockchip,pins =
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/* flexbus1_csn_m0 */
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<1 RK_PB1 5 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus1m1_pins: flexbus1m1-pins {
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rockchip,pins =
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/* flexbus1_csn_m1 */
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<1 RK_PB3 5 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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flexbus1m2_pins: flexbus1m2-pins {
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rockchip,pins =
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|
/* flexbus1_csn_m2 */
|
|
<1 RK_PB5 5 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
flexbus1m3_pins: flexbus1m3-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_csn_m3 */
|
|
<1 RK_PB7 5 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
flexbus1m4_pins: flexbus1m4-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_csn_m4 */
|
|
<1 RK_PC1 5 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
flexbus1m5_pins: flexbus1m5-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_csn_m5 */
|
|
<1 RK_PC3 5 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
flexbus1_clk_pins: flexbus1-clk-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_clk */
|
|
<1 RK_PC0 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d0_pins: flexbus1-d0-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d0 */
|
|
<1 RK_PA0 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d1_pins: flexbus1-d1-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d1 */
|
|
<1 RK_PA1 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d2_pins: flexbus1-d2-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d2 */
|
|
<1 RK_PA2 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d3_pins: flexbus1-d3-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d3 */
|
|
<1 RK_PA3 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d4_pins: flexbus1-d4-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d4 */
|
|
<1 RK_PA4 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d5_pins: flexbus1-d5-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d5 */
|
|
<1 RK_PA5 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d6_pins: flexbus1-d6-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d6 */
|
|
<1 RK_PA6 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d7_pins: flexbus1-d7-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d7 */
|
|
<1 RK_PA7 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d8_pins: flexbus1-d8-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d8 */
|
|
<1 RK_PB0 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d9_pins: flexbus1-d9-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d9 */
|
|
<1 RK_PB1 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d10_pins: flexbus1-d10-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d10 */
|
|
<1 RK_PB2 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d11_pins: flexbus1-d11-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d11 */
|
|
<1 RK_PB3 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d12_pins: flexbus1-d12-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d12 */
|
|
<1 RK_PB4 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d13_pins: flexbus1-d13-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d13 */
|
|
<1 RK_PB5 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d14_pins: flexbus1-d14-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d14 */
|
|
<1 RK_PB6 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
flexbus1_d15_pins: flexbus1-d15-pins {
|
|
rockchip,pins =
|
|
/* flexbus1_d15 */
|
|
<1 RK_PB7 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
fspi {
|
|
/omit-if-no-ref/
|
|
fspi_bus4_pins: fspi-bus4-pins {
|
|
rockchip,pins =
|
|
/* fspi_d0 */
|
|
<2 RK_PA2 1 &pcfg_pull_none>,
|
|
/* fspi_d1 */
|
|
<2 RK_PA3 1 &pcfg_pull_none>,
|
|
/* fspi_d2 */
|
|
<2 RK_PA4 1 &pcfg_pull_none>,
|
|
/* fspi_d3 */
|
|
<2 RK_PA5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
fspi_clk_pins: fspi-clk-pins {
|
|
rockchip,pins =
|
|
/* fspi_clk */
|
|
<2 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
fspi_csn_pins: fspi-csn-pins {
|
|
rockchip,pins =
|
|
/* fspi_csn */
|
|
<2 RK_PA0 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
jtag {
|
|
/omit-if-no-ref/
|
|
jtagm0_pins: jtagm0-pins {
|
|
rockchip,pins =
|
|
/* jtag_tck_m0 */
|
|
<3 RK_PA4 2 &pcfg_pull_none>,
|
|
/* jtag_tms_m0 */
|
|
<3 RK_PA5 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
jtagm1_pins: jtagm1-pins {
|
|
rockchip,pins =
|
|
/* jtag_tck_m1 */
|
|
<0 RK_PC6 2 &pcfg_pull_none>,
|
|
/* jtag_tms_m1 */
|
|
<0 RK_PC7 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
ref_clk1 {
|
|
/omit-if-no-ref/
|
|
ref_clk1_pins: ref-clk1-pins {
|
|
rockchip,pins =
|
|
/* ref_clk1_out */
|
|
<0 RK_PC2 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
rm {
|
|
/omit-if-no-ref/
|
|
rm_io0_pins: rm-io0-pins {
|
|
rockchip,pins =
|
|
/* rm_io0 */
|
|
<0 RK_PA0 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io1_pins: rm-io1-pins {
|
|
rockchip,pins =
|
|
/* rm_io1 */
|
|
<0 RK_PA1 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io2_pins: rm-io2-pins {
|
|
rockchip,pins =
|
|
/* rm_io2 */
|
|
<0 RK_PA2 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io3_pins: rm-io3-pins {
|
|
rockchip,pins =
|
|
/* rm_io3 */
|
|
<0 RK_PA3 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io4_pins: rm-io4-pins {
|
|
rockchip,pins =
|
|
/* rm_io4 */
|
|
<0 RK_PA4 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io5_pins: rm-io5-pins {
|
|
rockchip,pins =
|
|
/* rm_io5 */
|
|
<0 RK_PA5 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io6_pins: rm-io6-pins {
|
|
rockchip,pins =
|
|
/* rm_io6 */
|
|
<0 RK_PA6 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io7_pins: rm-io7-pins {
|
|
rockchip,pins =
|
|
/* rm_io7 */
|
|
<0 RK_PA7 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io8_pins: rm-io8-pins {
|
|
rockchip,pins =
|
|
/* rm_io8 */
|
|
<0 RK_PB0 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io9_pins: rm-io9-pins {
|
|
rockchip,pins =
|
|
/* rm_io9 */
|
|
<0 RK_PB1 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io10_pins: rm-io10-pins {
|
|
rockchip,pins =
|
|
/* rm_io10 */
|
|
<0 RK_PB2 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io11_pins: rm-io11-pins {
|
|
rockchip,pins =
|
|
/* rm_io11 */
|
|
<0 RK_PB3 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io12_pins: rm-io12-pins {
|
|
rockchip,pins =
|
|
/* rm_io12 */
|
|
<0 RK_PB4 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io13_pins: rm-io13-pins {
|
|
rockchip,pins =
|
|
/* rm_io13 */
|
|
<0 RK_PB5 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io14_pins: rm-io14-pins {
|
|
rockchip,pins =
|
|
/* rm_io14 */
|
|
<0 RK_PB6 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io15_pins: rm-io15-pins {
|
|
rockchip,pins =
|
|
/* rm_io15 */
|
|
<0 RK_PB7 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io16_pins: rm-io16-pins {
|
|
rockchip,pins =
|
|
/* rm_io16 */
|
|
<0 RK_PC0 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io17_pins: rm-io17-pins {
|
|
rockchip,pins =
|
|
/* rm_io17 */
|
|
<0 RK_PC1 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io18_pins: rm-io18-pins {
|
|
rockchip,pins =
|
|
/* rm_io18 */
|
|
<0 RK_PC2 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io19_pins: rm-io19-pins {
|
|
rockchip,pins =
|
|
/* rm_io19 */
|
|
<0 RK_PC3 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io20_pins: rm-io20-pins {
|
|
rockchip,pins =
|
|
/* rm_io20 */
|
|
<0 RK_PC4 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io21_pins: rm-io21-pins {
|
|
rockchip,pins =
|
|
/* rm_io21 */
|
|
<0 RK_PC5 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io22_pins: rm-io22-pins {
|
|
rockchip,pins =
|
|
/* rm_io22 */
|
|
<0 RK_PC6 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io23_pins: rm-io23-pins {
|
|
rockchip,pins =
|
|
/* rm_io23 */
|
|
<0 RK_PC7 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io24_pins: rm-io24-pins {
|
|
rockchip,pins =
|
|
/* rm_io24 */
|
|
<1 RK_PB1 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io25_pins: rm-io25-pins {
|
|
rockchip,pins =
|
|
/* rm_io25 */
|
|
<1 RK_PB2 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io26_pins: rm-io26-pins {
|
|
rockchip,pins =
|
|
/* rm_io26 */
|
|
<1 RK_PB3 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io27_pins: rm-io27-pins {
|
|
rockchip,pins =
|
|
/* rm_io27 */
|
|
<1 RK_PC2 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io28_pins: rm-io28-pins {
|
|
rockchip,pins =
|
|
/* rm_io28 */
|
|
<1 RK_PC3 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io29_pins: rm-io29-pins {
|
|
rockchip,pins =
|
|
/* rm_io29 */
|
|
<1 RK_PD1 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io30_pins: rm-io30-pins {
|
|
rockchip,pins =
|
|
/* rm_io30 */
|
|
<1 RK_PD2 7 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io31_pins: rm-io31-pins {
|
|
rockchip,pins =
|
|
/* rm_io31 */
|
|
<1 RK_PD3 7 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sai0 {
|
|
/omit-if-no-ref/
|
|
sai0_lrck_pins: sai0-lrck-pins {
|
|
rockchip,pins =
|
|
/* sai0_lrck */
|
|
<0 RK_PA0 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai0_mclk_pins: sai0-mclk-pins {
|
|
rockchip,pins =
|
|
/* sai0_mclk */
|
|
<0 RK_PA2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai0_sclk_pins: sai0-sclk-pins {
|
|
rockchip,pins =
|
|
/* sai0_sclk */
|
|
<0 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai0_sdi0_pins: sai0-sdi0-pins {
|
|
rockchip,pins =
|
|
/* sai0_sdi0 */
|
|
<0 RK_PA4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai0_sdi1_pins: sai0-sdi1-pins {
|
|
rockchip,pins =
|
|
/* sai0_sdi1 */
|
|
<0 RK_PA5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai0_sdi2_pins: sai0-sdi2-pins {
|
|
rockchip,pins =
|
|
/* sai0_sdi2 */
|
|
<0 RK_PA6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai0_sdi3_pins: sai0-sdi3-pins {
|
|
rockchip,pins =
|
|
/* sai0_sdi3 */
|
|
<0 RK_PA7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai0_sdo_pins: sai0-sdo-pins {
|
|
rockchip,pins =
|
|
/* sai0_sdo */
|
|
<0 RK_PA3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sai1 {
|
|
/omit-if-no-ref/
|
|
sai1_lrck_pins: sai1-lrck-pins {
|
|
rockchip,pins =
|
|
/* sai1_lrck */
|
|
<0 RK_PB2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai1_mclk_pins: sai1-mclk-pins {
|
|
rockchip,pins =
|
|
/* sai1_mclk */
|
|
<0 RK_PB0 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai1_sclk_pins: sai1-sclk-pins {
|
|
rockchip,pins =
|
|
/* sai1_sclk */
|
|
<0 RK_PB1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai1_sdo0_pins: sai1-sdo0-pins {
|
|
rockchip,pins =
|
|
/* sai1_sdo0 */
|
|
<0 RK_PB4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai1_sdo1_pins: sai1-sdo1-pins {
|
|
rockchip,pins =
|
|
/* sai1_sdo1 */
|
|
<0 RK_PB5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai1_sdo2_pins: sai1-sdo2-pins {
|
|
rockchip,pins =
|
|
/* sai1_sdo2 */
|
|
<0 RK_PB6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai1_sdo3_pins: sai1-sdo3-pins {
|
|
rockchip,pins =
|
|
/* sai1_sdo3 */
|
|
<0 RK_PB7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai1_sdi_pins: sai1-sdi-pins {
|
|
rockchip,pins =
|
|
/* sai1_sdi */
|
|
<0 RK_PB3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sai2 {
|
|
/omit-if-no-ref/
|
|
sai2m0_lrck_pins: sai2m0-lrck-pins {
|
|
rockchip,pins =
|
|
/* sai2_lrck_m0 */
|
|
<3 RK_PB1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai2m0_mclk_pins: sai2m0-mclk-pins {
|
|
rockchip,pins =
|
|
/* sai2_mclk_m0 */
|
|
<3 RK_PB6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai2m0_sclk_pins: sai2m0-sclk-pins {
|
|
rockchip,pins =
|
|
/* sai2_sclk_m0 */
|
|
<3 RK_PA7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai2m0_sdi_pins: sai2m0-sdi-pins {
|
|
rockchip,pins =
|
|
/* sai2m0_sdi */
|
|
<3 RK_PA6 1 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
sai2m0_sdo_pins: sai2m0-sdo-pins {
|
|
rockchip,pins =
|
|
/* sai2m0_sdo */
|
|
<3 RK_PB0 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai2m1_lrck_pins: sai2m1-lrck-pins {
|
|
rockchip,pins =
|
|
/* sai2_lrck_m1 */
|
|
<1 RK_PB3 6 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai2m1_mclk_pins: sai2m1-mclk-pins {
|
|
rockchip,pins =
|
|
/* sai2_mclk_m1 */
|
|
<1 RK_PC1 6 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai2m1_sclk_pins: sai2m1-sclk-pins {
|
|
rockchip,pins =
|
|
/* sai2_sclk_m1 */
|
|
<1 RK_PB2 6 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai2m1_sdi_pins: sai2m1-sdi-pins {
|
|
rockchip,pins =
|
|
/* sai2m1_sdi */
|
|
<1 RK_PC2 6 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
sai2m1_sdo_pins: sai2m1-sdo-pins {
|
|
rockchip,pins =
|
|
/* sai2m1_sdo */
|
|
<1 RK_PC3 6 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sai3 {
|
|
/omit-if-no-ref/
|
|
sai3_lrck_pins: sai3-lrck-pins {
|
|
rockchip,pins =
|
|
/* sai3_lrck */
|
|
<2 RK_PB5 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai3_mclk_pins: sai3-mclk-pins {
|
|
rockchip,pins =
|
|
/* sai3_mclk */
|
|
<2 RK_PC0 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai3_sclk_pins: sai3-sclk-pins {
|
|
rockchip,pins =
|
|
/* sai3_sclk */
|
|
<2 RK_PB4 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sai3_sdi_pins: sai3-sdi-pins {
|
|
rockchip,pins =
|
|
/* sai3_sdi */
|
|
<2 RK_PB6 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
sai3_sdo_pins: sai3-sdo-pins {
|
|
rockchip,pins =
|
|
/* sai3_sdo */
|
|
<2 RK_PB7 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sdmmc {
|
|
/omit-if-no-ref/
|
|
sdmmc_bus4_pins: sdmmc-bus4-pins {
|
|
rockchip,pins =
|
|
/* sdmmc_d0 */
|
|
<3 RK_PA2 1 &pcfg_pull_up>,
|
|
/* sdmmc_d1 */
|
|
<3 RK_PA3 1 &pcfg_pull_up>,
|
|
/* sdmmc_d2 */
|
|
<3 RK_PA4 1 &pcfg_pull_up>,
|
|
/* sdmmc_d3 */
|
|
<3 RK_PA5 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc_clk_pins: sdmmc-clk-pins {
|
|
rockchip,pins =
|
|
/* sdmmc_clk */
|
|
<3 RK_PA0 1 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
sdmmc_cmd_pins: sdmmc-cmd-pins {
|
|
rockchip,pins =
|
|
/* sdmmc_cmd */
|
|
<3 RK_PA1 1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
/omit-if-no-ref/
|
|
spi0_clk_pins: spi0-clk-pins {
|
|
rockchip,pins =
|
|
/* spi0_clk */
|
|
<0 RK_PC0 2 &pcfg_pull_none_drv_level_3>,
|
|
/* spi0_miso */
|
|
<0 RK_PC2 2 &pcfg_pull_none_drv_level_3>,
|
|
/* spi0_mosi */
|
|
<0 RK_PC1 2 &pcfg_pull_none_drv_level_3>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
spi0_csn0_pins: spi0-csn0-pins {
|
|
rockchip,pins =
|
|
/* spi0_csn0 */
|
|
<0 RK_PC3 2 &pcfg_pull_none_drv_level_3>;
|
|
};
|
|
/omit-if-no-ref/
|
|
spi0_csn1_pins: spi0-csn1-pins {
|
|
rockchip,pins =
|
|
/* spi0_csn1 */
|
|
<0 RK_PB7 2 &pcfg_pull_none_drv_level_3>;
|
|
};
|
|
};
|
|
|
|
spi1 {
|
|
/omit-if-no-ref/
|
|
spi1_clk_pins: spi1-clk-pins {
|
|
rockchip,pins =
|
|
/* spi1_clk */
|
|
<0 RK_PB0 2 &pcfg_pull_none_drv_level_3>,
|
|
/* spi1_miso */
|
|
<0 RK_PB2 2 &pcfg_pull_none_drv_level_3>,
|
|
/* spi1_mosi */
|
|
<0 RK_PB1 2 &pcfg_pull_none_drv_level_3>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
spi1_csn0_pins: spi1-csn0-pins {
|
|
rockchip,pins =
|
|
/* spi1_csn0 */
|
|
<0 RK_PB6 2 &pcfg_pull_none_drv_level_3>;
|
|
};
|
|
/omit-if-no-ref/
|
|
spi1_csn1_pins: spi1-csn1-pins {
|
|
rockchip,pins =
|
|
/* spi1_csn1 */
|
|
<0 RK_PA7 2 &pcfg_pull_none_drv_level_3>;
|
|
};
|
|
};
|
|
|
|
spi2 {
|
|
/omit-if-no-ref/
|
|
spi2_clk_pins: spi2-clk-pins {
|
|
rockchip,pins =
|
|
/* spi2_clk */
|
|
<2 RK_PB0 2 &pcfg_pull_none>,
|
|
/* spi2_miso */
|
|
<2 RK_PB3 2 &pcfg_pull_none>,
|
|
/* spi2_mosi */
|
|
<2 RK_PB2 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
spi2_csn_pins: spi2-csn-pins {
|
|
rockchip,pins =
|
|
/* spi2_csn */
|
|
<2 RK_PB1 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
test_clk {
|
|
/omit-if-no-ref/
|
|
test_clk_pins: test-clk-pins {
|
|
rockchip,pins =
|
|
/* test_clk_out */
|
|
<3 RK_PA3 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
/omit-if-no-ref/
|
|
uart0_xfer_pins: uart0-xfer-pins {
|
|
rockchip,pins =
|
|
/* uart0_rx */
|
|
<0 RK_PC7 1 &pcfg_pull_up>,
|
|
/* uart0_tx */
|
|
<0 RK_PC6 1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart5 {
|
|
/omit-if-no-ref/
|
|
uart5m0_xfer_pins: uart5m0-xfer-pins {
|
|
rockchip,pins =
|
|
/* uart5_rx_m0 */
|
|
<3 RK_PB3 1 &pcfg_pull_up>,
|
|
/* uart5_tx_m0 */
|
|
<3 RK_PB4 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart5m0_ctsn_pins: uart5m0-ctsn-pins {
|
|
rockchip,pins =
|
|
/* uart5m0_ctsn */
|
|
<3 RK_PB2 1 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart5m0_rtsn_pins: uart5m0-rtsn-pins {
|
|
rockchip,pins =
|
|
/* uart5m0_rtsn */
|
|
<3 RK_PB5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart5m1_xfer_pins: uart5m1-xfer-pins {
|
|
rockchip,pins =
|
|
/* uart5_rx_m1 */
|
|
<1 RK_PD3 6 &pcfg_pull_up>,
|
|
/* uart5_tx_m1 */
|
|
<1 RK_PD2 6 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart5m1_ctsn_pins: uart5m1-ctsn-pins {
|
|
rockchip,pins =
|
|
/* uart5m1_ctsn */
|
|
<1 RK_PB1 6 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart5m1_rtsn_pins: uart5m1-rtsn-pins {
|
|
rockchip,pins =
|
|
/* uart5m1_rtsn */
|
|
<1 RK_PD1 6 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
vo_lcdc {
|
|
/omit-if-no-ref/
|
|
vo_lcdc_pins: vo-lcdc-pins {
|
|
rockchip,pins =
|
|
/* vo_lcdc_clk */
|
|
<1 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
|
|
/* vo_lcdc_d0 */
|
|
<1 RK_PD3 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d1 */
|
|
<1 RK_PD2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d2 */
|
|
<1 RK_PD1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d3 */
|
|
<1 RK_PD0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d4 */
|
|
<1 RK_PC7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d5 */
|
|
<1 RK_PC6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d6 */
|
|
<1 RK_PC5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d7 */
|
|
<1 RK_PC4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d8 */
|
|
<1 RK_PC3 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d9 */
|
|
<1 RK_PC2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d10 */
|
|
<1 RK_PC1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d11 */
|
|
<1 RK_PC0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d12 */
|
|
<1 RK_PB7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d13 */
|
|
<1 RK_PB6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d14 */
|
|
<1 RK_PB5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d15 */
|
|
<1 RK_PB4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d16 */
|
|
<1 RK_PB3 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d17 */
|
|
<1 RK_PB2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d18 */
|
|
<1 RK_PB1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d19 */
|
|
<1 RK_PB0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d20 */
|
|
<1 RK_PA7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d21 */
|
|
<1 RK_PA6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d22 */
|
|
<1 RK_PA5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d23 */
|
|
<1 RK_PA4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_den */
|
|
<1 RK_PA0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_hsync */
|
|
<1 RK_PA2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_vsync */
|
|
<1 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/*
|
|
* This part is edited handly.
|
|
*/
|
|
&pinctrl {
|
|
dsm_aud {
|
|
/omit-if-no-ref/
|
|
dsm_audm0_pins: dsm-audm0-pins {
|
|
rockchip,pins =
|
|
/* dsm_aud_ln_m0 */
|
|
<1 RK_PD0 4 &pcfg_pull_none>,
|
|
/* dsm_aud_lp_m0 */
|
|
<1 RK_PD1 4 &pcfg_pull_none>,
|
|
/* dsm_aud_rn_m0 */
|
|
<1 RK_PC1 4 &pcfg_pull_none>,
|
|
/* dsm_aud_rp_m0 */
|
|
<1 RK_PC2 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
dsm_audm1_pins: dsm-audm1-pins {
|
|
rockchip,pins =
|
|
/* dsm_aud_ln_m1 */
|
|
<2 RK_PB6 2 &pcfg_pull_none>,
|
|
/* dsm_aud_lp_m1 */
|
|
<2 RK_PB7 2 &pcfg_pull_none>,
|
|
/* dsm_aud_rn_m1 */
|
|
<2 RK_PB4 2 &pcfg_pull_none>,
|
|
/* dsm_aud_rp_m1 */
|
|
<2 RK_PB5 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
dsm_audm0_iodown_pins: dsm-audm0-iodown-pins {
|
|
rockchip,pins =
|
|
/* dsm_aud_ln_m0 */
|
|
<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
/* dsm_aud_lp_m0 */
|
|
<1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
/* dsm_aud_rn_m0 */
|
|
<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
/* dsm_aud_rp_m0 */
|
|
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
dsm_audm1_iodown_pins: dsm-audm1-iodown-pins {
|
|
rockchip,pins =
|
|
/* dsm_aud_ln_m1 */
|
|
<2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
/* dsm_aud_lp_m1 */
|
|
<2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
/* dsm_aud_rn_m1 */
|
|
<2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
/* dsm_aud_rp_m1 */
|
|
<2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
dsmc {
|
|
/omit-if-no-ref/
|
|
dsmc_csn_pull_pins: dsmc-csn-pull-pins {
|
|
rockchip,pins =
|
|
/* dsmc_csn0 */
|
|
<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
/* dsmc_csn1 */
|
|
<1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
/* dsmc_csn2 */
|
|
<1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>,
|
|
/* dsmc_csn3 */
|
|
<1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
dsmc_slv {
|
|
/omit-if-no-ref/
|
|
dsmc_slv_csn0_pull_pins: dsmc-slv-csn0-pull-pins {
|
|
rockchip,pins =
|
|
/* dsmc_slv_csn0 */
|
|
<1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
rm_io_idle {
|
|
/omit-if-no-ref/
|
|
rm_io9_idle_pins: rm-io9-idle-pins {
|
|
rockchip,pins =
|
|
<0 RK_PB1 RK_FUNC_GPIO &pcfg_input_enable_pull_down>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io10_idle_pins: rm-io10-idle-pins {
|
|
rockchip,pins =
|
|
<0 RK_PB2 RK_FUNC_GPIO &pcfg_input_enable_pull_down>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io11_idle_pins: rm-io11-idle-pins {
|
|
rockchip,pins =
|
|
<0 RK_PB3 RK_FUNC_GPIO &pcfg_input_enable_pull_down>;
|
|
};
|
|
/omit-if-no-ref/
|
|
rm_io12_idle_pins: rm-io12-idle-pins {
|
|
rockchip,pins =
|
|
<0 RK_PB4 RK_FUNC_GPIO &pcfg_input_enable_pull_down>;
|
|
};
|
|
};
|
|
|
|
vo_lcdc {
|
|
/omit-if-no-ref/
|
|
bt1120_pins: bt1120-pins {
|
|
rockchip,pins =
|
|
/* vo_lcdc_clk */
|
|
<1 RK_PA3 1 &pcfg_pull_none_drv_level_4>,
|
|
/* vo_lcdc_d3 */
|
|
<1 RK_PD0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d4 */
|
|
<1 RK_PC7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d5 */
|
|
<1 RK_PC6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d6 */
|
|
<1 RK_PC5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d7 */
|
|
<1 RK_PC4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d10 */
|
|
<1 RK_PC1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d11 */
|
|
<1 RK_PC0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d12 */
|
|
<1 RK_PB7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d13 */
|
|
<1 RK_PB6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d14 */
|
|
<1 RK_PB5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d15 */
|
|
<1 RK_PB4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d19 */
|
|
<1 RK_PB0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d20 */
|
|
<1 RK_PA7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d21 */
|
|
<1 RK_PA6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d22 */
|
|
<1 RK_PA5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d23 */
|
|
<1 RK_PA4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
bt656_m0_pins: bt656-m0-pins {
|
|
rockchip,pins =
|
|
/* vo_lcdc_clk */
|
|
<1 RK_PA3 1 &pcfg_pull_none_drv_level_4>,
|
|
/* vo_lcdc_d3 */
|
|
<1 RK_PD0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d4 */
|
|
<1 RK_PC7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d5 */
|
|
<1 RK_PC6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d6 */
|
|
<1 RK_PC5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d7 */
|
|
<1 RK_PC4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d10 */
|
|
<1 RK_PC1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d11 */
|
|
<1 RK_PC0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d12 */
|
|
<1 RK_PB7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
bt656_m1_pins: bt656-m1-pins {
|
|
rockchip,pins =
|
|
/* vo_lcdc_clk */
|
|
<1 RK_PA3 1 &pcfg_pull_none_drv_level_4>,
|
|
/* vo_lcdc_d13 */
|
|
<1 RK_PB6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d14 */
|
|
<1 RK_PB5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d15 */
|
|
<1 RK_PB4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d19 */
|
|
<1 RK_PB0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d20 */
|
|
<1 RK_PA7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d21 */
|
|
<1 RK_PA6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d22 */
|
|
<1 RK_PA5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d23 */
|
|
<1 RK_PA4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
mcu_rgb3x8_rgb2x8_m0_pins: mcu-rgb3x8-rgb2x8-m0-pins {
|
|
rockchip,pins =
|
|
/* vo_lcdc_clk */
|
|
<1 RK_PA3 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d3 */
|
|
<1 RK_PD0 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d4 */
|
|
<1 RK_PC7 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d5 */
|
|
<1 RK_PC6 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d6 */
|
|
<1 RK_PC5 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d7 */
|
|
<1 RK_PC4 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d10 */
|
|
<1 RK_PC1 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d11 */
|
|
<1 RK_PC0 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d12 */
|
|
<1 RK_PB7 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_den */
|
|
<1 RK_PA0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_hsync */
|
|
<1 RK_PA2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_vsync */
|
|
<1 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
mcu_rgb3x8_rgb2x8_m1_pins: mcu-rgb3x8-rgb2x8-m1-pins {
|
|
rockchip,pins =
|
|
/* vo_lcdc_clk */
|
|
<1 RK_PA3 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d13 */
|
|
<1 RK_PB6 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d14 */
|
|
<1 RK_PB5 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d15 */
|
|
<1 RK_PB4 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d19 */
|
|
<1 RK_PB0 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d20 */
|
|
<1 RK_PA7 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d21 */
|
|
<1 RK_PA6 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d22 */
|
|
<1 RK_PA5 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d23 */
|
|
<1 RK_PA4 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_den */
|
|
<1 RK_PA0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_hsync */
|
|
<1 RK_PA2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_vsync */
|
|
<1 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
mcu_rgb565_pins: mcu-rgb565-pins {
|
|
rockchip,pins =
|
|
/* vo_lcdc_clk */
|
|
<1 RK_PA3 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d3 */
|
|
<1 RK_PD0 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d4 */
|
|
<1 RK_PC7 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d5 */
|
|
<1 RK_PC6 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d6 */
|
|
<1 RK_PC5 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d7 */
|
|
<1 RK_PC4 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d10 */
|
|
<1 RK_PC1 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d11 */
|
|
<1 RK_PC0 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d12 */
|
|
<1 RK_PB7 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d13 */
|
|
<1 RK_PB6 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d14 */
|
|
<1 RK_PB5 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d15 */
|
|
<1 RK_PB4 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d19 */
|
|
<1 RK_PB0 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d20 */
|
|
<1 RK_PA7 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d21 */
|
|
<1 RK_PA6 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d22 */
|
|
<1 RK_PA5 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d23 */
|
|
<1 RK_PA4 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_den */
|
|
<1 RK_PA0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_hsync */
|
|
<1 RK_PA2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_vsync */
|
|
<1 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
mcu_rgb666_pins: mcu-rgb666-pins {
|
|
rockchip,pins =
|
|
/* vo_lcdc_clk */
|
|
<1 RK_PA3 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d2 */
|
|
<1 RK_PD1 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d3 */
|
|
<1 RK_PD0 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d4 */
|
|
<1 RK_PC7 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d5 */
|
|
<1 RK_PC6 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d6 */
|
|
<1 RK_PC5 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d7 */
|
|
<1 RK_PC4 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d10 */
|
|
<1 RK_PC1 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d11 */
|
|
<1 RK_PC0 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d12 */
|
|
<1 RK_PB7 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d13 */
|
|
<1 RK_PB6 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d14 */
|
|
<1 RK_PB5 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d15 */
|
|
<1 RK_PB4 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d18 */
|
|
<1 RK_PB1 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d19 */
|
|
<1 RK_PB0 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d20 */
|
|
<1 RK_PA7 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d21 */
|
|
<1 RK_PA6 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d22 */
|
|
<1 RK_PA5 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d23 */
|
|
<1 RK_PA4 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_den */
|
|
<1 RK_PA0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_hsync */
|
|
<1 RK_PA2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_vsync */
|
|
<1 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
mcu_rgb888_pins: mcu-rgb888-pins {
|
|
rockchip,pins =
|
|
/* vo_lcdc_clk */
|
|
<1 RK_PA3 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d0 */
|
|
<1 RK_PD3 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d1 */
|
|
<1 RK_PD2 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d2 */
|
|
<1 RK_PD1 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d3 */
|
|
<1 RK_PD0 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d4 */
|
|
<1 RK_PC7 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d5 */
|
|
<1 RK_PC6 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d6 */
|
|
<1 RK_PC5 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d7 */
|
|
<1 RK_PC4 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d8 */
|
|
<1 RK_PC3 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d9 */
|
|
<1 RK_PC2 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d10 */
|
|
<1 RK_PC1 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d11 */
|
|
<1 RK_PC0 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d12 */
|
|
<1 RK_PB7 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d13 */
|
|
<1 RK_PB6 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d14 */
|
|
<1 RK_PB5 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d15 */
|
|
<1 RK_PB4 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d16 */
|
|
<1 RK_PB3 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d17 */
|
|
<1 RK_PB2 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d18 */
|
|
<1 RK_PB1 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d19 */
|
|
<1 RK_PB0 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d20 */
|
|
<1 RK_PA7 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d21 */
|
|
<1 RK_PA6 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d22 */
|
|
<1 RK_PA5 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_d23 */
|
|
<1 RK_PA4 1 &pcfg_pull_none_drv_level_0>,
|
|
/* vo_lcdc_den */
|
|
<1 RK_PA0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_hsync */
|
|
<1 RK_PA2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_vsync */
|
|
<1 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
rgb3x8_rgb2x8_m0_pins: rgb3x8-rgb2x8-m0-pins {
|
|
rockchip,pins =
|
|
/* vo_lcdc_clk */
|
|
<1 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
|
|
/* vo_lcdc_d3 */
|
|
<1 RK_PD0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d4 */
|
|
<1 RK_PC7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d5 */
|
|
<1 RK_PC6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d6 */
|
|
<1 RK_PC5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d7 */
|
|
<1 RK_PC4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d10 */
|
|
<1 RK_PC1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d11 */
|
|
<1 RK_PC0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d12 */
|
|
<1 RK_PB7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_den */
|
|
<1 RK_PA0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_hsync */
|
|
<1 RK_PA2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_vsync */
|
|
<1 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
rgb3x8_rgb2x8_m1_pins: rgb3x8-rgb2x8-m1-pins {
|
|
rockchip,pins =
|
|
/* vo_lcdc_clk */
|
|
<1 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
|
|
/* vo_lcdc_d13 */
|
|
<1 RK_PB6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d14 */
|
|
<1 RK_PB5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d15 */
|
|
<1 RK_PB4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d19 */
|
|
<1 RK_PB0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d20 */
|
|
<1 RK_PA7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d21 */
|
|
<1 RK_PA6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d22 */
|
|
<1 RK_PA5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d23 */
|
|
<1 RK_PA4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_den */
|
|
<1 RK_PA0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_hsync */
|
|
<1 RK_PA2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_vsync */
|
|
<1 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
rgb565_pins: rgb565-pins {
|
|
rockchip,pins =
|
|
/* vo_lcdc_clk */
|
|
<1 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
|
|
/* vo_lcdc_d3 */
|
|
<1 RK_PD0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d4 */
|
|
<1 RK_PC7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d5 */
|
|
<1 RK_PC6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d6 */
|
|
<1 RK_PC5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d7 */
|
|
<1 RK_PC4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d10 */
|
|
<1 RK_PC1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d11 */
|
|
<1 RK_PC0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d12 */
|
|
<1 RK_PB7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d13 */
|
|
<1 RK_PB6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d14 */
|
|
<1 RK_PB5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d15 */
|
|
<1 RK_PB4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d19 */
|
|
<1 RK_PB0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d20 */
|
|
<1 RK_PA7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d21 */
|
|
<1 RK_PA6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d22 */
|
|
<1 RK_PA5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d23 */
|
|
<1 RK_PA4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_den */
|
|
<1 RK_PA0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_hsync */
|
|
<1 RK_PA2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_vsync */
|
|
<1 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
rgb666_pins: rgb666-pins {
|
|
rockchip,pins =
|
|
/* vo_lcdc_clk */
|
|
<1 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
|
|
/* vo_lcdc_d2 */
|
|
<1 RK_PD1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d3 */
|
|
<1 RK_PD0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d4 */
|
|
<1 RK_PC7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d5 */
|
|
<1 RK_PC6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d6 */
|
|
<1 RK_PC5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d7 */
|
|
<1 RK_PC4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d10 */
|
|
<1 RK_PC1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d11 */
|
|
<1 RK_PC0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d12 */
|
|
<1 RK_PB7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d13 */
|
|
<1 RK_PB6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d14 */
|
|
<1 RK_PB5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d15 */
|
|
<1 RK_PB4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d18 */
|
|
<1 RK_PB1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d19 */
|
|
<1 RK_PB0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d20 */
|
|
<1 RK_PA7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d21 */
|
|
<1 RK_PA6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d22 */
|
|
<1 RK_PA5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d23 */
|
|
<1 RK_PA4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_den */
|
|
<1 RK_PA0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_hsync */
|
|
<1 RK_PA2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_vsync */
|
|
<1 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
rgb888_pins: rgb888-pins {
|
|
rockchip,pins =
|
|
/* vo_lcdc_clk */
|
|
<1 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
|
|
/* vo_lcdc_d0 */
|
|
<1 RK_PD3 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d1 */
|
|
<1 RK_PD2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d2 */
|
|
<1 RK_PD1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d3 */
|
|
<1 RK_PD0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d4 */
|
|
<1 RK_PC7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d5 */
|
|
<1 RK_PC6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d6 */
|
|
<1 RK_PC5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d7 */
|
|
<1 RK_PC4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d8 */
|
|
<1 RK_PC3 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d9 */
|
|
<1 RK_PC2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d10 */
|
|
<1 RK_PC1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d11 */
|
|
<1 RK_PC0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d12 */
|
|
<1 RK_PB7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d13 */
|
|
<1 RK_PB6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d14 */
|
|
<1 RK_PB5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d15 */
|
|
<1 RK_PB4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d16 */
|
|
<1 RK_PB3 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d17 */
|
|
<1 RK_PB2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d18 */
|
|
<1 RK_PB1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d19 */
|
|
<1 RK_PB0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d20 */
|
|
<1 RK_PA7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d21 */
|
|
<1 RK_PA6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d22 */
|
|
<1 RK_PA5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d23 */
|
|
<1 RK_PA4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_den */
|
|
<1 RK_PA0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_hsync */
|
|
<1 RK_PA2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_vsync */
|
|
<1 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|