679 lines
13 KiB
Plaintext
679 lines
13 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rockchip-pinconf.dtsi"
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&pinctrl {
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hdmi {
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hdmi_gpio: hdmi-gpio {
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rockchip,pins =
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<7 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>,
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<7 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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hdmi_cec_c0: hdmi-cec-c0 {
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rockchip,pins =
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<7 RK_PC0 2 &pcfg_pull_none>;
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};
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hdmi_cec_c7: hdmi-cec-c7 {
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rockchip,pins =
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<7 RK_PC7 4 &pcfg_pull_none>;
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};
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hdmi_ddc: hdmi-ddc {
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rockchip,pins =
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<7 RK_PC3 2 &pcfg_pull_none>,
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<7 RK_PC4 2 &pcfg_pull_none>;
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};
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hdmi_ddc_unwedge: hdmi-ddc-unwedge {
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rockchip,pins =
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<7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
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<7 RK_PC4 2 &pcfg_pull_none>;
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};
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};
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suspend {
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global_pwroff: global-pwroff {
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rockchip,pins =
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<0 RK_PA0 1 &pcfg_pull_none>;
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};
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ddrio_pwroff: ddrio-pwroff {
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rockchip,pins =
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<0 RK_PA1 1 &pcfg_pull_none>;
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};
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ddr0_retention: ddr0-retention {
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rockchip,pins =
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<0 RK_PA2 1 &pcfg_pull_up>;
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};
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ddr1_retention: ddr1-retention {
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rockchip,pins =
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<0 RK_PA3 1 &pcfg_pull_up>;
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};
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};
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edp {
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edp_hpd: edp-hpd {
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rockchip,pins =
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<7 RK_PB3 2 &pcfg_pull_down>;
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};
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};
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i2c0 {
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i2c0_xfer: i2c0-xfer {
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rockchip,pins =
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<0 RK_PB7 1 &pcfg_pull_none>,
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<0 RK_PC0 1 &pcfg_pull_none>;
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};
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};
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i2c1 {
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i2c1_xfer: i2c1-xfer {
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rockchip,pins =
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<8 RK_PA4 1 &pcfg_pull_none>,
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<8 RK_PA5 1 &pcfg_pull_none>;
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};
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};
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i2c2 {
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i2c2_xfer: i2c2-xfer {
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rockchip,pins =
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<6 RK_PB1 1 &pcfg_pull_none>,
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<6 RK_PB2 1 &pcfg_pull_none>;
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};
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};
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i2c3 {
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i2c3_xfer: i2c3-xfer {
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rockchip,pins =
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<2 RK_PC0 1 &pcfg_pull_none>,
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<2 RK_PC1 1 &pcfg_pull_none>;
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};
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};
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i2c4 {
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i2c4_xfer: i2c4-xfer {
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rockchip,pins =
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<7 RK_PC1 1 &pcfg_pull_none>,
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<7 RK_PC2 1 &pcfg_pull_none>;
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};
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};
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i2c5 {
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i2c5_xfer: i2c5-xfer {
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rockchip,pins =
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<7 RK_PC3 1 &pcfg_pull_none>,
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<7 RK_PC4 1 &pcfg_pull_none>;
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};
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};
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i2s0 {
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i2s0_bus: i2s0-bus {
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rockchip,pins =
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<6 RK_PA0 1 &pcfg_pull_none>,
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<6 RK_PA1 1 &pcfg_pull_none>,
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<6 RK_PA2 1 &pcfg_pull_none>,
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<6 RK_PA3 1 &pcfg_pull_none>,
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<6 RK_PA4 1 &pcfg_pull_none>;
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};
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i2s0_mclk: i2s0-mclk {
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rockchip,pins =
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<6 RK_PB0 1 &pcfg_pull_none>;
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};
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};
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lcdc {
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lcdc_rgb_pins: lcdc-rgb-pins {
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rockchip,pins =
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<1 RK_PD3 1 &pcfg_pull_none>, /* LCDC_DCLK */
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<1 RK_PD2 1 &pcfg_pull_none>, /* LCDC_DEN */
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<1 RK_PD1 1 &pcfg_pull_none>, /* LCDC_VSYNC */
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<1 RK_PD0 1 &pcfg_pull_none>; /* LCDC_HSYNC */
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};
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lcdc_sleep_pins: lcdc-sleep-pins {
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rockchip,pins =
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<1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */
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<1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */
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<1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */
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<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_HSYNC */
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};
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};
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sdmmc {
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sdmmc_clk: sdmmc-clk {
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rockchip,pins =
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<6 RK_PC4 1 &pcfg_pull_none>;
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};
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sdmmc_cmd: sdmmc-cmd {
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rockchip,pins =
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<6 RK_PC5 1 &pcfg_pull_up>;
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};
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sdmmc_cd: sdmmc-cd {
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rockchip,pins =
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<6 RK_PC6 1 &pcfg_pull_up>;
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};
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sdmmc_bus1: sdmmc-bus1 {
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rockchip,pins =
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<6 RK_PC0 1 &pcfg_pull_up>;
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};
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sdmmc_bus4: sdmmc-bus4 {
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rockchip,pins =
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<6 RK_PC0 1 &pcfg_pull_up>,
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<6 RK_PC1 1 &pcfg_pull_up>,
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<6 RK_PC2 1 &pcfg_pull_up>,
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<6 RK_PC3 1 &pcfg_pull_up>;
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};
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};
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sdio0 {
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sdio0_bus1: sdio0-bus1 {
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rockchip,pins =
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<4 RK_PC4 1 &pcfg_pull_up>;
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};
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sdio0_bus4: sdio0-bus4 {
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rockchip,pins =
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<4 RK_PC4 1 &pcfg_pull_up>,
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<4 RK_PC5 1 &pcfg_pull_up>,
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<4 RK_PC6 1 &pcfg_pull_up>,
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<4 RK_PC7 1 &pcfg_pull_up>;
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};
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sdio0_cmd: sdio0-cmd {
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rockchip,pins =
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<4 RK_PD0 1 &pcfg_pull_up>;
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};
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sdio0_clk: sdio0-clk {
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rockchip,pins =
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<4 RK_PD1 1 &pcfg_pull_none>;
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};
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sdio0_cd: sdio0-cd {
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rockchip,pins =
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<4 RK_PD2 1 &pcfg_pull_up>;
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};
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sdio0_wp: sdio0-wp {
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rockchip,pins =
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<4 RK_PD3 1 &pcfg_pull_up>;
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};
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sdio0_pwr: sdio0-pwr {
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rockchip,pins =
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<4 RK_PD4 1 &pcfg_pull_up>;
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};
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sdio0_bkpwr: sdio0-bkpwr {
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rockchip,pins =
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<4 RK_PD5 1 &pcfg_pull_up>;
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};
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sdio0_int: sdio0-int {
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rockchip,pins =
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<4 RK_PD6 1 &pcfg_pull_up>;
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};
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};
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sdio1 {
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sdio1_bus1: sdio1-bus1 {
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rockchip,pins =
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<3 RK_PD0 4 &pcfg_pull_up>;
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};
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sdio1_bus4: sdio1-bus4 {
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rockchip,pins =
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<3 RK_PD0 4 &pcfg_pull_up>,
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<3 RK_PD1 4 &pcfg_pull_up>,
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<3 RK_PD2 4 &pcfg_pull_up>,
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<3 RK_PD3 4 &pcfg_pull_up>;
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};
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sdio1_cd: sdio1-cd {
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rockchip,pins =
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<3 RK_PD4 4 &pcfg_pull_up>;
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};
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sdio1_wp: sdio1-wp {
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rockchip,pins =
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<3 RK_PD5 4 &pcfg_pull_up>;
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};
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sdio1_bkpwr: sdio1-bkpwr {
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rockchip,pins =
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<3 RK_PD6 4 &pcfg_pull_up>;
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};
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sdio1_int: sdio1-int {
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rockchip,pins =
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<3 RK_PD7 4 &pcfg_pull_up>;
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};
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sdio1_cmd: sdio1-cmd {
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rockchip,pins =
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<4 RK_PA6 4 &pcfg_pull_up>;
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};
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sdio1_clk: sdio1-clk {
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rockchip,pins =
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<4 RK_PA7 4 &pcfg_pull_none>;
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};
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sdio1_pwr: sdio1-pwr {
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rockchip,pins =
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<4 RK_PB1 4 &pcfg_pull_up>;
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};
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};
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emmc {
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emmc_clk: emmc-clk {
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rockchip,pins =
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<3 RK_PC2 2 &pcfg_pull_none>;
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};
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emmc_cmd: emmc-cmd {
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rockchip,pins =
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<3 RK_PC0 2 &pcfg_pull_up>;
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};
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emmc_pwr: emmc-pwr {
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rockchip,pins =
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<3 RK_PB1 2 &pcfg_pull_up>;
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};
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emmc_bus1: emmc-bus1 {
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rockchip,pins =
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<3 RK_PA0 2 &pcfg_pull_up>;
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};
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emmc_bus4: emmc-bus4 {
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rockchip,pins =
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<3 RK_PA0 2 &pcfg_pull_up>,
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<3 RK_PA1 2 &pcfg_pull_up>,
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<3 RK_PA2 2 &pcfg_pull_up>,
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<3 RK_PA3 2 &pcfg_pull_up>;
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};
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emmc_bus8: emmc-bus8 {
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rockchip,pins =
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<3 RK_PA0 2 &pcfg_pull_up>,
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<3 RK_PA1 2 &pcfg_pull_up>,
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<3 RK_PA2 2 &pcfg_pull_up>,
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<3 RK_PA3 2 &pcfg_pull_up>,
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<3 RK_PA4 2 &pcfg_pull_up>,
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<3 RK_PA5 2 &pcfg_pull_up>,
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<3 RK_PA6 2 &pcfg_pull_up>,
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<3 RK_PA7 2 &pcfg_pull_up>;
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};
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};
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spi0 {
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spi0_clk: spi0-clk {
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rockchip,pins =
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<5 RK_PB4 1 &pcfg_pull_up>;
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};
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spi0_cs0: spi0-cs0 {
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rockchip,pins =
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<5 RK_PB5 1 &pcfg_pull_up>;
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};
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spi0_tx: spi0-tx {
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rockchip,pins =
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<5 RK_PB6 1 &pcfg_pull_up>;
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};
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spi0_rx: spi0-rx {
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rockchip,pins =
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<5 RK_PB7 1 &pcfg_pull_up>;
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};
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spi0_cs1: spi0-cs1 {
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rockchip,pins =
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<5 RK_PC0 1 &pcfg_pull_up>;
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};
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};
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spi1 {
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spi1_clk: spi1-clk {
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rockchip,pins =
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<7 RK_PB4 2 &pcfg_pull_up>;
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};
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spi1_cs0: spi1-cs0 {
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rockchip,pins =
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<7 RK_PB5 2 &pcfg_pull_up>;
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};
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spi1_rx: spi1-rx {
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rockchip,pins =
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<7 RK_PB6 2 &pcfg_pull_up>;
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};
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spi1_tx: spi1-tx {
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rockchip,pins =
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<7 RK_PB7 2 &pcfg_pull_up>;
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};
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};
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spi2 {
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spi2_cs1: spi2-cs1 {
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rockchip,pins =
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<8 RK_PA3 1 &pcfg_pull_up>;
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};
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spi2_clk: spi2-clk {
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rockchip,pins =
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<8 RK_PA6 1 &pcfg_pull_up>;
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};
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spi2_cs0: spi2-cs0 {
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rockchip,pins =
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<8 RK_PA7 1 &pcfg_pull_up>;
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};
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spi2_rx: spi2-rx {
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rockchip,pins =
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<8 RK_PB0 1 &pcfg_pull_up>;
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};
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spi2_tx: spi2-tx {
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rockchip,pins =
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<8 RK_PB1 1 &pcfg_pull_up>;
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};
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};
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uart0 {
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uart0_xfer: uart0-xfer {
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rockchip,pins =
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<4 RK_PC0 1 &pcfg_pull_up>,
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<4 RK_PC1 1 &pcfg_pull_up>;
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};
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uart0_cts: uart0-cts {
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rockchip,pins =
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<4 RK_PC2 1 &pcfg_pull_up>;
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};
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uart0_rts: uart0-rts {
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rockchip,pins =
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<4 RK_PC3 1 &pcfg_pull_none>;
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};
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};
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uart1 {
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uart1_xfer: uart1-xfer {
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rockchip,pins =
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<5 RK_PB0 1 &pcfg_pull_up>,
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<5 RK_PB1 1 &pcfg_pull_up>;
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};
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uart1_cts: uart1-cts {
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rockchip,pins =
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<5 RK_PB2 1 &pcfg_pull_up>;
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};
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uart1_rts: uart1-rts {
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rockchip,pins =
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<5 RK_PB3 1 &pcfg_pull_none>;
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};
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};
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uart2 {
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uart2_xfer: uart2-xfer {
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rockchip,pins =
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<7 RK_PC6 1 &pcfg_pull_up>,
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<7 RK_PC7 1 &pcfg_pull_up>;
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};
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/* no rts / cts for uart2 */
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};
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uart3 {
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uart3_xfer: uart3-xfer {
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rockchip,pins =
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<7 RK_PA7 1 &pcfg_pull_up>,
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<7 RK_PB0 1 &pcfg_pull_up>;
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};
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uart3_cts: uart3-cts {
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rockchip,pins =
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<7 RK_PB1 1 &pcfg_pull_up>;
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};
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uart3_rts: uart3-rts {
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rockchip,pins =
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<7 RK_PB2 1 &pcfg_pull_none>;
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};
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};
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uart4 {
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uart4_xfer: uart4-xfer {
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rockchip,pins =
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<5 RK_PB7 3 &pcfg_pull_up>,
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<5 RK_PB6 3 &pcfg_pull_up>;
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};
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uart4_cts: uart4-cts {
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rockchip,pins =
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<5 RK_PB4 3 &pcfg_pull_up>;
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};
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uart4_rts: uart4-rts {
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rockchip,pins =
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<5 RK_PB5 3 &pcfg_pull_none>;
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};
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};
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tsadc {
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otp_pin: otp-pin {
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rockchip,pins =
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<0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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otp_out: otp-out {
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rockchip,pins =
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<0 RK_PB2 1 &pcfg_pull_none>;
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};
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};
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pwm0 {
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pwm0_pin: pwm0-pin {
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rockchip,pins =
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<7 RK_PA0 1 &pcfg_pull_none>;
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};
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pwm0_pin_pull_down: pwm0-pin-pull-down {
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rockchip,pins =
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<7 RK_PA0 1 &pcfg_pull_down>;
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};
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};
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pwm1 {
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pwm1_pin: pwm1-pin {
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rockchip,pins =
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<7 RK_PA1 1 &pcfg_pull_none>;
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};
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pwm1_pin_pull_down: pwm1-pin-pull-down {
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rockchip,pins =
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<7 RK_PA1 1 &pcfg_pull_down>;
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};
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};
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pwm2 {
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pwm2_pin: pwm2-pin {
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rockchip,pins =
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<7 RK_PC6 3 &pcfg_pull_none>;
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};
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pwm2_pin_pull_down: pwm2-pin-pull-down {
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rockchip,pins =
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<7 RK_PC6 3 &pcfg_pull_down>;
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};
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};
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pwm3 {
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pwm3_pin: pwm3-pin {
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rockchip,pins =
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<7 RK_PC7 3 &pcfg_pull_none>;
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};
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pwm3_pin_pull_down: pwm3-pin-pull-down {
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rockchip,pins =
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<7 RK_PC7 3 &pcfg_pull_down>;
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};
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};
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gmac {
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rgmii_pins: rgmii-pins {
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rockchip,pins =
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<3 RK_PD6 3 &pcfg_pull_none>,
|
|
<3 RK_PD7 3 &pcfg_pull_none>,
|
|
<3 RK_PD2 3 &pcfg_pull_none>,
|
|
<3 RK_PD3 3 &pcfg_pull_none>,
|
|
<3 RK_PD4 3 &pcfg_pull_none_drv_level_12>,
|
|
<3 RK_PD5 3 &pcfg_pull_none_drv_level_12>,
|
|
<3 RK_PD0 3 &pcfg_pull_none_drv_level_12>,
|
|
<3 RK_PD1 3 &pcfg_pull_none_drv_level_12>,
|
|
<4 RK_PA0 3 &pcfg_pull_none>,
|
|
<4 RK_PA5 3 &pcfg_pull_none>,
|
|
<4 RK_PA6 3 &pcfg_pull_none>,
|
|
<4 RK_PB1 3 &pcfg_pull_none_drv_level_12>,
|
|
<4 RK_PA4 3 &pcfg_pull_none_drv_level_12>,
|
|
<4 RK_PA1 3 &pcfg_pull_none>,
|
|
<4 RK_PA3 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
rmii_pins: rmii-pins {
|
|
rockchip,pins =
|
|
<3 RK_PD6 3 &pcfg_pull_none>,
|
|
<3 RK_PD7 3 &pcfg_pull_none>,
|
|
<3 RK_PD4 3 &pcfg_pull_none>,
|
|
<3 RK_PD5 3 &pcfg_pull_none>,
|
|
<4 RK_PA0 3 &pcfg_pull_none>,
|
|
<4 RK_PA5 3 &pcfg_pull_none>,
|
|
<4 RK_PA4 3 &pcfg_pull_none>,
|
|
<4 RK_PA1 3 &pcfg_pull_none>,
|
|
<4 RK_PA2 3 &pcfg_pull_none>,
|
|
<4 RK_PA3 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spdif {
|
|
spdif_tx: spdif-tx {
|
|
rockchip,pins =
|
|
<6 RK_PB3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
isp_pin {
|
|
isp_mipi: isp-mipi {
|
|
rockchip,pins =
|
|
/* cif_clkout */
|
|
<2 RK_PB3 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
isp_dvp_d2d9: isp-d2d9 {
|
|
rockchip,pins =
|
|
/* cif_data2 ... cif_data9 */
|
|
<2 RK_PA0 1 &pcfg_pull_none>,
|
|
<2 RK_PA1 1 &pcfg_pull_none>,
|
|
<2 RK_PA2 1 &pcfg_pull_none>,
|
|
<2 RK_PA3 1 &pcfg_pull_none>,
|
|
<2 RK_PA4 1 &pcfg_pull_none>,
|
|
<2 RK_PA5 1 &pcfg_pull_none>,
|
|
<2 RK_PA6 1 &pcfg_pull_none>,
|
|
<2 RK_PA7 1 &pcfg_pull_none>,
|
|
/* cif_sync, cif_href */
|
|
<2 RK_PB0 1 &pcfg_pull_none>,
|
|
<2 RK_PB1 1 &pcfg_pull_none>,
|
|
/* cif_clkin */
|
|
<2 RK_PB2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
isp_dvp_d0d1: isp-d0d1 {
|
|
rockchip,pins =
|
|
/* cif_data0, cif_data1 */
|
|
<2 RK_PB4 1 &pcfg_pull_none>,
|
|
<2 RK_PB5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
isp_dvp_d10d11: isp-d10d11 {
|
|
rockchip,pins =
|
|
/* cif_data10, cif_data11 */
|
|
<2 RK_PB6 1 &pcfg_pull_none>,
|
|
<2 RK_PB7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
isp_dvp_d0d7: isp-d0d7 {
|
|
rockchip,pins =
|
|
/* cif_data0 ... cif_data7 */
|
|
<2 RK_PB4 1 &pcfg_pull_none>,
|
|
<2 RK_PB5 1 &pcfg_pull_none>,
|
|
<2 RK_PA0 1 &pcfg_pull_none>,
|
|
<2 RK_PA1 1 &pcfg_pull_none>,
|
|
<2 RK_PA2 1 &pcfg_pull_none>,
|
|
<2 RK_PA3 1 &pcfg_pull_none>,
|
|
<2 RK_PA4 1 &pcfg_pull_none>,
|
|
<2 RK_PA5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
isp_shutter: isp-shutter {
|
|
rockchip,pins =
|
|
/* SHUTTEREN, SHUTTERTRIG */
|
|
<7 RK_PB4 2 &pcfg_pull_none>,
|
|
<7 RK_PB7 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
isp_flash_trigger: isp-flash-trigger {
|
|
rockchip,pins =
|
|
/* ISP_FLASHTRIGOU */
|
|
<7 RK_PB5 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
isp_prelight: isp-prelight {
|
|
rockchip,pins =
|
|
/* ISP_PRELIGHTTRIG */
|
|
<7 RK_PB6 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
|
|
rockchip,pins =
|
|
/* ISP_FLASHTRIGOU */
|
|
<7 RK_PB5 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
cif_pin {
|
|
cif_dvp_d0d1: cif-dvp-d0d1 {
|
|
rockchip,pins =
|
|
<2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
|
|
<2 RK_PB5 1 &pcfg_pull_none>; /* cif_data1 */
|
|
};
|
|
|
|
cif_dvp_d2d9: cif-dvp-d2d9 {
|
|
rockchip,pins =
|
|
<2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
|
|
<2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
|
|
<2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
|
|
<2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
|
|
<2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
|
|
<2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
|
|
<2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
|
|
<2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
|
|
<2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
|
|
<2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
|
|
<2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
|
|
<2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
|
|
};
|
|
|
|
cif_dvp_d10d11: cif-dvp-d10d11 {
|
|
rockchip,pins =
|
|
<2 RK_PB6 1 &pcfg_pull_none>, /* cif_data10 */
|
|
<2 RK_PB7 1 &pcfg_pull_none>; /* cif_data11 */
|
|
};
|
|
};
|
|
};
|