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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*/
#include <dt-bindings/display/mipi_dsi.h>
#include <dt-bindings/display/drm_mipi_dsi.h>
#include <dt-bindings/display/media-bus-format.h>
/ {
chosen: chosen {
bootargs = "earlycon=uart8250,mmio32,0x20068000";
};
cpuinfo {
compatible = "rockchip,cpuinfo";
nvmem-cells = <&efuse_id>;
nvmem-cell-names = "id";
};
fiq-debugger {
compatible = "rockchip,fiq-debugger";
rockchip,serial-id = <2>;
rockchip,signal-irq = <159>;
rockchip,wake-irq = <0>;
/* If enable uart uses irq instead of fiq */
rockchip,irq-mode-enable = <1>;
rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
};
firmware {
firmware_android: android {};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
cma_region: region@63000000 {
compatible = "shared-dma-pool";
reusable;
reg = <0x63000000 0x1800000>;
};
ramoops: ramoops@62e00000 {
compatible = "ramoops";
reg = <0x62e00000 0xf0000>;
record-size = <0x20000>;
console-size = <0x80000>;
ftrace-size = <0x00000>;
pmsg-size = <0x50000>;
};
drm_logo: drm-logo@0 {
compatible = "rockchip,drm-logo";
reg = <0x0 0x0>;
};
};
};
&cif_new {
memory-region = <&cma_region>;
};
&dfi {
status = "okay";
};
&display_subsystem {
memory-region = <&cma_region>;
logo-memory-region = <&drm_logo>;
status = "okay";
route {
route_dsi: route-dsi {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vop_out_dsi>;
};
route_lvds: route-lvds {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vop_out_lvds>;
};
route_rgb: route-rgb {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vop_out_rgb>;
};
};
};
&dmc {
vop-dclk-mode = <1>;
status = "okay";
};
&dsi {
panel@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi: endpoint {
remote-endpoint = <&dsi_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi>;
};
};
};
};
&video_phy {
status = "okay";
};