60 lines
1.7 KiB
Plaintext
60 lines
1.7 KiB
Plaintext
Rockchip SuperSpeed DWC3 USB SoC controller with INNO USB3 PHY inside
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Required properties:
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- compatible : should be one of the listed compatibles:
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* "rockchip,rk3328-dwc3"
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* "rockchip,rk322xh-dwc3"
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- clocks : a list of phandle + clock-specifier pairs for the
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clocks listed in clock-names.
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- clock-names : Should contain the following:
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* "ref_clk" for controller reference clk, have to be 24 MHz
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* "suspend_clk" for controller suspend clk, have to be 24 MHz or 32 KHz
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* "bus_clk" for master/Core clock, have to be >= 62.5 MHz for SS
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operation and >= 30MHz for HS operation.
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Required child node:
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A child node must exist to represent the core DWC3 IP block. The name of
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the node is not important. The content of the node is defined in dwc3.txt.
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Phy documentation is provided in the following places:
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Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.txt
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Example device nodes:
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u3phy: usb3-phy@ff470000 {
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compatible = "rockchip,rk3328-u3phy";
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reg = <0x0 0xff470000 0x0 0x0>;
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...
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u3phy_utmi: utmi@ff470000 {
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reg = <0x0 0xff470000 0x0 0x8000>;
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#phy-cells = <0>;
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};
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u3phy_pipe: pipe@ff478000 {
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reg = <0x0 0xff478000 0x0 0x8000>;
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#phy-cells = <0>;
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};
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};
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usbdrd3: usb@ff600000 {
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compatible = "rockchip,rk3328-dwc3";
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clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
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<&cru ACLK_USB3OTG>;
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clock-names = "ref_clk", "suspend_clk",
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"bus_clk";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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usbdrd_dwc3: dwc3@ff600000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xff600000 0x0 0x100000>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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dr_mode = "host";
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phys = <&u3phy_utmi>, <&u3phy_pipe>;
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phy-names = "usb2-phy", "usb3-phy";
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phy_type = "utmi_wide";
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};
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};
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