239 lines
4.3 KiB
Plaintext
239 lines
4.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include <dt-bindings/display/media-bus-format.h>
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#include "rk3576.dtsi"
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#include "rk3576-cpu-swap.dtsi"
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#include "rk3576-evb2.dtsi"
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#include "rk3576-evb2-rk628-bt1120-to-hdmi.dtsi"
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#include "rk3576-evb2-rk628-hdmi2csi.dtsi"
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#include "rk3576-linux.dtsi"
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/ {
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model = "Rockchip RK3576 EVB2 V10 NVR Board";
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compatible = "rockchip,rk3576-nvr-v10", "rockchip,rk3576";
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};
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&cluster0_opp_table {
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/delete-node/ opp-408000000;
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/delete-node/ opp-600000000;
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/delete-node/ opp-816000000;
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/delete-node/ opp-1008000000;
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/delete-node/ opp-1200000000;
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/delete-node/ opp-1416000000;
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/delete-node/ opp-2208000000;
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};
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&cluster1_opp_table {
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/delete-node/ opp-408000000;
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/delete-node/ opp-600000000;
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/delete-node/ opp-816000000;
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/delete-node/ opp-1008000000;
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/delete-node/ opp-1200000000;
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/delete-node/ opp-1416000000;
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/delete-node/ opp-2304000000;
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};
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&display_subsystem {
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/delete-property/ clkcks;
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/delete-property/ clocks-names;
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};
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&dmc {
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status = "okay";
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center-supply = <&vdd_ddr_s0>;
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mem-supply = <&vdd_logic_s0>;
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system-status-level = <
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/* system status freq level */
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SYS_STATUS_NORMAL DMC_FREQ_LEVEL_HIGH
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SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH
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SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW
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SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH
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SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH
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SYS_STATUS_VIDEO_SVEP DMC_FREQ_LEVEL_MID_HIGH
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SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH
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SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH
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SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH
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SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH
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SYS_STATUS_HDMIRX DMC_FREQ_LEVEL_HIGH
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SYS_STATUS_DEEP_SUSPEND DMC_FREQ_LEVEL_HIGH
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>;
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auto-freq-en = <0>;
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};
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&dp0_in_vp0 {
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status = "okay";
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};
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&dp0_in_vp1 {
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status = "okay";
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};
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&dp0_in_vp2 {
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status = "okay";
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};
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&hdmi_in_vp0 {
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status = "okay";
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};
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&hdmi_in_vp1 {
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status = "okay";
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};
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&hdmi_in_vp2 {
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status = "okay";
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};
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&npu_opp_table {
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/delete-node/ opp-1000000000;
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};
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&rgb_in_vp1 {
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status = "okay";
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};
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&rgb_in_vp2 {
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status = "okay";
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};
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&route_dp0 {
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status = "okay";
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connect = <&vp0_out_dp0>;
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force-output;
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force_timing {
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clock-frequency = <65000000>;
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hactive = <1024>;
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vactive = <768>;
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hfront-porch = <24>;
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hsync-len = <136>;
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hback-porch = <160>;
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vfront-porch = <3>;
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vsync-len = <6>;
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vback-porch = <29>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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};
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&route_hdmi {
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status = "okay";
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connect = <&vp0_out_hdmi>;
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force-output;
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force_timing {
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clock-frequency = <65000000>;
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hactive = <1024>;
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vactive = <768>;
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hfront-porch = <24>;
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hsync-len = <136>;
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hback-porch = <160>;
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vfront-porch = <3>;
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vsync-len = <6>;
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vback-porch = <29>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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};
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&route_rgb {
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status = "okay";
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connect = <&vp1_out_rgb>;
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force-bus-format = <MEDIA_BUS_FMT_YUYV8_1X16>;
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force-output;
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force_timing {
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clock-frequency = <65000000>;
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hactive = <1024>;
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vactive = <768>;
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hfront-porch = <24>;
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hsync-len = <136>;
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hback-porch = <160>;
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vfront-porch = <3>;
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vsync-len = <6>;
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vback-porch = <29>;
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hsync-active = <1>;
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vsync-active = <1>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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};
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&rk628d {
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display-timings {
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src-timing {
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clock-frequency = <65000000>;
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hactive = <1024>;
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vactive = <768>;
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hfront-porch = <24>;
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hsync-len = <136>;
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hback-porch = <160>;
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vfront-porch = <3>;
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vsync-len = <6>;
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vback-porch = <29>;
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hsync-active = <1>;
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vsync-active = <1>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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dst-timing {
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clock-frequency = <65000000>;
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hactive = <1024>;
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vactive = <768>;
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hfront-porch = <24>;
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hsync-len = <136>;
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hback-porch = <160>;
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vfront-porch = <3>;
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vsync-len = <6>;
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vback-porch = <29>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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};
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};
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&rkisp_vir0_sditf {
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status = "okay";
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};
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&rkvpss {
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status = "okay";
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};
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&rkvpss_mmu {
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status = "okay";
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};
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&rkvpss_vir0 {
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status = "okay";
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};
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&vp0 {
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assigned-clocks = <&cru DCLK_VP0_SRC>;
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assigned-clock-parents = <&cru PLL_VPLL>;
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};
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&vp1 {
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assigned-clocks = <&cru DCLK_VP1_SRC>;
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assigned-clock-parents = <&cru PLL_VPLL>;
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};
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&vp2 {
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assigned-clocks = <&cru DCLK_VP2_SRC>;
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assigned-clock-parents = <&cru PLL_GPLL>;
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};
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