CoolPi-Armbian-Rockchip-RK3.../arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2lvds0-lp4x-v10.dts

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include <dt-bindings/display/rockchip_vop.h>
#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi"
#include "rk3568-android.dtsi"
&backlight {
pwms = <&pwm4 0 25000 0>;
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <10000>;
};
&dsi1 {
status = "disabled";
};
&dsi0_in_vp0 {
status = "okay";
};
&dsi0_in_vp1 {
status = "disabled";
};
/delete-node/ &dsi0_panel;
&pwm4 {
pinctrl-names = "active";
pinctrl-0 = <&pwm4_pins>;
status = "okay";
};
&video_phy0 {
status = "okay";
};
&dsi0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi0_out_rkx110_x120: endpoint {
remote-endpoint = <&rkx110_x120_in_dsi0>;
};
};
};
};
&rkx110_x120 {
remote1-addr = <0x54>;
};
&serdes_timing0 {
clock-frequency = <100000000>;
hactive = <2048>;
vactive = <600>;
hfront-porch = <320>;
hsync-len = <40>;
hback-porch = <280>;
vfront-porch = <12>;
vsync-len = <3>;
vback-porch = <20>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
};
&serdes_panel {
local-port0 = <RK_SERDES_DSI_RX0>;
remote0-port0 = <RK_SERDES_LVDS_TX0>;
remote1-port0 = <RK_SERDES_LVDS_TX0>;
rockchip,split-mode;
backlight = <&backlight>;
enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
rkx110_x120_in_dsi0: endpoint {
remote-endpoint = <&dsi0_out_rkx110_x120>;
};
};
};
};
/* vp0 for HDMI, vp2 for rgb */
&vp0 {
rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 |
1 << ROCKCHIP_VOP2_SMART0)>;
rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>;
};
&vp2 {
rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 |
1 << ROCKCHIP_VOP2_SMART1)>;
rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>;
};