637 lines
20 KiB
C
637 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* techpoint lib
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*
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* Copyright (C) 2023 Rockchip Electronics Co., Ltd.
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*/
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#include "techpoint_tp9951.h"
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#include "techpoint_dev.h"
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static struct techpoint_video_modes supported_modes[] = {
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#if TP9951_DEF_PAL
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{
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.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
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.width = 960,
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.height = 576,
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.max_fps = {
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.numerator = 10000,
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.denominator = 250000,
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},
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.link_freq_value = TP9951_LINK_FREQ_148M,
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.common_reg_list = NULL,
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.common_reg_size = 0,
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.bpp = TP9951_BITS_PER_SAMPLE,
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.lane = TP9951_LANES,
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.vc[PAD0] = 0,
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.vc[PAD1] = 1,
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.vc[PAD2] = 2,
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.vc[PAD3] = 3,
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},
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#endif
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#if TP9951_DEF_NTSC
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{
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.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
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.width = 960,
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.height = 480,
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.max_fps = {
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.numerator = 10000,
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.denominator = 250000,
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},
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.link_freq_value = TP9951_LINK_FREQ_148M,
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.common_reg_list = NULL,
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.common_reg_size = 0,
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.bpp = TP9951_BITS_PER_SAMPLE,
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.lane = TP9951_LANES,
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.vc[PAD0] = 0,
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.vc[PAD1] = 1,
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.vc[PAD2] = 2,
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.vc[PAD3] = 3,
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},
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#endif
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#if TP9951_DEF_1080P
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{
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.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
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.width = 1920,
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.height = 1080,
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.max_fps = {
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.numerator = 10000,
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.denominator = 250000,
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},
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.link_freq_value = TP9951_LINK_FREQ_594M,
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//.link_freq_value = TP9951_LINK_FREQ_297M,
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.common_reg_list = NULL,
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.common_reg_size = 0,
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.bpp = TP9951_BITS_PER_SAMPLE,
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.lane = TP9951_LANES,
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.vc[PAD0] = 0,
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.vc[PAD1] = 1,
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.vc[PAD2] = 2,
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.vc[PAD3] = 3,
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},
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#endif
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#if TP9951_DEF_720P
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{
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.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
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.width = 1280,
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.height = 720,
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.max_fps = {
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.numerator = 10000,
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.denominator = 250000,
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},
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.link_freq_value = TP9951_LINK_FREQ_297M,
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.common_reg_list = NULL,
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.common_reg_size = 0,
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.bpp = TP9951_BITS_PER_SAMPLE,
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.lane = TP9951_LANES,
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.vc[PAD0] = 0,
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.vc[PAD1] = 1,
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.vc[PAD2] = 2,
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.vc[PAD3] = 3,
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},
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#endif
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};
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int tp9951_initialize(struct techpoint *techpoint)
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{
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int array_size = 0;
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struct i2c_client *client = techpoint->client;
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struct device *dev = &client->dev;
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techpoint->video_modes_num = ARRAY_SIZE(supported_modes);
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array_size =
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sizeof(struct techpoint_video_modes) * techpoint->video_modes_num;
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techpoint->video_modes = devm_kzalloc(dev, array_size, GFP_KERNEL);
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memcpy(techpoint->video_modes, supported_modes, array_size);
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techpoint->cur_video_mode = &techpoint->video_modes[0];
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return 0;
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}
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int tp9951_get_channel_input_status(struct techpoint *techpoint, u8 ch)
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{
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u8 val = 0;
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struct i2c_client *client = techpoint->client;
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if (ch != 0) // tp9951 just support 1 chn
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return 0;
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techpoint_write_reg(client, PAGE_REG, ch);
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techpoint_read_reg(client, INPUT_STATUS_REG, &val);
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dev_dbg(&client->dev, "input_status ch %d : %x\n", ch, val);
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return (val & INPUT_STATUS_MASK) ? 0 : 1;
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}
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int tp9951_get_all_input_status(struct techpoint *techpoint, u8 *detect_status)
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{
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u8 val = 0;
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struct i2c_client *client = techpoint->client;
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// tp9951 just support 1 chn
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techpoint_write_reg(client, PAGE_REG, 0);
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techpoint_read_reg(client, INPUT_STATUS_REG, &val);
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detect_status[0] = tp9951_get_channel_input_status(techpoint, 0);
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return 0;
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}
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static void tp9951_set_mipi_out(struct i2c_client *client,
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enum techpoint_support_reso reso,
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unsigned char lane)
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{
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u8 tmp;
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//mipi setting
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techpoint_write_reg(client, PAGE_REG, 0x08); //select MIPI page
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techpoint_write_reg(client, 0x02, 0x7d);
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techpoint_write_reg(client, 0x03, 0x75);
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techpoint_write_reg(client, 0x04, 0x75);
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techpoint_write_reg(client, 0x13, 0xef);
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techpoint_write_reg(client, 0x20, 0x00);
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techpoint_write_reg(client, 0x23, 0x9e);
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if (lane == MIPI_1LANE) {
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techpoint_write_reg(client, 0x21, 0x11);
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if (TECHPOINT_S_RESO_1080P_30 == reso || TECHPOINT_S_RESO_1080P_25 == reso) {
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techpoint_write_reg(client, 0x12, 0x54);
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techpoint_write_reg(client, 0x14, 0x00);
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techpoint_write_reg(client, 0x15, 0x02);
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techpoint_write_reg(client, 0x2a, 0x08);
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techpoint_write_reg(client, 0x2b, 0x06);
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techpoint_write_reg(client, 0x2c, 0x12);
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techpoint_write_reg(client, 0x2e, 0x0a);
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} else if (TECHPOINT_S_RESO_720P_30 == reso || TECHPOINT_S_RESO_720P_25 == reso) {
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techpoint_write_reg(client, 0x12, 0x54);
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techpoint_write_reg(client, 0x14, 0x00);
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techpoint_write_reg(client, 0x15, 0x12);
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techpoint_write_reg(client, 0x2a, 0x04);
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techpoint_write_reg(client, 0x2b, 0x03);
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techpoint_write_reg(client, 0x2c, 0x0a);
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techpoint_write_reg(client, 0x2e, 0x02);
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} else if (TECHPOINT_S_RESO_NTSC == reso || TECHPOINT_S_RESO_PAL == reso) {
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techpoint_write_reg(client, 0x12, 0x54);
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techpoint_write_reg(client, 0x14, 0x51);
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techpoint_write_reg(client, 0x15, 0x07);
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techpoint_write_reg(client, 0x2a, 0x02);
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techpoint_write_reg(client, 0x2b, 0x01);
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techpoint_write_reg(client, 0x2c, 0x06);
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techpoint_write_reg(client, 0x2e, 0x02);
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}
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} else { // 2 lane
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techpoint_write_reg(client, 0x21, 0x12);
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if (TECHPOINT_S_RESO_1080P_30 == reso || TECHPOINT_S_RESO_1080P_25 == reso) {
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techpoint_write_reg(client, 0x12, 0x54);
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techpoint_write_reg(client, 0x14, 0x41);
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techpoint_write_reg(client, 0x15, 0x02);
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techpoint_write_reg(client, 0x2a, 0x04);
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techpoint_write_reg(client, 0x2b, 0x03);
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techpoint_write_reg(client, 0x2c, 0x0a);
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techpoint_write_reg(client, 0x2e, 0x02);
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} else if (TECHPOINT_S_RESO_720P_30 == reso || TECHPOINT_S_RESO_720P_25 == reso) {
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techpoint_write_reg(client, 0x12, 0x54);
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techpoint_write_reg(client, 0x14, 0x41);
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techpoint_write_reg(client, 0x15, 0x12);
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techpoint_write_reg(client, 0x2a, 0x02);
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techpoint_write_reg(client, 0x2b, 0x01);
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techpoint_write_reg(client, 0x2c, 0x06);
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techpoint_write_reg(client, 0x2e, 0x02);
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} else if (TECHPOINT_S_RESO_NTSC == reso || TECHPOINT_S_RESO_PAL == reso) {
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techpoint_write_reg(client, 0x12, 0x54);
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techpoint_write_reg(client, 0x14, 0x62);
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techpoint_write_reg(client, 0x15, 0x07);
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techpoint_write_reg(client, 0x2a, 0x02);
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techpoint_write_reg(client, 0x2b, 0x00);
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techpoint_write_reg(client, 0x2c, 0x04);
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techpoint_write_reg(client, 0x2e, 0x02);
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}
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}
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techpoint_write_reg(client, PAGE_REG, 0x00); //back to decoder page
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techpoint_read_reg(client, 0x06, &tmp); //PLL reset
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techpoint_write_reg(client, 0x06, 0x80 | tmp);
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techpoint_write_reg(client, PAGE_REG, 0x08); //back to mipi page
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techpoint_read_reg(client, 0x14, &tmp); //PLL reset
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techpoint_write_reg(client, 0x14, 0x80 | tmp);
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techpoint_write_reg(client, 0x14, tmp);
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/* Enable MIPI CSI2 output */
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techpoint_write_reg(client, 0x28, 0x02); //stream off
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techpoint_write_reg(client, 0x28, 0x00); //stream on
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techpoint_write_reg(client, PAGE_REG, 0x00); //back to decoder page
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}
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int tp9951_set_channel_reso(struct i2c_client *client, int ch,
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enum techpoint_support_reso reso)
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{
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int val = reso;
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dev_info(&client->dev, "##$$ %s", __func__);
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techpoint_write_reg(client, 0x40, 0x00); //select decoder page
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techpoint_write_reg(client, 0x06, 0x12); //default value
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techpoint_write_reg(client, 0x42, 0x00); //common setting for all format
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techpoint_write_reg(client, 0x4e, 0x00); //common setting for MIPI output
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techpoint_write_reg(client, 0x54, 0x00); //common setting for MIPI output
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techpoint_write_reg(client, 0x41, ch); //video MUX select
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switch (val) {
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case TECHPOINT_S_RESO_720P_25:
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#if TP9951_DEF_720P
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default:
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#endif
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dev_err(&client->dev, "set channel 720P_25\n");
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techpoint_write_reg(client, 0x02, 0x42);
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techpoint_write_reg(client, 0x07, 0xc0);
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techpoint_write_reg(client, 0x0b, 0xc0);
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techpoint_write_reg(client, 0x0c, 0x13);
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techpoint_write_reg(client, 0x0d, 0x50);
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techpoint_write_reg(client, 0x15, 0x13);
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techpoint_write_reg(client, 0x16, 0x15);
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techpoint_write_reg(client, 0x17, 0x00);
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techpoint_write_reg(client, 0x18, 0x19);
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techpoint_write_reg(client, 0x19, 0xd0);
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techpoint_write_reg(client, 0x1a, 0x25);
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techpoint_write_reg(client, 0x1c, 0x07);//1280*720, 25fps
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techpoint_write_reg(client, 0x1d, 0xbc);//1280*720, 25fps
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techpoint_write_reg(client, 0x20, 0x30);
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techpoint_write_reg(client, 0x21, 0x84);
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techpoint_write_reg(client, 0x22, 0x36);
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techpoint_write_reg(client, 0x23, 0x3c);
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techpoint_write_reg(client, 0x2b, 0x60);
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techpoint_write_reg(client, 0x2c, 0x2a);
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techpoint_write_reg(client, 0x2d, 0x30);
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techpoint_write_reg(client, 0x2e, 0x70);
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techpoint_write_reg(client, 0x30, 0x48);
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techpoint_write_reg(client, 0x31, 0xbb);
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techpoint_write_reg(client, 0x32, 0x2e);
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techpoint_write_reg(client, 0x33, 0x90);
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techpoint_write_reg(client, 0x35, 0x25);
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techpoint_write_reg(client, 0x38, 0x00);
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techpoint_write_reg(client, 0x39, 0x18);
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if (STD_HDA) {
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techpoint_write_reg(client, 0x02, 0x46);
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techpoint_write_reg(client, 0x0d, 0x71);
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techpoint_write_reg(client, 0x18, 0x1b);
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techpoint_write_reg(client, 0x20, 0x40);
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techpoint_write_reg(client, 0x21, 0x46);
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techpoint_write_reg(client, 0x25, 0xfe);
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techpoint_write_reg(client, 0x26, 0x01);
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techpoint_write_reg(client, 0x2c, 0x3a);
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techpoint_write_reg(client, 0x2d, 0x5a);
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techpoint_write_reg(client, 0x2e, 0x40);
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techpoint_write_reg(client, 0x30, 0x9e);
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techpoint_write_reg(client, 0x31, 0x20);
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techpoint_write_reg(client, 0x32, 0x10);
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techpoint_write_reg(client, 0x33, 0x90);
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}
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tp9951_set_mipi_out(client, reso, MIPI_2LANE); // 2 lane
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break;
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case TECHPOINT_S_RESO_1080P_25: // FHD25
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#if TP9951_DEF_1080P
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default:
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#endif
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dev_err(&client->dev, "set channel 1080P_25\n");
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techpoint_write_reg(client, 0x02, 0x40);
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techpoint_write_reg(client, 0x07, 0xc0);
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techpoint_write_reg(client, 0x0b, 0xc0);
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techpoint_write_reg(client, 0x0c, 0x03);
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techpoint_write_reg(client, 0x0d, 0x50);
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techpoint_write_reg(client, 0x15, 0x03);
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techpoint_write_reg(client, 0x16, 0xd2);
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techpoint_write_reg(client, 0x17, 0x80);
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techpoint_write_reg(client, 0x18, 0x29);
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techpoint_write_reg(client, 0x19, 0x38);
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techpoint_write_reg(client, 0x1a, 0x47);
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techpoint_write_reg(client, 0x1c, 0x0a); //1920*1080, 25fps
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techpoint_write_reg(client, 0x1d, 0x50);
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techpoint_write_reg(client, 0x20, 0x30);
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techpoint_write_reg(client, 0x21, 0x84);
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techpoint_write_reg(client, 0x22, 0x36);
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techpoint_write_reg(client, 0x23, 0x3c);
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techpoint_write_reg(client, 0x2b, 0x60);
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techpoint_write_reg(client, 0x2c, 0x2a);
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techpoint_write_reg(client, 0x2d, 0x30);
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techpoint_write_reg(client, 0x2e, 0x70);
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techpoint_write_reg(client, 0x30, 0x48);
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techpoint_write_reg(client, 0x31, 0xbb);
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techpoint_write_reg(client, 0x32, 0x2e);
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techpoint_write_reg(client, 0x33, 0x90);
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techpoint_write_reg(client, 0x35, 0x05);
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techpoint_write_reg(client, 0x38, 0x00);
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techpoint_write_reg(client, 0x39, 0x1C);
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if (STD_HDA) {
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techpoint_write_reg(client, 0x02, 0x44);
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techpoint_write_reg(client, 0x0d, 0x73);
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techpoint_write_reg(client, 0x15, 0x01);
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techpoint_write_reg(client, 0x16, 0xf0);
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techpoint_write_reg(client, 0x18, 0x2a);
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techpoint_write_reg(client, 0x20, 0x3c);
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techpoint_write_reg(client, 0x21, 0x46);
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techpoint_write_reg(client, 0x25, 0xfe);
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techpoint_write_reg(client, 0x26, 0x0d);
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techpoint_write_reg(client, 0x2c, 0x3a);
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techpoint_write_reg(client, 0x2d, 0x54);
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techpoint_write_reg(client, 0x2e, 0x40);
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techpoint_write_reg(client, 0x30, 0xa5);
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techpoint_write_reg(client, 0x31, 0x86);
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techpoint_write_reg(client, 0x32, 0xfb);
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techpoint_write_reg(client, 0x33, 0x60);
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}
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tp9951_set_mipi_out(client, reso, MIPI_2LANE); // 2 lane
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break;
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case TECHPOINT_S_RESO_1080P_30: // FHD30
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dev_err(&client->dev, "set channel PAL\n");
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techpoint_write_reg(client, 0x02, 0x40);
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techpoint_write_reg(client, 0x07, 0xc0);
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techpoint_write_reg(client, 0x0b, 0xc0);
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techpoint_write_reg(client, 0x0c, 0x03);
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techpoint_write_reg(client, 0x0d, 0x50);
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techpoint_write_reg(client, 0x15, 0x03);
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techpoint_write_reg(client, 0x16, 0xd2);
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techpoint_write_reg(client, 0x17, 0x80);
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techpoint_write_reg(client, 0x18, 0x29);
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techpoint_write_reg(client, 0x19, 0x38);
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techpoint_write_reg(client, 0x1a, 0x47);
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techpoint_write_reg(client, 0x1c, 0x08); //1920*1080, 30fps
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techpoint_write_reg(client, 0x1d, 0x98); //
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techpoint_write_reg(client, 0x20, 0x30);
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techpoint_write_reg(client, 0x21, 0x84);
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techpoint_write_reg(client, 0x22, 0x36);
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techpoint_write_reg(client, 0x23, 0x3c);
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techpoint_write_reg(client, 0x2b, 0x60);
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techpoint_write_reg(client, 0x2c, 0x2a);
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techpoint_write_reg(client, 0x2d, 0x30);
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techpoint_write_reg(client, 0x2e, 0x70);
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techpoint_write_reg(client, 0x30, 0x48);
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techpoint_write_reg(client, 0x31, 0xbb);
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techpoint_write_reg(client, 0x32, 0x2e);
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techpoint_write_reg(client, 0x33, 0x90);
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techpoint_write_reg(client, 0x35, 0x05);
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techpoint_write_reg(client, 0x38, 0x00);
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techpoint_write_reg(client, 0x39, 0x1C);
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if (STD_HDA) { //AHD1080p30 extra
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techpoint_write_reg(client, 0x02, 0x44);
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techpoint_write_reg(client, 0x0d, 0x72);
|
|
|
|
techpoint_write_reg(client, 0x15, 0x01);
|
|
techpoint_write_reg(client, 0x16, 0xf0);
|
|
techpoint_write_reg(client, 0x18, 0x2a);
|
|
|
|
techpoint_write_reg(client, 0x20, 0x38);
|
|
techpoint_write_reg(client, 0x21, 0x46);
|
|
|
|
techpoint_write_reg(client, 0x25, 0xfe);
|
|
techpoint_write_reg(client, 0x26, 0x0d);
|
|
|
|
techpoint_write_reg(client, 0x2c, 0x3a);
|
|
techpoint_write_reg(client, 0x2d, 0x54);
|
|
techpoint_write_reg(client, 0x2e, 0x40);
|
|
|
|
techpoint_write_reg(client, 0x30, 0xa5);
|
|
techpoint_write_reg(client, 0x31, 0x95);
|
|
techpoint_write_reg(client, 0x32, 0xe0);
|
|
techpoint_write_reg(client, 0x33, 0x60);
|
|
}
|
|
|
|
tp9951_set_mipi_out(client, reso, MIPI_2LANE); // 2 lane
|
|
break;
|
|
|
|
case TECHPOINT_S_RESO_PAL:
|
|
#if TP9951_DEF_PAL
|
|
default:
|
|
#endif
|
|
|
|
#if CVBS_960H
|
|
dev_err(&client->dev, "set channel CVBS_960H\n");
|
|
|
|
techpoint_write_reg(client, 0x02, 0x47);
|
|
techpoint_write_reg(client, 0x0c, 0x13);
|
|
techpoint_write_reg(client, 0x0d, 0x51);
|
|
|
|
techpoint_write_reg(client, 0x15, 0x13);
|
|
techpoint_write_reg(client, 0x16, 0x76);
|
|
techpoint_write_reg(client, 0x17, 0x80);
|
|
techpoint_write_reg(client, 0x18, 0x17);
|
|
techpoint_write_reg(client, 0x19, 0x20);
|
|
techpoint_write_reg(client, 0x1a, 0x17);
|
|
techpoint_write_reg(client, 0x1c, 0x09);
|
|
techpoint_write_reg(client, 0x1d, 0x48);
|
|
|
|
techpoint_write_reg(client, 0x20, 0x48);
|
|
techpoint_write_reg(client, 0x21, 0x84);
|
|
techpoint_write_reg(client, 0x22, 0x37);
|
|
techpoint_write_reg(client, 0x23, 0x3f);
|
|
|
|
techpoint_write_reg(client, 0x2b, 0x70);
|
|
techpoint_write_reg(client, 0x2c, 0x2a);
|
|
techpoint_write_reg(client, 0x2d, 0x64);
|
|
techpoint_write_reg(client, 0x2e, 0x56);
|
|
|
|
techpoint_write_reg(client, 0x30, 0x7a);
|
|
techpoint_write_reg(client, 0x31, 0x4a);
|
|
techpoint_write_reg(client, 0x32, 0x4d);
|
|
techpoint_write_reg(client, 0x33, 0xf0);
|
|
|
|
techpoint_write_reg(client, 0x35, 0x65);
|
|
techpoint_write_reg(client, 0x38, 0x00);
|
|
techpoint_write_reg(client, 0x39, 0x04);
|
|
|
|
#else //PAL 720H
|
|
dev_err(&client->dev, "set channel PAL 720H\n");
|
|
techpoint_write_reg(client, 0x02, 0x47);
|
|
techpoint_write_reg(client, 0x06, 0x32);
|
|
techpoint_write_reg(client, 0x0c, 0x13);
|
|
techpoint_write_reg(client, 0x0d, 0x51);
|
|
|
|
techpoint_write_reg(client, 0x15, 0x03);
|
|
techpoint_write_reg(client, 0x16, 0xf0);
|
|
techpoint_write_reg(client, 0x17, 0xa0);
|
|
techpoint_write_reg(client, 0x18, 0x17);
|
|
techpoint_write_reg(client, 0x19, 0x20);
|
|
techpoint_write_reg(client, 0x1a, 0x15);
|
|
techpoint_write_reg(client, 0x1c, 0x06);
|
|
techpoint_write_reg(client, 0x1d, 0xc0);
|
|
|
|
techpoint_write_reg(client, 0x20, 0x48);
|
|
techpoint_write_reg(client, 0x21, 0x84);
|
|
techpoint_write_reg(client, 0x22, 0x37);
|
|
techpoint_write_reg(client, 0x23, 0x3f);
|
|
|
|
techpoint_write_reg(client, 0x2b, 0x70);
|
|
techpoint_write_reg(client, 0x2c, 0x2a);
|
|
techpoint_write_reg(client, 0x2d, 0x4b);
|
|
techpoint_write_reg(client, 0x2e, 0x56);
|
|
|
|
techpoint_write_reg(client, 0x30, 0x7a);
|
|
techpoint_write_reg(client, 0x31, 0x4a);
|
|
techpoint_write_reg(client, 0x32, 0x4d);
|
|
techpoint_write_reg(client, 0x33, 0xfb);
|
|
|
|
techpoint_write_reg(client, 0x35, 0x65);
|
|
techpoint_write_reg(client, 0x38, 0x00);
|
|
techpoint_write_reg(client, 0x39, 0x04);
|
|
#endif
|
|
tp9951_set_mipi_out(client, reso, MIPI_2LANE); // 2 lane
|
|
|
|
break;
|
|
case TECHPOINT_S_RESO_NTSC:
|
|
#if TP9951_DEF_NTSC
|
|
default:
|
|
#endif
|
|
|
|
#if CVBS_960H
|
|
dev_err(&client->dev, "set channel NTSC CVBS_960H\n");
|
|
techpoint_write_reg(client, 0x02, 0x47);
|
|
techpoint_write_reg(client, 0x0c, 0x13);
|
|
techpoint_write_reg(client, 0x0d, 0x50);
|
|
|
|
techpoint_write_reg(client, 0x15, 0x13);
|
|
techpoint_write_reg(client, 0x16, 0x60);
|
|
techpoint_write_reg(client, 0x17, 0x80);
|
|
techpoint_write_reg(client, 0x18, 0x12);
|
|
techpoint_write_reg(client, 0x19, 0xf0);
|
|
techpoint_write_reg(client, 0x1a, 0x07);
|
|
techpoint_write_reg(client, 0x1c, 0x09);
|
|
techpoint_write_reg(client, 0x1d, 0x38);
|
|
|
|
techpoint_write_reg(client, 0x20, 0x40);
|
|
techpoint_write_reg(client, 0x21, 0x84);
|
|
techpoint_write_reg(client, 0x22, 0x36);
|
|
techpoint_write_reg(client, 0x23, 0x3c);
|
|
|
|
techpoint_write_reg(client, 0x2b, 0x70);
|
|
techpoint_write_reg(client, 0x2c, 0x2a);
|
|
techpoint_write_reg(client, 0x2d, 0x68);
|
|
techpoint_write_reg(client, 0x2e, 0x57);
|
|
|
|
techpoint_write_reg(client, 0x30, 0x62);
|
|
techpoint_write_reg(client, 0x31, 0xbb);
|
|
techpoint_write_reg(client, 0x32, 0x96);
|
|
techpoint_write_reg(client, 0x33, 0xc0);
|
|
|
|
techpoint_write_reg(client, 0x35, 0x65);
|
|
techpoint_write_reg(client, 0x38, 0x00);
|
|
techpoint_write_reg(client, 0x39, 0x04);
|
|
#else
|
|
dev_err(&client->dev, "set channel NTSC 720H\n");
|
|
techpoint_write_reg(client, 0x02, 0x47);
|
|
techpoint_write_reg(client, 0x0c, 0x13);
|
|
techpoint_write_reg(client, 0x0d, 0x50);
|
|
|
|
techpoint_write_reg(client, 0x15, 0x03);
|
|
techpoint_write_reg(client, 0x16, 0xd6);
|
|
techpoint_write_reg(client, 0x17, 0xa0);
|
|
techpoint_write_reg(client, 0x18, 0x12);
|
|
techpoint_write_reg(client, 0x19, 0xf0);
|
|
techpoint_write_reg(client, 0x1a, 0x05);
|
|
techpoint_write_reg(client, 0x1c, 0x06);
|
|
techpoint_write_reg(client, 0x1d, 0xb4);
|
|
|
|
techpoint_write_reg(client, 0x20, 0x40);
|
|
techpoint_write_reg(client, 0x21, 0x84);
|
|
techpoint_write_reg(client, 0x22, 0x36);
|
|
techpoint_write_reg(client, 0x23, 0x3c);
|
|
|
|
techpoint_write_reg(client, 0x2b, 0x70);
|
|
techpoint_write_reg(client, 0x2c, 0x2a);
|
|
techpoint_write_reg(client, 0x2d, 0x4b);
|
|
techpoint_write_reg(client, 0x2e, 0x57);
|
|
|
|
techpoint_write_reg(client, 0x30, 0x62);
|
|
techpoint_write_reg(client, 0x31, 0xbb);
|
|
techpoint_write_reg(client, 0x32, 0x96);
|
|
techpoint_write_reg(client, 0x33, 0xcb);
|
|
|
|
techpoint_write_reg(client, 0x35, 0x65);
|
|
techpoint_write_reg(client, 0x38, 0x00);
|
|
techpoint_write_reg(client, 0x39, 0x04);
|
|
#endif
|
|
break;
|
|
}
|
|
|
|
#if TECHPOINT_TEST_PATTERN
|
|
techpoint_write_reg(client, 0x2a, 0x3c);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
// detect for reference only, the accuracy may be affected by the current invoked decoding standard.
|
|
int tp9951_get_channel_reso(struct i2c_client *client, int ch)
|
|
{
|
|
u8 detect_fmt = 0xff;
|
|
u8 reso = 0xff;
|
|
|
|
techpoint_write_reg(client, 0x40, ch);
|
|
techpoint_read_reg(client, 0x03, &detect_fmt);
|
|
reso = detect_fmt & 0x7; // CVSTD[2-0]
|
|
|
|
switch (reso) {
|
|
case TP9951_CVSTD_720P_25:
|
|
#if TP9951_DEF_720P
|
|
default:
|
|
#endif
|
|
dev_err(&client->dev, "detect channel %d 720P_25\n", ch);
|
|
return TECHPOINT_S_RESO_720P_25;
|
|
case TP9951_CVSTD_1080P_25:
|
|
#if TP9951_DEF_1080P
|
|
default:
|
|
#endif
|
|
dev_err(&client->dev, "detect channel %d 1080P_25\n", ch);
|
|
return TECHPOINT_S_RESO_1080P_25;
|
|
case TP9951_CVSTD_PAL:
|
|
#if TP9951_DEF_PAL
|
|
default:
|
|
#endif
|
|
dev_err(&client->dev, "detect channel %d PAL\n", ch);
|
|
return TECHPOINT_S_RESO_PAL;
|
|
case TP9951_CVSTD_NTSC:
|
|
#if TP9951_DEF_NTSC
|
|
default:
|
|
#endif
|
|
dev_err(&client->dev, "detect channel %d NTSC\n", ch);
|
|
return TECHPOINT_S_RESO_NTSC;
|
|
}
|
|
|
|
return reso;
|
|
}
|
|
|
|
int tp9951_set_quick_stream(struct i2c_client *client, u32 stream)
|
|
{
|
|
if (stream) {
|
|
techpoint_write_reg(client, PAGE_REG, 0x08);
|
|
techpoint_write_reg(client, 0x28, 0x00);
|
|
} else {
|
|
techpoint_write_reg(client, PAGE_REG, 0x08);
|
|
techpoint_write_reg(client, 0x28, 0x02);
|
|
usleep_range(40 * 1000, 50 * 1000);
|
|
}
|
|
return 0;
|
|
}
|