282 lines
6.8 KiB
Plaintext
282 lines
6.8 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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menu "TI OMAP/AM/DM/DRA Family"
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depends on ARCH_MULTI_V6 || ARCH_MULTI_V7
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config OMAP_HWMOD
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bool
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config ARCH_OMAP2
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bool "TI OMAP2"
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depends on ARCH_MULTI_V6
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select ARCH_OMAP2PLUS
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select CPU_V6
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select OMAP_HWMOD
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select SOC_HAS_OMAP2_SDRC
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config ARCH_OMAP3
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bool "TI OMAP3"
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depends on ARCH_MULTI_V7
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select ARCH_OMAP2PLUS
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select ARM_CPU_SUSPEND
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select OMAP_HWMOD
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select OMAP_INTERCONNECT
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select PM_OPP
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select SOC_HAS_OMAP2_SDRC
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select ARM_ERRATA_430973
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config ARCH_OMAP4
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bool "TI OMAP4"
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depends on ARCH_MULTI_V7
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select ARCH_OMAP2PLUS
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select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
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select ARM_CPU_SUSPEND
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select ARM_ERRATA_720789
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select ARM_GIC
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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select OMAP_INTERCONNECT
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select OMAP_INTERCONNECT_BARRIER
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select PL310_ERRATA_588369 if CACHE_L2X0
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select PL310_ERRATA_727915 if CACHE_L2X0
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select PM_OPP
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select PM if CPU_IDLE
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select ARM_ERRATA_754322
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select ARM_ERRATA_775420
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select OMAP_INTERCONNECT
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config SOC_OMAP5
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bool "TI OMAP5"
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depends on ARCH_MULTI_V7
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select ARCH_OMAP2PLUS
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select ARM_CPU_SUSPEND
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select ARM_GIC
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_ARCH_TIMER
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select ARM_ERRATA_798181 if SMP
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select OMAP_INTERCONNECT
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select OMAP_INTERCONNECT_BARRIER
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select PM_OPP
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select ZONE_DMA if ARM_LPAE
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config SOC_AM33XX
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bool "TI AM33XX"
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depends on ARCH_MULTI_V7
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select ARCH_OMAP2PLUS
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select ARM_CPU_SUSPEND
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config SOC_AM43XX
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bool "TI AM43x"
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depends on ARCH_MULTI_V7
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select ARCH_OMAP2PLUS
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select ARM_GIC
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select MACH_OMAP_GENERIC
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select HAVE_ARM_SCU
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select GENERIC_CLOCKEVENTS_BROADCAST
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select HAVE_ARM_TWD
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select ARM_ERRATA_754322
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select ARM_ERRATA_775420
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select OMAP_INTERCONNECT
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select ARM_CPU_SUSPEND
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config SOC_DRA7XX
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bool "TI DRA7XX"
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depends on ARCH_MULTI_V7
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select ARCH_OMAP2PLUS
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select ARM_CPU_SUSPEND
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select ARM_GIC
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_ARCH_TIMER
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select IRQ_CROSSBAR
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select ARM_ERRATA_798181 if SMP
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select OMAP_INTERCONNECT
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select OMAP_INTERCONNECT_BARRIER
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select PM_OPP
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select ZONE_DMA if ARM_LPAE
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select PINCTRL_TI_IODELAY if OF && PINCTRL
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config ARCH_OMAP2PLUS
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bool
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select ARCH_HAS_BANDGAP
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select ARCH_HAS_RESET_CONTROLLER
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select ARCH_OMAP
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select CLKSRC_MMIO
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select GENERIC_IRQ_CHIP
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select GPIOLIB
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select MACH_OMAP_GENERIC
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select MEMORY
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select MFD_SYSCON
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select OMAP_DM_SYSTIMER
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select OMAP_DM_TIMER
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select OMAP_GPMC
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select PINCTRL
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select PM
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select PM_GENERIC_DOMAINS
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select PM_GENERIC_DOMAINS_OF
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select RESET_CONTROLLER
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select SOC_BUS
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select TI_SYSC
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select OMAP_IRQCHIP
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select CLKSRC_TI_32K
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help
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Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
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config OMAP_INTERCONNECT_BARRIER
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bool
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select ARM_HEAVY_MB
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config ARCH_OMAP
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bool
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if ARCH_OMAP2PLUS
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menu "TI OMAP2/3/4 Specific Features"
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config ARCH_OMAP2PLUS_TYPICAL
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bool "Typical OMAP configuration"
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default y
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select AEABI
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select HIGHMEM
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select I2C
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select I2C_OMAP
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select MENELAUS if ARCH_OMAP2
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select NEON if CPU_V7
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select REGULATOR
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select REGULATOR_FIXED_VOLTAGE
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select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
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select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
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select VFP
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help
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Compile a kernel suitable for booting most boards
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config SOC_HAS_OMAP2_SDRC
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bool "OMAP2 SDRAM Controller support"
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config SOC_HAS_REALTIME_COUNTER
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bool "Real time free running counter"
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depends on SOC_OMAP5 || SOC_DRA7XX
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default y
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config POWER_AVS_OMAP
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bool "AVS(Adaptive Voltage Scaling) support for OMAP IP versions 1&2"
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depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
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select POWER_SUPPLY
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help
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Say Y to enable AVS(Adaptive Voltage Scaling)
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support on OMAP containing the version 1 or
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version 2 of the SmartReflex IP.
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V1 is the 65nm version used in OMAP3430.
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V2 is the update for the 45nm version of the IP used in OMAP3630
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and OMAP4430
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Please note, that by default SmartReflex is only
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initialized and not enabled. To enable the automatic voltage
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compensation for vdd mpu and vdd core from user space,
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user must write 1 to
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/debug/smartreflex/sr_<X>/autocomp,
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where X is mpu_iva or core for OMAP3.
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Optionally autocompensation can be enabled in the kernel
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by default during system init via the enable_on_init flag
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which an be passed as platform data to the smartreflex driver.
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config POWER_AVS_OMAP_CLASS3
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bool "Class 3 mode of Smartreflex Implementation"
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depends on POWER_AVS_OMAP && TWL4030_CORE
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help
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Say Y to enable Class 3 implementation of Smartreflex
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Class 3 implementation of Smartreflex employs continuous hardware
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voltage calibration.
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config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
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bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
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depends on ARCH_OMAP3 && PM
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help
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Without this option, L2 Auxiliary control register contents are
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lost during off-mode entry on HS/EMU devices. This feature
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requires support from PPA / boot-loader in HS/EMU devices, which
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currently does not exist by default.
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config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
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int "Service ID for the support routine to set L2 AUX control"
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depends on OMAP3_L2_AUX_SECURE_SAVE_RESTORE
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default 43
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help
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PPA routine service ID for setting L2 auxiliary control register.
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comment "OMAP Core Type"
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depends on ARCH_OMAP2
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config SOC_OMAP2420
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bool "OMAP2420 support"
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depends on ARCH_OMAP2
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default y
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select OMAP_DM_SYSTIMER
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select OMAP_DM_TIMER
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select SOC_HAS_OMAP2_SDRC
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config SOC_OMAP2430
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bool "OMAP2430 support"
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depends on ARCH_OMAP2
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default y
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select SOC_HAS_OMAP2_SDRC
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config SOC_OMAP3430
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bool "OMAP3430 support"
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depends on ARCH_OMAP3
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default y
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select SOC_HAS_OMAP2_SDRC
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config SOC_TI81XX
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bool "TI81XX support"
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depends on ARCH_OMAP3
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default y
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comment "OMAP Legacy Platform Data Board Type"
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depends on ARCH_OMAP2PLUS
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config MACH_OMAP_GENERIC
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bool
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config MACH_OMAP2_TUSB6010
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bool
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depends on ARCH_OMAP2 && SOC_OMAP2420
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default y if MACH_NOKIA_N8X0
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config MACH_NOKIA_N810
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bool
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config MACH_NOKIA_N810_WIMAX
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bool
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config MACH_NOKIA_N8X0
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bool "Nokia N800/N810"
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depends on SOC_OMAP2420
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default y
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select MACH_NOKIA_N810
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select MACH_NOKIA_N810_WIMAX
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config OMAP3_SDRC_AC_TIMING
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bool "Enable SDRC AC timing register changes"
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depends on ARCH_OMAP3
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help
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If you know that none of your system initiators will attempt to
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access SDRAM during CORE DVFS, select Y here. This should boost
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SDRAM performance at lower CORE OPPs. There are relatively few
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users who will wish to say yes at this point - almost everyone will
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wish to say no. Selecting yes without understanding what is
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going on could result in system crashes;
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endmenu
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endif
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config OMAP5_ERRATA_801819
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bool "Errata 801819: An eviction from L1 data cache might stall indefinitely"
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depends on SOC_OMAP5 || SOC_DRA7XX
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help
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A livelock can occur in the L2 cache arbitration that might prevent
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a snoop from completing. Under certain conditions this can cause the
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system to deadlock.
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endmenu
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