156 lines
3.1 KiB
Plaintext
156 lines
3.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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*
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*/
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/ {
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pwm_rockchip_test: pwm-rockchip-test {
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compatible = "pwm-rockchip-test";
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pwms = <&pwm0_2ch_0 0 25000 0>,
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<&pwm0_2ch_1 0 25000 0>,
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<&pwm1_6ch_0 0 25000 0>,
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<&pwm1_6ch_1 0 25000 0>,
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<&pwm1_6ch_2 0 25000 0>,
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<&pwm1_6ch_3 0 25000 0>,
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<&pwm1_6ch_4 0 25000 0>,
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<&pwm1_6ch_5 0 25000 0>,
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<&pwm2_8ch_0 0 25000 0>,
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<&pwm2_8ch_1 0 25000 0>,
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<&pwm2_8ch_2 0 25000 0>,
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<&pwm2_8ch_3 0 25000 0>,
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<&pwm2_8ch_4 0 25000 0>,
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<&pwm2_8ch_5 0 25000 0>,
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<&pwm2_8ch_6 0 25000 0>,
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<&pwm2_8ch_7 0 25000 0>;
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pwm-names = "pwm0_0",
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"pwm0_1",
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"pwm1_0",
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"pwm1_1",
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"pwm1_2",
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"pwm1_3",
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"pwm1_4",
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"pwm1_5",
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"pwm2_0",
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"pwm2_1",
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"pwm2_2",
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"pwm2_3",
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"pwm2_4",
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"pwm2_5",
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"pwm2_6",
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"pwm2_7";
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};
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};
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&pwm0_2ch_0 {
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status = "okay";
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pinctrl-0 = <&pwm0m0_ch0>;
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assigned-clocks = <&cru CLK_PMU1PWM>;
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assigned-clock-rates = <100000000>;
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};
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&pwm0_2ch_1 {
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status = "okay";
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pinctrl-0 = <&pwm0m0_ch1>;
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assigned-clocks = <&cru CLK_PMU1PWM>;
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assigned-clock-rates = <100000000>;
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};
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&pwm1_6ch_0 {
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status = "okay";
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pinctrl-0 = <&pwm1m0_ch0>;
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assigned-clocks = <&cru CLK_PWM1>;
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assigned-clock-rates = <100000000>;
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};
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&pwm1_6ch_1 {
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status = "okay";
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pinctrl-0 = <&pwm1m0_ch1>;
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assigned-clocks = <&cru CLK_PWM1>;
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assigned-clock-rates = <100000000>;
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};
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&pwm1_6ch_2 {
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status = "okay";
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pinctrl-0 = <&pwm1m0_ch2>;
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assigned-clocks = <&cru CLK_PWM1>;
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assigned-clock-rates = <100000000>;
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};
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&pwm1_6ch_3 {
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status = "okay";
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pinctrl-0 = <&pwm1m0_ch3>;
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assigned-clocks = <&cru CLK_PWM1>;
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assigned-clock-rates = <100000000>;
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};
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&pwm1_6ch_4 {
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status = "okay";
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pinctrl-0 = <&pwm1m0_ch4>;
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assigned-clocks = <&cru CLK_PWM1>;
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assigned-clock-rates = <100000000>;
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};
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&pwm1_6ch_5 {
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status = "okay";
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pinctrl-0 = <&pwm1m0_ch5>;
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assigned-clocks = <&cru CLK_PWM1>;
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assigned-clock-rates = <100000000>;
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};
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&pwm2_8ch_0 {
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status = "okay";
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pinctrl-0 = <&pwm2m0_ch0>;
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assigned-clocks = <&cru CLK_PWM2>;
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assigned-clock-rates = <100000000>;
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};
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&pwm2_8ch_1 {
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status = "okay";
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pinctrl-0 = <&pwm2m0_ch1>;
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assigned-clocks = <&cru CLK_PWM2>;
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assigned-clock-rates = <100000000>;
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};
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&pwm2_8ch_2 {
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status = "okay";
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pinctrl-0 = <&pwm2m0_ch2>;
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assigned-clocks = <&cru CLK_PWM2>;
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assigned-clock-rates = <100000000>;
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};
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&pwm2_8ch_3 {
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status = "okay";
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pinctrl-0 = <&pwm2m0_ch3>;
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assigned-clocks = <&cru CLK_PWM2>;
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assigned-clock-rates = <100000000>;
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};
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&pwm2_8ch_4 {
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status = "okay";
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pinctrl-0 = <&pwm2m0_ch4>;
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assigned-clocks = <&cru CLK_PWM2>;
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assigned-clock-rates = <100000000>;
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};
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&pwm2_8ch_5 {
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status = "okay";
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pinctrl-0 = <&pwm2m0_ch5>;
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assigned-clocks = <&cru CLK_PWM2>;
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assigned-clock-rates = <100000000>;
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};
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&pwm2_8ch_6 {
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status = "okay";
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pinctrl-0 = <&pwm2m0_ch6>;
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assigned-clocks = <&cru CLK_PWM2>;
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assigned-clock-rates = <100000000>;
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};
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&pwm2_8ch_7 {
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status = "okay";
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pinctrl-0 = <&pwm2m0_ch7>;
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assigned-clocks = <&cru CLK_PWM2>;
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assigned-clock-rates = <100000000>;
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};
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